On Fri, Apr 22, 2016 at 9:29 PM, Sean Conner <s...@conman.org> wrote: > One major problem with adding a faster CPU to an SGI is the MIPS chip > itself---code compiled for one MIPS CPU (say, the R3000) won't run on > another MIPS CPU (say, the R4400) due to the differences in the pipeline. > MIPS compilers were specific for a chip because such details were not hidden > in the CPU itself, but left to the compiler to deal with.
Having written a bunch of R3000 and R4000/4200/4300/4400/4600 assembly code in the 1990s, my (possibly faulty) recollection disagrees with you. There are differences in supervisor-mode programming, but I don't recall any issues with running 32-bit user-mode R3000 code on any R4xxx. The programmer-visible pipelline behavior (e.g., branch delay slots) were the same. That's only considering the CPU itself, which I used as an embedded processor; I never used IRIX so I don't know whether IRIX on R4xxx might have somehow prevented use of IRIX R3xxx binaries (e.g., by different system call conventions or the like).
