> On Jul 20, 2016, at 1:34 PM, Cameron Kaiser <spec...@floodgap.com> wrote:
>
>> Also, RISC does not use, or need, microcode.
>
> I'm not sure what you mean by this, but (for example) many POWER
> implementations have microcode (example: the 970/G5, which is descended from
> POWER4).
What I meant is that I had no idea such things existed. Very curious. Learn
something new every day. What do they use this for?
The closest to microcode I'd ever heard of before is the "epicode" in Alpha.
Or was that Prism? Anyway, a DEC RISC architecture where some privileged stuff
was done in code running in a corner of the chip. Not actual microcode because
it was essentially the standard instruction set, somewhat extended and running
in a special processor state.
paul
