> On Sep 1, 2016, at 12:56 AM, Eric Smith <space...@gmail.com> wrote:
>
> On Wed, Aug 31, 2016 at 6:42 AM, Paul Koning <paulkon...@comcast.net> wrote:
>> Yes, the one I saw when I made that comment is an MSM51V18165F by Lapis, a
>> 1M by 16 "fast page mode" EDO DRAM.
>
> If it's EDO, it may not be compatible with systems that weren't
> designed for EDO, and since none of the 16-pin parts were EDO, I'd
> avoid it.
>
> "Normal" and FPM memory stops driving the data output when CAS is
> deasserted, regardless of the state of RAS. EDO continues driving the
> data output even with CAS deasserted, unless RAS is also deasserted.
The ISSI memory calls itself "DRAM with fast page mode", it does not say "EDO".
But judging from the timing diagrams (which show that data out turns off after
the later of RAS and CAS deassertion) it sounds like "fast page mode" is a
confusing way to say "EDO".
Now the question becomes what the Pro actually does. I don't see it in the
documentation or schematics, unfortunately.
Incidentally, the Pro technical manual says that the daughterboard can be up to
2 MB (but DEC only offers 512 kB). It doesn't say how that is done. It looks
like the answer is that there are four RAS signals, so you can have four banks,
256k by 16 each.
paul
