On Tue, Sep 6, 2016 at 12:11 PM, Marc Howard <cramc...@gmail.com> wrote: > It seems to me that one possible solution would be to whip up a PLL in a > CPLD or FPGA to generate 12 sector timing from a 16 sector pack or vice > versa.
This is one of the recurring conversations here - 12-sector packs are abundant compared to 16-sector packs, and the only difference is the slits in the hub and the consequent formatting on the matching controller... -ethan
