On 06/13/2017 05:29 PM, Eric Smith wrote: > It's mathematically impossible for a normal UART [*] to handle 49% > timing error. The cumulative timebase error by the end of a > character can't be more than one bit time, or the wrong bit will get > sampled, resulting in incorrect data, or, (if that happens on the > stop bit) a possible framing error. For 8N1 [**], there are 10 bits > in total (including start and stop), so that's an absolute maximum > timing error of 10%, but for various reasons even 10% speed variation > won't actually work in practice. If they meant 4.9%, that is > believable, but even that won't work if the other side is more than > slightly off-speed in the other direction. Normal spec is a maximum > timing variation of within +/-2% at each end [***], so that things > still work properly if one side is at +2% and the other is at -2%,
Well, I didn't say "timing error", I did say "timing distortion", which is not quite the same thing. My reference was the "TR1602/TR1863/TR1865 MOS/LSI Application Notes Asynchronous Receiver Transmitter", which can be found in the WD 1984 Data Communications Handbook (I think there's a copy online). Page 126-127. "Thus, signals with up to 46.875% distortion could be received." Perhaps this is in error; I'll let you decide. I can say, however, that once I set the trimmer on the 555, I didn't touch it for a couple of years (eventually replacing the TVT with a real terminal). Obviously, the developer of the subject board didn't have much of a problem either; or else he wouldn't be able to sell the thing. --Chuck
