> On Oct 27, 2017, at 1:47 PM, Rob Jarratt <robert.jarr...@ntlworld.com> wrote:
>
> If I had the skill, data and time, I would always go for a gate level model.
> However, I do most (sim/em)ulation in SIMH instead, like I have been doing
> for MU5 where I lack the data and the time and probably the skill as well,
> but I can always acquire the skill, the other two are harder to find.
I've read some VHDL before, but my 6600 gate level model was my first VHDL
project. It's actually quite easy, easier than the level of fluency needed to
do a good behavioral model. A decent textbook helps a lot. My favorite is The
Designer's Guide to VHDL by Peter Ashenden. The point is that modeling small
modules (SSI gates, or 6600 "cordwood" modules, or the like) is easy because
they are small and have quite simple behavior. Then it's just a matter of
wiring them together.
Note that you don't need an FPGA to do logic level design; all you need is a
VHDL simulator. I use GHDL, which is open source, part of GCC so you can hook
in C code if you need it. For example, that allows you to make a model of the
I/O channel and connect it to a SIMH style emulation of a peripheral device.
The real issue for gate level modeling is the availability of the necessary
documentation. If you have schematics, and they includes critical detail such
as microcode ROM contents, you're all set. If all you have is functional
specs, you can't even start.
It helps to have a machine built with sane design principles. Things like RS
flops that don't have both inputs active at the same time. And a properly
clocked architecture. Neither of these properties holds for the CDC 6600...
paul
