On 10/27/2017 1:06 PM, Paul Koning wrote:
True if you have a TTL machine. 6600 is discrete transistor, and the actual
transistor specs are nowhere to be found as far as I have been able to tell.
Well if you can find one loose, you could allways measure it.
But that doesn't directly relate to gate level emulation. If you have gate
level documentation you can of course build a copy of the machine out of actual
gate-type parts, like 7400 chips. Or you can write a gate level model in VHDL,
which is not the most popular form but certainly perfectly straightforward.
Either way, though, you have to start with a document that shows what the gates
are in the original and how they connect. And to get it to work, you need to
deal with timing issues and logic abuse, if present. In the 6600, both are
very present and very critical. For example, I've been debugging a section
(the central processor branch logic) where the behavior changes quite
substantially depending on whether you favor S or R in an R/S flop, i.e., if
both are asserted at the same time, who wins? And the circuit and wire delays
matter, down to the few-nanosecond level.
You need to find a lucky man, for help. You stand here, and look that
way. Yes it works.
Most machines are not so crazy; I would assume a PDP-11/20 gate level model
would be quite painless.
paul
I still have not figured out VHDL yet. Logic that I can figure out, but
how you use the the stupid
logic blocks I can not with all the stupid type defines. What I need is
real reference book, not a DUMMYS GUIDE TO BLA-BLA-BLA.
For my own hobby stuff I am useing WINCPUL and ALTERA's AHDL. There a D
F/F is D flip flop.
Ben.
