On 11/17/2017 7:25 PM, Paul Koning wrote:
One key question is whether it should be asynchronous, as the Unibus is, or
synchronous.
I thought synchronous would make for a smaller/simpler design, but could
be wrong.
A synchronous version of the Unibus would be quite easy; all the funny one-shot
delays would disappear and actions would simply be taken on the clock edge
(rising or falling, pick one). Just make the clock period comfortably longer
than the worst case propagation delay and you're in business.
Given the CPU landscape, I am thinking < 10MHz, which would seem to
satisfy the criteria.
I'm assuming it doesn't need to be all that fast. If you clock period > prop
delay is an issue, things get vastly more complicated. If so, you might want to
stick with something that's already been sorted out, like PCIe.
It does not have to be fast. I rather thought, "what is the simplest
multi-cpu shared bus that could be easily understood by folks and allow
them to focus on multi-processing education, not bus understanding"
Jim
