On Sat, Mar 2, 2019 at 12:02 PM Joseph Zatarski via cctalk <cctalk@classiccmp.org> wrote: > > On a somewhat related note, I don't suppose anybody knows or has > documentation on the pinout of the C/D interconnect on these RAM boards? > The pinout for the ribbon cable is in the manual, but the C/D > interconnect doesn't seem to be documented in any of the manuals that > are online.
650QS Field Maintenance Print Set, MP-02538-01, Rev C1 http://www.bitsavers.org/pdf/dec/vax/650/MP02538_650QS_Sep88.pdf Page 65 of the PDF, KA650 Circuit Schematics Page 23 of 40 MA0 - MA9 CAS0 - CAS3 RAS0 - RAS3 WE SE XADDR20, XADDR21 +5 GND Page 47 of the PDF, Page 5 of 40 is an overview block diagram of those signals originating at the DC357 CMCTL Memory System Controller.