I believe I read they weaved the planes this way to minimize crosstalk, EMI or heat.
=] On Thu, Apr 18, 2019, 1:13 PM Paul Koning via cctalk <cctalk@classiccmp.org> wrote: > > > > On Apr 18, 2019, at 11:47 AM, Jon Elson via cctalk < > cctalk@classiccmp.org> wrote: > > > > On 04/18/2019 04:49 AM, Brent Hilpert via cctalk wrote: > >> It's a 4-wire 3D planar array. By topology and construction I would > guess it date it from the 60s. > > Make that EARLY '60s. As soon as somebody figured out that you could > combine the sense and inhibit wires, everybody immediately went to 3-wire > planes. > > > > Jon > > Is that true even for the highest speed designs? > > CDC 6000 series memory is unusual in that it has 5 wires per core. > Instead of the classic X, Y, Inhibit, Sense it has two inhibit wires, > routed in the X and Y direction. There are four X and four Y inhibit > wires, each of which run through 1/4th of the cores, so a given inhibit > pair acts on 1/16th of the cores. > > The documentation doesn't spell out why this is done. My guess is that it > makes the various driven wires more alike in how many cores they pass > through. X and Y, in the 12 bit stack, pass through 64 * 12 cores. Each > inhibit wire passes through 64 * 16 cores, i.e., nearly the same number. > And the driver circuits for all these wires are the same. > > A regular full-plane inhibit wire would pass through 4k cores, meaning the > inductance is far higher than that of the X and Y wires. So either the > drive circuit would require a lot more power, or it would be significantly > slower than the X/Y drive. > > As for separate sense, split inhibit obviously requires that, but even > with conventional inhibit, keeping sense separate avoids the overhead of > switching the signal path between two very different bits of circuitry. > > Compared to many other core memory designs of that same era, the 6000 > memory is quite fast, with access times of a few hundred nanoseconds and > full cycle (read plus restore) in one microsecond. Actually, comfortably > under 1 microsecond, allowing for magic like read and update in one cycle > (for the exchange instruction in the CPU) or read and write new data in one > cycle via the ALU data path (in the PPUs). I suspect the unusual core > plane design was a factor in making this speed possible. > > paul > >