On 6/15/19 7:47 AM, Stefan Skoglund wrote: > > With VAX 11/780 and S/360 involved ? I don't think so soo > the Cyber series and 709(4) could be interesting.
It's difficult to say exactly, because of the constraints on the definition. Or does something have to be RISC only if it came after the definition? One of the issues with much older systems is that register memory was very expensive--and the corollary, of course, is that memory in general was expensive and a bottleneck. So, for example, the IBM 7030, with all of its very advanced architecture, remains out of the picture, because of its single-accumulator architecture. I don't think I'd call a 7090 a RISC architecture, either. There are plenty of early simple-architecture systems, (e.g. IBM 1130) that fail to qualify under the RISC definition because of this. One detail about the CDC 6000 that escapes many people is that there are no condition codes for branches. Given a three-address architecture, there's no "compare" instruction either (absent the CMU add-on). If you want to compare, say, registers X1 and X2 for equality, your code might look like this: IX0 X1-X2 ZR X0,equal-target The peculiar advantage of this is that condition codes don't come into the picture for the purposes of instruction scheduling--one simply uses the normal result reservation mechanism. The "compare" (IX0) above, can be anywhere in the preceding instruction stream before the zero jump. --Chuck