On 8/28/20 1:10 PM, Paul Koning wrote:
SD is a packet based storage device on a serial interconnect, minimally one lane wide but it can also be four lanes (and that's typically how you use it). Apparently it starts out in a SPI compatible mode, interesting. Also, SD requires a rather complex handshake at power up to get to the point where you can do I/O.
I've implemented the SPI protocol in a little micro-coded engine on an FPGA and have considered upgrading it to the standard interface over one to four lanes except it looks like the SD licensing says I'm not supposed to do that without paying them a bunch of money. And yeah, it took me a while to work through the initialization dance and it still fails from time to time (and from SD card to SD card).
However ...
One oddity I remember from a decade ago is that it has a high speed mode where the clock speed is doubled. That's not strange. What's strange is that when you do this, the device switches from clocking data on the rising edge to clocking on the falling edge, or the other way around, I don't remember which. Fortunately I wasn't the hardware designer who had to cope with all that strangeness.
... this I had totally missed. Doubling the clock speed (from 25 to 50 MHz) would be relatively easy (once I'm not running this over long ribbon cable) but switching the clock around like that would have really confused me, I think. Thanks for the heads-up.
There's some other speed increase (UHS) that comes along with also dropping from 3.3V down to 1.8V. I don't know how to program FPGAs to do that or even know if they can.
