Very impressive. Congratulations! Marc
> On Jul 11, 2023, at 3:23 AM, Jay Jaeger via cctalk <cctalk@classiccmp.org> > wrote: > > Over the past couple of months I have been working on my FPGA implementation > of the IBM 1410 1960's era pre System/360 system again. I am pleased to share > that the CPU now passes a significant diagnostic, CU01, which tests almost > all of the instructions, and also tests I/O with overlap and the priority > feature (interrupts). Also, it runs at generally the same speed as the > original machine (comparing the IBM estimates for 1000 passes), using the > same logic as the original machine (though no doubt optimized by the process > of taking in VHDL logic statements and turning combinatorial logic into > lookup tables (LUTs), and some additions of "D" flip flops to avoid race > conditions in latches and logic loops.) > > (The speed is the same because its "oscillator" - crystal controlled in the > original - is now a clock divider/counter off of the FPGA chip clock.) > > For more details, see > > https://www.computercollection.net/index.php/ibm-1410-fpga-implementation/ > > Mostly the ALD (Automated Logic Diagram) data capture seems to have been very > accurate. I really only had to do four things this year to get it to this > point: > > - Make the necessary logic gate deletions / changes for configuration > option S40/$40 - 40K of core > - Add the ability to transfer a core image from the PC support program > to the FPGA. > - Fix some issues in the Assembly Channel because while almost all of > the ALDs are for a 1410 with the Accelerator feature, several pages of > the very important Assembly channel were for the base 1410 model. > - Deal with a race condition during overlapped I/O > > These are generally discussed in individual blog posts off the above link. > > I really was quite happily surprised that when capturing the data on over two > hundred ALDs with over 10,000 logic gates, over 4,200 individual unique > signals, more than 12,000 signal names on individual ALDs, and more than > 32,000 interconnections that there were not a lot more problems than these. > (I may run into some as yet undiscovered errors involving the channels as I > add I/O devices, though). > > I suppose that there were not more problems because for most of the > individual sheets and in many cases groups of sheets I wrote VHDL test > benches using the Intermediate Logic Diagrams (ILDs) as a guide, and of > course took considerable care during the data entry process from the ALDs, > checking connection counts on each logic block, for example. > > The last post ("Off to the Races") on the aforementioned web page also > discusses the next expected steps: some more work on the PC/Console support > program, more diagnostic tests, other support program enhancements, and > figuring out how to go about I/O, especially since I don't have ALDs for the > 1414 I/O Synchronizers. > > But I no longer have any doubts about the viability of this process, so long > as the FPGA logic clock is somewhere around 10x the logic clock of the > simulated machine. (I expect to try and "push it" by speeding up the 1410 > logic clock to see at what ratio of the FPGA clock to the CPU clock things > break down, as well). > > JRJ
