> On Sep 1, 2023, at 2:18 PM, Adrian Godwin via cctalk <cctalk@classiccmp.org>
> wrote:
>
> Interesting that processors are getting wider and wider, whilst (perhaps
> not in the same timeframe) we have moved away from parallel interfaces
> towards serial ones. I know there are reasons for that in
> operations-per-cycle and the difficulty of synchronising wide busses
> off-chip but I wonder if those sweetspots will change again.
I remember when, in the early days of Ethernet (1981 or so) someone in DEC
suggested moving towards Ethernet as the I/O interconnect. That didn't go
anywhere -- which makes sense if you remember an Ethernet interface in those
days looked like a DEUNA -- two hex boards -- and run at only 10 Mb/s. Of
course it wasn't too many years after that it started to make sense for
terminals (LAT terminal servers), and not long after that at least for some
storage devices (LAVC and InfoServer).
There's actually a pull in two opposite directions. One is to put more stuff
within a chip (System On Chip approach) and make the interconnects inside very
wide, perhaps an entire L1 cache line wide. The Raza/NetLogic/Broadcom XLR and
its successors are a good example, very nice MIPS-64 SOCs. The other is to do
off-chip interconnects serially at very high clock rates.
Of course there are cases where serial isn't fast enough. The fastest
Ethernets are an example, with their multi-lane transceiver buses. Another is
the JESD204 standard, used in signal processing to connect A/D and D/A
converters, where you might be looking at multiple analog data streams, 14-16
bits wide, multiple Gsamples/second. That might takes 2-8 serial links working
together. For those, there isn't a requirement for alignment of the bits
across the wires, instead the data streams are reconstructed serially for each
lane and then aligned properly to form the words. So within reason the lanes
may have different propagation delay and still work.
paul
