On Fri, 19 Sep 2025, Robert Marinelli wrote:
So looking through the pseudo-schematics/block diagrams in SY31-0552-3 IBM
5110 System Logic there is quite a bit of gate logic on the multiple ROS
cards, plenty of wires between them. Maybe, hardware interrupts are held off
in hardware when we are doing reads from the language ROS cards. The
interrupt bits are properly shown in a register, but nothing detailing gating
of interrupt -> CPU.
Hm, this is a very good point! Actually, thinking about it, the system
ISRs are located in the ExecROS (e.g. keyboard ISR), so you may be correct
about "ANDing" the interrupt line with the ExecROS select line, *if* the
interrupt mode bit for that level (i.e. 0-3) says that the ISR is in a
ROS. On the other hand, you can have an ISR in RWS, so that could be
called anytime.
To test the idea I made this change in emu.c:
175c175,176
< check_int(); /* check for pending interrupts */
---
if(curr_ros==ExecROS) /* if in ExecROS we can HOLD/resume */
check_int(); /* check for pending interrupts */
This may break an ISR in RWS, but I haven't tested this with your
modification.
Christian
