see: http://netfpga.org/ The quad gig-E version looks like it works well (in that there are advanced things like DRR available for it) but the underlying FPGA is obsolete. The quad 10GigE version looks sexy but not very functional as yet. In either case, implementing {n,e,s}fq_codel onboard looks very feasible, although something of a larger effort than I'd like to spend personally. (it's been about 6 years since I last touched verilog)
I would be interested however in getting a bunch of hardware hackers together (and getting the academic discount on this board) to try and do an implementation of a fq_codel derivative on the quad 10GigE board. (or I would be happy to learn of some group already doing it) The only thing that is seriously serial about fq_codel is shooting the biggest flow when the queue limit is exceeded, and that could be made embarrassingly parallel with enough gates.There are no doubt other tricky issues. I would like it if we could match the ns2 model entirely... down to the last packet... in the real world. I have few contacts at stanford, presently. https://mailman.stanford.edu/pipermail/netfpga-announce/2012-October/000094.html There are a couple of other alternatives in the GigE space and below on openers.... -- Dave Täht Fixing bufferbloat with cerowrt: http://www.teklibre.com/cerowrt/subscribe.html _______________________________________________ Cerowrt-devel mailing list Cerowrt-devel@lists.bufferbloat.net https://lists.bufferbloat.net/listinfo/cerowrt-devel