[PATCH] [PATCH][X86] Slightly refactor default features for AMD bdver* cpus. Also improve checks for target features in test Preprocessor/predefined-arch-macros.c.

[Andrea Di Biagio]

Hi rnk, craig.topper, qcolombet,

Hi Reid, Quentin (and all),

This patch slightly refactors how clang sets default features for AMD bdver 
cpus.
Method 'getDefaultFeatures' (in Basic/Targets.cpp), already uses a fallthrough 
mechanism to set default features for 'bdver4', bdver3 and bdver2. This patch 
simply adds another fallthrough from case 'CK_BDVER2' to case 'CK_BDVER1'. That 
is because 'bdver2' has the same features available in 'bdver1' plus 
BMI,FMA,F16C and TBM etc.

While at it, I added missing checks for features in test 
predefined-arch-macros.c.
In the case of BTVER2, this patch adds explicit checks for __F16C__, __BMI__ 
and __PCLMUL__.
In the case of BDVER3 and BDVER4, this patch checks for the presence of 
__FSGSBASE__ (added at r221130).

Please let me know if ok to submit.

Thanks,
Andrea

http://reviews.llvm.org/D6134

Files:
  lib/Basic/Targets.cpp
  test/Preprocessor/predefined-arch-macros.c

Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -2326,31 +2326,28 @@
     setFeatureEnabledImpl(Features, "f16c", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
-  case CK_BDVER1:
-    setFeatureEnabledImpl(Features, "xop", true);
-    setFeatureEnabledImpl(Features, "lzcnt", true);
-    setFeatureEnabledImpl(Features, "aes", true);
-    setFeatureEnabledImpl(Features, "pclmul", true);
-    setFeatureEnabledImpl(Features, "prfchw", true);
-    setFeatureEnabledImpl(Features, "cx16", true);
-    break;
   case CK_BDVER4:
     setFeatureEnabledImpl(Features, "avx2", true);
     setFeatureEnabledImpl(Features, "bmi2", true);
     // FALLTHROUGH
   case CK_BDVER3:
     setFeatureEnabledImpl(Features, "fsgsbase", true);
     // FALLTHROUGH
   case CK_BDVER2:
+    setFeatureEnabledImpl(Features, "bmi", true);
+    setFeatureEnabledImpl(Features, "fma", true);
+    setFeatureEnabledImpl(Features, "f16c", true);
+    setFeatureEnabledImpl(Features, "tbm", true);
+    // FALLTHROUGH
+  case CK_BDVER1:
+    setFeatureEnabledImpl(Features, "avx", true);
     setFeatureEnabledImpl(Features, "xop", true);
+    setFeatureEnabledImpl(Features, "fma4", true);
+    setFeatureEnabledImpl(Features, "sse4a", true);
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "aes", true);
     setFeatureEnabledImpl(Features, "pclmul", true);
     setFeatureEnabledImpl(Features, "prfchw", true);
-    setFeatureEnabledImpl(Features, "bmi", true);
-    setFeatureEnabledImpl(Features, "fma", true);
-    setFeatureEnabledImpl(Features, "f16c", true);
-    setFeatureEnabledImpl(Features, "tbm", true);
     setFeatureEnabledImpl(Features, "cx16", true);
     break;
   case CK_C3_2:
Index: test/Preprocessor/predefined-arch-macros.c
===================================================================
--- test/Preprocessor/predefined-arch-macros.c
+++ test/Preprocessor/predefined-arch-macros.c
@@ -1342,8 +1342,11 @@
 // CHECK_BTVER2_M32-NOT: #define __3dNOW__ 1
 // CHECK_BTVER2_M32: #define __AES__ 1
 // CHECK_BTVER2_M32: #define __AVX__ 1
+// CHECK_BTVER2_M32: #define __BMI__ 1
+// CHECK_BTVER2_M32: #define __F16C__ 1
 // CHECK_BTVER2_M32: #define __LZCNT__ 1
 // CHECK_BTVER2_M32: #define __MMX__ 1
+// CHECK_BTVER2_M32: #define __PCLMUL__ 1
 // CHECK_BTVER2_M32: #define __POPCNT__ 1
 // CHECK_BTVER2_M32: #define __PRFCHW__ 1
 // CHECK_BTVER2_M32: #define __SSE2_MATH__ 1
@@ -1365,8 +1368,11 @@
 // CHECK_BTVER2_M64-NOT: #define __3dNOW__ 1
 // CHECK_BTVER2_M64: #define __AES__ 1
 // CHECK_BTVER2_M64: #define __AVX__ 1
+// CHECK_BTVER2_M64: #define __BMI__ 1
+// CHECK_BTVER2_M64: #define __F16C__ 1
 // CHECK_BTVER2_M64: #define __LZCNT__ 1
 // CHECK_BTVER2_M64: #define __MMX__ 1
+// CHECK_BTVER2_M64: #define __PCLMUL__ 1
 // CHECK_BTVER2_M64: #define __POPCNT__ 1
 // CHECK_BTVER2_M64: #define __PRFCHW__ 1
 // CHECK_BTVER2_M64: #define __SSE2_MATH__ 1
@@ -1518,6 +1524,7 @@
 // CHECK_BDVER3_M32: #define __F16C__ 1
 // CHECK_BDVER3_M32: #define __FMA4__ 1
 // CHECK_BDVER3_M32: #define __FMA__ 1
+// CHECK_BDVER3_M32: #define __FSGSBASE__ 1
 // CHECK_BDVER3_M32: #define __LZCNT__ 1
 // CHECK_BDVER3_M32: #define __MMX__ 1
 // CHECK_BDVER3_M32: #define __PCLMUL__ 1
@@ -1550,6 +1557,7 @@
 // CHECK_BDVER3_M64: #define __F16C__ 1
 // CHECK_BDVER3_M64: #define __FMA4__ 1
 // CHECK_BDVER3_M64: #define __FMA__ 1
+// CHECK_BDVER3_M64: #define __FSGSBASE__ 1
 // CHECK_BDVER3_M64: #define __LZCNT__ 1
 // CHECK_BDVER3_M64: #define __MMX__ 1
 // CHECK_BDVER3_M64: #define __PCLMUL__ 1
@@ -1586,6 +1594,7 @@
 // CHECK_BDVER4_M32: #define __F16C__ 1
 // CHECK_BDVER4_M32: #define __FMA4__ 1
 // CHECK_BDVER4_M32: #define __FMA__ 1
+// CHECK_BDVER4_M32: #define __FSGSBASE__ 1
 // CHECK_BDVER4_M32: #define __LZCNT__ 1
 // CHECK_BDVER4_M32: #define __MMX__ 1
 // CHECK_BDVER4_M32: #define __PCLMUL__ 1
@@ -1620,6 +1629,7 @@
 // CHECK_BDVER4_M64: #define __F16C__ 1
 // CHECK_BDVER4_M64: #define __FMA4__ 1
 // CHECK_BDVER4_M64: #define __FMA__ 1
+// CHECK_BDVER4_M64: #define __FSGSBASE__ 1
 // CHECK_BDVER4_M64: #define __LZCNT__ 1
 // CHECK_BDVER4_M64: #define __MMX__ 1
 // CHECK_BDVER4_M64: #define __PCLMUL__ 1

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