Here is a new version with the previous feedback incorporated:
1. Use 'DSC_condition' instead of 'DSC_constexpr'.
2. Delay applying `ActOnFinishFullExpr' until all switch conditions are done.
I ended up unconditionally adding `ActOnFinishFullExpr' for the if, for, while,
and switch cases. There is a small amount of duplication, but it makes the
code easier to follow since you don't have to think about under what conditions
the call happens (and I personally found it difficult to understand why it was
conditional with 'switch' to begin with). Also, it seems to be common practice
to directly call `ActOnFinishFullExpr' in a lot of the other Sema
implementation pieces.
http://reviews.llvm.org/D8978
Files:
lib/Target/AArch64/AArch64TargetMachine.cpp
lib/Target/ARM/ARMTargetMachine.cpp
lib/Target/Mips/MipsTargetMachine.cpp
lib/Target/R600/AMDGPUTargetMachine.cpp
lib/Target/SystemZ/SystemZTargetMachine.cpp
EMAIL PREFERENCES
http://reviews.llvm.org/settings/panel/emailpreferences/
Index: lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetMachine.cpp
+++ lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -115,9 +115,8 @@
}
// Helper function to build a DataLayout string
-static std::string computeDataLayout(StringRef TT, bool LittleEndian) {
- Triple Triple(TT);
- if (Triple.isOSBinFormatMachO())
+static std::string computeDataLayout(const Triple &TT, bool LittleEndian) {
+ if (TT.isOSBinFormatMachO())
return "e-m:o-i64:64-i128:128-n32:64-S128";
if (LittleEndian)
return "e-m:e-i64:64-i128:128-n32:64-S128";
@@ -134,8 +133,8 @@
bool LittleEndian)
// This nested ternary is horrible, but DL needs to be properly
// initialized before TLInfo is constructed.
- : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
- Options, RM, CM, OL),
+ : LLVMTargetMachine(T, computeDataLayout(Triple(TT), LittleEndian), TT, CPU,
+ FS, Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
isLittle(LittleEndian) {
initAsmInfo();
Index: lib/Target/ARM/ARMTargetMachine.cpp
===================================================================
--- lib/Target/ARM/ARMTargetMachine.cpp
+++ lib/Target/ARM/ARMTargetMachine.cpp
@@ -115,11 +115,10 @@
return TargetABI;
}
-static std::string computeDataLayout(StringRef TT, StringRef CPU,
+static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
- const Triple Triple(TT);
- auto ABI = computeTargetABI(Triple, CPU, Options);
+ auto ABI = computeTargetABI(TT, CPU, Options);
std::string Ret = "";
if (isLittle)
@@ -129,7 +128,7 @@
// Big endian.
Ret += "E";
- Ret += DataLayout::getManglingComponent(Triple);
+ Ret += DataLayout::getManglingComponent(TT);
// Pointers are 32 bits and aligned to 32 bits.
Ret += "-p:32:32";
@@ -159,7 +158,7 @@
// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
// aligned everywhere else.
- if (Triple.isOSNaCl())
+ if (TT.isOSNaCl())
Ret += "-S128";
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
Ret += "-S64";
@@ -176,8 +175,9 @@
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
- : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
- CPU, FS, Options, RM, CM, OL),
+ : LLVMTargetMachine(T,
+ computeDataLayout(Triple(TT), CPU, Options, isLittle),
+ TT, CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) {
Index: lib/Target/Mips/MipsTargetMachine.cpp
===================================================================
--- lib/Target/Mips/MipsTargetMachine.cpp
+++ lib/Target/Mips/MipsTargetMachine.cpp
@@ -44,12 +44,11 @@
RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
}
-static std::string computeDataLayout(StringRef TT, StringRef CPU,
+static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
std::string Ret = "";
- MipsABIInfo ABI =
- MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions);
+ MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
// There are both little and big endian mips.
if (isLittle)
@@ -88,8 +87,9 @@
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
- : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
- CPU, FS, Options, RM, CM, OL),
+ : LLVMTargetMachine(T,
+ computeDataLayout(Triple(TT), CPU, Options, isLittle),
+ TT, CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
Subtarget(nullptr),
Index: lib/Target/R600/AMDGPUTargetMachine.cpp
===================================================================
--- lib/Target/R600/AMDGPUTargetMachine.cpp
+++ lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -51,11 +51,10 @@
SchedCustomRegistry("r600", "Run R600's custom scheduler",
createR600MachineScheduler);
-static std::string computeDataLayout(StringRef TT) {
- Triple Triple(TT);
+static std::string computeDataLayout(const Triple &TT) {
std::string Ret = "e-p:32:32";
- if (Triple.getArch() == Triple::amdgcn) {
+ if (TT.getArch() == Triple::amdgcn) {
// 32-bit private, local, and region pointers. 64-bit global and constant.
Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
}
@@ -71,8 +70,8 @@
TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OptLevel)
- : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
- OptLevel),
+ : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
+ RM, CM, OptLevel),
TLOF(new TargetLoweringObjectFileELF()),
Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() {
setRequiresStructuredCFG(true);
Index: lib/Target/SystemZ/SystemZTargetMachine.cpp
===================================================================
--- lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -43,17 +43,16 @@
return VectorABI;
}
-static std::string computeDataLayout(StringRef TT, StringRef CPU,
+static std::string computeDataLayout(const Triple &TT, StringRef CPU,
StringRef FS) {
- const Triple Triple(TT);
bool VectorABI = UsesVectorABI(CPU, FS);
std::string Ret = "";
// Big endian.
Ret += "E";
// Data mangling.
- Ret += DataLayout::getManglingComponent(Triple);
+ Ret += DataLayout::getManglingComponent(TT);
// Make sure that global data has at least 16 bits of alignment by
// default, so that we can refer to it using LARL. We don't have any
@@ -84,8 +83,8 @@
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
- : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
- RM, CM, OL),
+ : LLVMTargetMachine(T, computeDataLayout(Triple(TT), CPU, FS), TT, CPU, FS,
+ Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo();
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