Author: rsingh Date: Wed Jun 17 14:56:30 2015 New Revision: 239932 URL: http://llvm.org/viewvc/llvm-project?rev=239932&view=rev Log: [ARM] Replace hard coded metadata arguments in tests with a regex.
Differential Revision: http://reviews.llvm.org/D10507 Modified: cfe/trunk/test/CodeGen/arm_acle.c cfe/trunk/test/CodeGen/builtins-arm64.c Modified: cfe/trunk/test/CodeGen/arm_acle.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm_acle.c?rev=239932&r1=239931&r2=239932&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/arm_acle.c (original) +++ cfe/trunk/test/CodeGen/arm_acle.c Wed Jun 17 14:56:30 2015 @@ -339,8 +339,8 @@ uint32_t test_crc32cd(uint32_t a, uint64 /* 10.1 Special register intrinsics */ // ARM-LABEL: test_rsr -// AArch64: call i64 @llvm.read_register.i64(metadata !1) -// AArch32: call i32 @llvm.read_register.i32(metadata !3) +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]]) uint32_t test_rsr() { #ifdef __ARM_32BIT_STATE return __arm_rsr("cp1:2:c3:c4:5"); @@ -350,8 +350,8 @@ uint32_t test_rsr() { } // ARM-LABEL: test_rsr64 -// AArch64: call i64 @llvm.read_register.i64(metadata !1) -// AArch32: call i64 @llvm.read_register.i64(metadata !4) +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]]) uint64_t test_rsr64() { #ifdef __ARM_32BIT_STATE return __arm_rsr64("cp1:2:c3"); @@ -361,15 +361,15 @@ uint64_t test_rsr64() { } // ARM-LABEL: test_rsrp -// AArch64: call i64 @llvm.read_register.i64(metadata !2) -// AArch32: call i32 @llvm.read_register.i32(metadata !5) +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M1:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M4:[0-9]]]) void *test_rsrp() { return __arm_rsrp("sysreg"); } // ARM-LABEL: test_wsr -// AArch64: call void @llvm.write_register.i64(metadata !1, i64 %{{.*}}) -// AArch32: call void @llvm.write_register.i32(metadata !3, i32 %{{.*}}) +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}}) void test_wsr(uint32_t v) { #ifdef __ARM_32BIT_STATE __arm_wsr("cp1:2:c3:c4:5", v); @@ -379,8 +379,8 @@ void test_wsr(uint32_t v) { } // ARM-LABEL: test_wsr64 -// AArch64: call void @llvm.write_register.i64(metadata !1, i64 %{{.*}}) -// AArch32: call void @llvm.write_register.i64(metadata !4, i64 %{{.*}}) +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}}) void test_wsr64(uint64_t v) { #ifdef __ARM_32BIT_STATE __arm_wsr64("cp1:2:c3", v); @@ -390,15 +390,15 @@ void test_wsr64(uint64_t v) { } // ARM-LABEL: test_wsrp -// AArch64: call void @llvm.write_register.i64(metadata !2, i64 %{{.*}}) -// AArch32: call void @llvm.write_register.i32(metadata !5, i32 %{{.*}}) +// AArch64: call void @llvm.write_register.i64(metadata ![[M1:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M4:[0-9]]], i32 %{{.*}}) void test_wsrp(void *v) { __arm_wsrp("sysreg", v); } -// AArch32: !3 = !{!"cp1:2:c3:c4:5"} -// AArch32: !4 = !{!"cp1:2:c3"} -// AArch32: !5 = !{!"sysreg"} +// AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"} +// AArch32: ![[M3]] = !{!"cp1:2:c3"} +// AArch32: ![[M4]] = !{!"sysreg"} -// AArch64: !1 = !{!"1:2:3:4:5"} -// AArch64: !2 = !{!"sysreg"} +// AArch64: ![[M0]] = !{!"1:2:3:4:5"} +// AArch64: ![[M1]] = !{!"sysreg"} Modified: cfe/trunk/test/CodeGen/builtins-arm64.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-arm64.c?rev=239932&r1=239931&r2=239932&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/builtins-arm64.c (original) +++ cfe/trunk/test/CodeGen/builtins-arm64.c Wed Jun 17 14:56:30 2015 @@ -45,37 +45,37 @@ void prefetch() { } unsigned rsr() { - // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !1) + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) // CHECK-NEXT: trunc i64 [[V0]] to i32 return __builtin_arm_rsr("1:2:3:4:5"); } unsigned long rsr64() { - // CHECK: call i64 @llvm.read_register.i64(metadata !1) + // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) return __builtin_arm_rsr64("1:2:3:4:5"); } void *rsrp() { - // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !1) + // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) // CHECK-NEXT: inttoptr i64 [[V0]] to i8* return __builtin_arm_rsrp("1:2:3:4:5"); } void wsr(unsigned v) { // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64 - // CHECK-NEXT: call void @llvm.write_register.i64(metadata !1, i64 [[V0]]) + // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]]) __builtin_arm_wsr("1:2:3:4:5", v); } void wsr64(unsigned long v) { - // CHECK: call void @llvm.write_register.i64(metadata !1, i64 %v) + // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v) __builtin_arm_wsr64("1:2:3:4:5", v); } void wsrp(void *v) { // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64 - // CHECK-NEXT: call void @llvm.write_register.i64(metadata !1, i64 [[V0]]) + // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]]) __builtin_arm_wsrp("1:2:3:4:5", v); } -// CHECK: !1 = !{!"1:2:3:4:5"} +// CHECK: ![[M0]] = !{!"1:2:3:4:5"} _______________________________________________ cfe-commits mailing list cfe-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
