On 17.11.2012, at 18:30, Benjamin Kramer <[email protected]> wrote:
> Author: d0k > Date: Sat Nov 17 11:30:55 2012 > New Revision: 168260 > > URL: http://llvm.org/viewvc/llvm-project?rev=168260&view=rev > Log: > Enable inlining of 4 byte atomic ops on ppc32, 8 byte atomic ops on ppc64. > > Also fixes a bit/byte mismatch when checking if a target supports atomic ops > of a certain size. John, is this OK for 3.2? It unbreaks clang selfhost on ppc64 with libstdc++ 4.7. - Ben > > Added: > cfe/trunk/test/CodeGen/ppc-atomics.c > Modified: > cfe/trunk/lib/Basic/Targets.cpp > cfe/trunk/lib/CodeGen/CGExpr.cpp > > Modified: cfe/trunk/lib/Basic/Targets.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=168260&r1=168259&r2=168260&view=diff > ============================================================================== > --- cfe/trunk/lib/Basic/Targets.cpp (original) > +++ cfe/trunk/lib/Basic/Targets.cpp Sat Nov 17 11:30:55 2012 > @@ -1037,6 +1037,9 @@ > LongDoubleWidth = LongDoubleAlign = 64; > LongDoubleFormat = &llvm::APFloat::IEEEdouble; > } > + > + // PPC32 supports atomics up to 4 bytes. > + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; > } > > virtual BuiltinVaListKind getBuiltinVaListKind() const { > @@ -1065,7 +1068,9 @@ > DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" > "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" > "v128:128:128-n32:64"; > - > + > + // PPC64 supports atomics up to 8 bytes. > + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; > } > virtual BuiltinVaListKind getBuiltinVaListKind() const { > return TargetInfo::CharPtrBuiltinVaList; > > Modified: cfe/trunk/lib/CodeGen/CGExpr.cpp > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGExpr.cpp?rev=168260&r1=168259&r2=168260&view=diff > ============================================================================== > --- cfe/trunk/lib/CodeGen/CGExpr.cpp (original) > +++ cfe/trunk/lib/CodeGen/CGExpr.cpp Sat Nov 17 11:30:55 2012 > @@ -3166,11 +3166,10 @@ > uint64_t Size = sizeChars.getQuantity(); > CharUnits alignChars = getContext().getTypeAlignInChars(AtomicTy); > unsigned Align = alignChars.getQuantity(); > - unsigned MaxInlineWidth = > - getContext().getTargetInfo().getMaxAtomicInlineWidth(); > - bool UseLibcall = (Size != Align || Size > MaxInlineWidth); > - > - > + unsigned MaxInlineWidthInBits = > + getContext().getTargetInfo().getMaxAtomicInlineWidth(); > + bool UseLibcall = (Size != Align || > + getContext().toBits(sizeChars) > MaxInlineWidthInBits); > > llvm::Value *Ptr, *Order, *OrderFail = 0, *Val1 = 0, *Val2 = 0; > Ptr = EmitScalarExpr(E->getPtr()); > > Added: cfe/trunk/test/CodeGen/ppc-atomics.c > URL: > http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ppc-atomics.c?rev=168260&view=auto > ============================================================================== > --- cfe/trunk/test/CodeGen/ppc-atomics.c (added) > +++ cfe/trunk/test/CodeGen/ppc-atomics.c Sat Nov 17 11:30:55 2012 > @@ -0,0 +1,35 @@ > +// RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm %s -o - | FileCheck > %s -check-prefix=32 > +// RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | > FileCheck %s -check-prefix=64 > + > +unsigned char c1, c2; > +unsigned short s1, s2; > +unsigned int i1, i2; > +unsigned long long ll1, ll2; > + > +enum memory_order { > + memory_order_relaxed, > + memory_order_consume, > + memory_order_acquire, > + memory_order_release, > + memory_order_acq_rel, > + memory_order_seq_cst > +}; > + > +void test1(void) { > + (void)__atomic_load(&c1, &c2, memory_order_seq_cst); > + (void)__atomic_load(&s1, &s2, memory_order_seq_cst); > + (void)__atomic_load(&i1, &i2, memory_order_seq_cst); > + (void)__atomic_load(&ll1, &ll2, memory_order_seq_cst); > + > +// 32: define void @test1 > +// 32: load atomic i8* @c1 seq_cst > +// 32: load atomic i16* @s1 seq_cst > +// 32: load atomic i32* @i1 seq_cst > +// 32: call void @__atomic_load(i32 8, i8* bitcast (i64* @ll1 to i8*) > + > +// 64: define void @test1 > +// 64: load atomic i8* @c1 seq_cst > +// 64: load atomic i16* @s1 seq_cst > +// 64: load atomic i32* @i1 seq_cst > +// 64: load atomic i64* @ll1 seq_cst > +} > > > _______________________________________________ > cfe-commits mailing list > [email protected] > http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
