Hi Eli,
I didn't find much info about atomics for targets. I find two attributes are
relevant: MaxAtomicPromoteWidth and MaxAtomicInlineWidth, but they cannot
be used to compute the macros.
Besides, even for the same target, the macros are dependent on CPU types.
For example, for X86 target:
if (CPU >= CK_i486) {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
}
if (CPU >= CK_i586)
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
}
Thanks,
Weiming
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
From: Eli Friedman [mailto:[email protected]]
Sent: Monday, September 02, 2013 7:12 PM
To: Weiming Zhao
Cc: [email protected] Commits
Subject: Re: Bug fix 12730: Add support for
__GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8} on ARM
On Sat, Aug 31, 2013 at 11:51 PM, <[email protected]> wrote:
Hi,
The orignal patch (r178816) fixed bug 12730 for x86. This patch adds the
same macro definitions "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}" to ARM
target to address the same issue.
Please help to review it.
Is there any way we can compute the correct setting for these macros in a
target-independent code? IIRC, targets already expose some information
about atomics.
-Eli
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