Andrew Pinski wrote:
On 6/30/07, Ian Rogers <[EMAIL PROTECTED]> wrote:
Attached is a patch that improves the performance of an Float/Double
compare by exploiting information carried in their bit integer/long
versions sign bit. It removes one comparison from the normal path, as
well as making other compares with ints/longs. When sorting an array of
floats this can yield a little under a 8% speed up on a Pentium 4.
There's a thread discussing whether this is a good or bad idea on the
main mailing list, but so far I'm merrily talking to myself :-)
This is going to slow down this function for PowerPC (except for
Power6+) where you have to take a huge hit to transfer between
register sets via the stack. For an example on the Cell, this is
going to be an extra 40-100 cycle hit.
I guess there are a lot of factors to do with the underlying
architecture. My feeling is that we should move the code to
VMFloat/VMDouble and then the VM can choose the appropriate version.
Having the regular version optimized for Intel would make sense to me.
Its not straight forward for me to benchmark the code on non-IA32
architectures, in particular Cell. I'll try to do a Jikes RVM benchmark
on a PowerPC I have access to in the week. My feeling is that the
performance may not be as bad as you imagine, but it's hard to predict -
and this may not be an architecture you care about anyway.
Regards,
Ian
