Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2024-08-30 13:32:50
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.2698 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Fri Aug 30 13:32:50 2024 rev:36 rq:1197732 version:1.98.3
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2024-08-13
13:24:48.354150960 +0200
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.2698/CoreFreq.changes
2024-08-30 13:33:24.909060751 +0200
@@ -1,0 +2,12 @@
+Fri Aug 30 07:47:04 UTC 2024 - Michael Pujos <pujos.mich...@gmail.com>
+
+- Update to 1.98.3
+ * [AMD]
+ - [VMR/RPL/GNR] Voltage Curve Optimizer (VCO)
+ - Provide a specific VCO formula based on HWM_CHIPSET=AMD_VCO
+ build parameter
+ - The standard voltage formulas are restored to these architectures
+ - Zen5: Guessed a new P-State MSR bits specification to fix the
+ Coefficient Of Frequency (COF)
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.98.2.tar.gz
New:
----
CoreFreq-1.98.3.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.QAHqh0/_old 2024-08-30 13:33:25.357079533 +0200
+++ /var/tmp/diff_new_pack.QAHqh0/_new 2024-08-30 13:33:25.357079533 +0200
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.98.2
+Version: 1.98.3
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.98.2.tar.gz -> CoreFreq-1.98.3.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/Makefile new/CoreFreq-1.98.3/Makefile
--- old/CoreFreq-1.98.2/Makefile 2024-08-12 00:35:24.000000000 +0200
+++ new/CoreFreq-1.98.3/Makefile 2024-08-25 13:09:07.000000000 +0200
@@ -4,7 +4,7 @@
COREFREQ_MAJOR = 1
COREFREQ_MINOR = 98
-COREFREQ_REV = 2
+COREFREQ_REV = 3
HW = $(shell uname -m)
CC ?= cc
WARNING = -Wall -Wfatal-errors
@@ -351,7 +351,7 @@
"| where <freq> is at least 4850000000 Hz |\n"\
"| |\n"\
"| HWM_CHIPSET=<chipset> |\n"\
- "| where <chipset> is W83627 or IT8720 or COMPATIBLE |\n"\
+ "| where <chipset> is W83627; IT8720; AMD_VCO or COMPATIBLE |\n"\
"| |\n"\
"| Performance Counters: |\n"\
"| ------------------------------------------------------- |\n"\
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/README.md
new/CoreFreq-1.98.3/README.md
--- old/CoreFreq-1.98.2/README.md 2024-08-12 00:35:24.000000000 +0200
+++ new/CoreFreq-1.98.3/README.md 2024-08-25 13:09:07.000000000 +0200
@@ -542,7 +542,7 @@
| where <freq> is at least 4850000000 Hz |
| |
| HWM_CHIPSET=<chipset> |
-| where <chipset> is W83627 or IT8720 or COMPATIBLE |
+| where <chipset> is W83627; IT8720; AMD_VCO or COMPATIBLE |
| |
| Performance Counters: |
| ------------------------------------------------------- |
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/x86_64/amd_reg.h
new/CoreFreq-1.98.3/x86_64/amd_reg.h
--- old/CoreFreq-1.98.2/x86_64/amd_reg.h 2024-08-12 00:35:24.000000000
+0200
+++ new/CoreFreq-1.98.3/x86_64/amd_reg.h 2024-08-25 13:09:07.000000000
+0200
@@ -541,6 +541,18 @@
Reserved : 63-33,
PstateEn : 64-63;
} Family_19h; /* Model 70h_A0; Model 11h_B1; Model 61h_B1 */
+ struct
+ {
+ unsigned long long /* MSR 0xC001_006[4...B] P-state [7:0] */
+ CpuFid : 11-0, /* Undocumented FID */
+ CpuDfsId : 14-11, /* Undocumented DID */
+ CpuVid : 22-14, /* VID verified w/ 9950X */
+ IddValue : 30-22,
+ IddDiv : 32-30,
+ CpuVid8 : 33-32,
+ Reserved : 63-33,
+ PstateEn : 64-63;
+ } Family_1Ah; /* CPUID signature BF_44h */
} PSTATEDEF;
typedef union
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/x86_64/corefreqd.c
new/CoreFreq-1.98.3/x86_64/corefreqd.c
--- old/CoreFreq-1.98.2/x86_64/corefreqd.c 2024-08-12 00:35:24.000000000
+0200
+++ new/CoreFreq-1.98.3/x86_64/corefreqd.c 2024-08-25 13:09:07.000000000
+0200
@@ -784,48 +784,48 @@
[FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_RMB_PerPkg
};
-static void ComputeVoltage_AMD_19_61h( struct FLIP_FLOP *CFlip,
- RO(SHM_STRUCT) *RO(Shm),
- unsigned int cpu )
+static void ComputeVoltage_AMD_VCO( struct FLIP_FLOP *CFlip,
+ RO(SHM_STRUCT) *RO(Shm),
+ unsigned int cpu )
{
- COMPUTE_VOLTAGE(AMD_19_61h,
+ COMPUTE_VOLTAGE(AMD_VCO,
CFlip->Voltage.Vcore,
CFlip->Voltage.VID);
Core_ComputeVoltageLimits(&RO(Shm)->Cpu[cpu], CFlip);
}
-#define ComputeVoltage_AMD_19_61h_PerSMT ComputeVoltage_AMD_19_61h
+#define ComputeVoltage_AMD_VCO_PerSMT ComputeVoltage_AMD_VCO
-static void ComputeVoltage_AMD_19_61h_PerCore( struct FLIP_FLOP *CFlip,
- RO(SHM_STRUCT) *RO(Shm),
- unsigned int cpu )
+static void ComputeVoltage_AMD_VCO_PerCore( struct FLIP_FLOP *CFlip,
+ RO(SHM_STRUCT) *RO(Shm),
+ unsigned int cpu )
{
if ((RO(Shm)->Cpu[cpu].Topology.ThreadID == 0)
|| (RO(Shm)->Cpu[cpu].Topology.ThreadID == -1))
{
- ComputeVoltage_AMD_19_61h(CFlip, RO(Shm), cpu);
+ ComputeVoltage_AMD_VCO(CFlip, RO(Shm), cpu);
}
}
-static void ComputeVoltage_AMD_19_61h_PerPkg( struct FLIP_FLOP *CFlip,
- RO(SHM_STRUCT) *RO(Shm),
- unsigned int cpu )
+static void ComputeVoltage_AMD_VCO_PerPkg( struct FLIP_FLOP *CFlip,
+ RO(SHM_STRUCT) *RO(Shm),
+ unsigned int cpu )
{
if (cpu == RO(Shm)->Proc.Service.Core)
{
- ComputeVoltage_AMD_19_61h(CFlip, RO(Shm), cpu);
+ ComputeVoltage_AMD_VCO(CFlip, RO(Shm), cpu);
}
}
-static void (*ComputeVoltage_AMD_19_61h_Matrix[4])(struct FLIP_FLOP*,
+static void (*ComputeVoltage_AMD_VCO_Matrix[4])(struct FLIP_FLOP*,
RO(SHM_STRUCT)*,
unsigned int) = \
{
[FORMULA_SCOPE_NONE] = ComputeVoltage_None,
- [FORMULA_SCOPE_SMT ] = ComputeVoltage_AMD_19_61h_PerSMT,
- [FORMULA_SCOPE_CORE] = ComputeVoltage_AMD_19_61h_PerCore,
- [FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_19_61h_PerPkg
+ [FORMULA_SCOPE_SMT ] = ComputeVoltage_AMD_VCO_PerSMT,
+ [FORMULA_SCOPE_CORE] = ComputeVoltage_AMD_VCO_PerCore,
+ [FORMULA_SCOPE_PKG ] = ComputeVoltage_AMD_VCO_PerPkg
};
static void ComputeVoltage_Winbond_IO( struct FLIP_FLOP *CFlip,
@@ -1102,8 +1102,14 @@
case VOLTAGE_KIND_AMD_RMB:
ComputeVoltageFormula = ComputeVoltage_AMD_RMB_Matrix;
break;
- case VOLTAGE_KIND_AMD_19_61h:
- ComputeVoltageFormula = ComputeVoltage_AMD_19_61h_Matrix;
+ case VOLTAGE_KIND_ZEN3_VCO:
+ ComputeVoltageFormula = ComputeVoltage_AMD_VCO_Matrix;
+ break;
+ case VOLTAGE_KIND_ZEN4_VCO:
+ ComputeVoltageFormula = ComputeVoltage_AMD_VCO_Matrix;
+ break;
+ case VOLTAGE_KIND_ZEN5_VCO:
+ ComputeVoltageFormula = ComputeVoltage_AMD_VCO_Matrix;
break;
case VOLTAGE_KIND_WINBOND_IO:
ComputeVoltageFormula = ComputeVoltage_Winbond_IO_Matrix;
@@ -8784,13 +8790,36 @@
PFlip->Voltage.VID.SOC);
}
-static void Pkg_ComputeVoltage_AMD_19_61h(struct PKG_FLIP_FLOP *PFlip)
+static void Pkg_ComputeVoltage_ZEN3_VCO(struct PKG_FLIP_FLOP *PFlip)
{
- COMPUTE_VOLTAGE(AMD_19_61h,
+ COMPUTE_VOLTAGE(AMD_VCO,
PFlip->Voltage.CPU,
PFlip->Voltage.VID.CPU);
-/*TODO
- COMPUTE_VOLTAGE(AMD_19_61h,
+
+ COMPUTE_VOLTAGE(AMD_17h,
+ PFlip->Voltage.SOC,
+ PFlip->Voltage.VID.SOC);
+}
+
+static void Pkg_ComputeVoltage_ZEN4_VCO(struct PKG_FLIP_FLOP *PFlip)
+{
+ COMPUTE_VOLTAGE(AMD_VCO,
+ PFlip->Voltage.CPU,
+ PFlip->Voltage.VID.CPU);
+
+ COMPUTE_VOLTAGE(AMD_RMB,
+ PFlip->Voltage.SOC,
+ PFlip->Voltage.VID.SOC);
+}
+
+static void Pkg_ComputeVoltage_ZEN5_VCO(struct PKG_FLIP_FLOP *PFlip)
+{
+ COMPUTE_VOLTAGE(AMD_VCO,
+ PFlip->Voltage.CPU,
+ PFlip->Voltage.VID.CPU);
+
+/*TODO(Unknown SOC voltage register)
+ COMPUTE_VOLTAGE(AMD_VCO,
PFlip->Voltage.SOC,
PFlip->Voltage.VID.SOC); */
}
@@ -8951,8 +8980,14 @@
case VOLTAGE_KIND_AMD_RMB:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_AMD_RMB;
break;
- case VOLTAGE_KIND_AMD_19_61h:
- Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_AMD_19_61h;
+ case VOLTAGE_KIND_ZEN3_VCO:
+ Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_ZEN3_VCO;
+ break;
+ case VOLTAGE_KIND_ZEN4_VCO:
+ Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_ZEN4_VCO;
+ break;
+ case VOLTAGE_KIND_ZEN5_VCO:
+ Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_ZEN5_VCO;
break;
case VOLTAGE_KIND_WINBOND_IO:
Pkg_ComputeVoltageFormula = Pkg_ComputeVoltage_Winbond_IO;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/x86_64/corefreqk.c
new/CoreFreq-1.98.3/x86_64/corefreqk.c
--- old/CoreFreq-1.98.2/x86_64/corefreqk.c 2024-08-12 00:35:24.000000000
+0200
+++ new/CoreFreq-1.98.3/x86_64/corefreqk.c 2024-08-25 13:09:07.000000000
+0200
@@ -8107,16 +8107,28 @@
Default_Unlock_Reset();
}
-inline COF_ST AMD_Zen_CoreCOF(unsigned int FID, unsigned int DID)
+inline COF_ST AMD_Zen_CoreCOF(PSTATEDEF PStateDef)
{/* Source: PPR for AMD Family 17h Model 01h, Revision B1 Processors
CoreCOF = (PStateDef[CpuFid[7:0]] / PStateDef[CpuDfsId]) * 200 */
+ unsigned long remainder;
COF_ST COF;
- if (DID != 0) {
- COF.Q = (FID << 1) / DID;
- COF.R = (UNIT_KHz(1) * (FID - ((COF.Q * DID) >> 1))) >> 2;
- } else {
- COF.Q = FID >> 2;
+ if (PStateDef.Family_17h.CpuDfsId > 0b111) {
+ COF.Q = (PStateDef.Family_17h.CpuFid << 1)
+ / PStateDef.Family_17h.CpuDfsId;
+ remainder = (UNIT_KHz(1) * (PStateDef.Family_17h.CpuFid
+ - ((COF.Q * PStateDef.Family_17h.CpuDfsId) >> 1))) >> 2;
+ COF.R = (unsigned short) remainder;
+ } else switch (PUBLIC(RO(Proc))->Features.Std.EAX.ExtFamily) {
+ case 0xB: /* Zen5: Granite Ridge & Strix Point */
+ COF.Q = (PStateDef.Family_1Ah.CpuFid >> 1) / 10;
+ remainder = (PRECISION * PStateDef.Family_1Ah.CpuFid) >> 1;
+ remainder = remainder - (UNIT_KHz(1) * COF.Q);
+ COF.R = (unsigned short) remainder;
+ break;
+ default:
+ COF.Q = PStateDef.Family_17h.CpuFid >> 2;
COF.R = 0;
+ break;
}
return COF;
}
@@ -8174,8 +8186,7 @@
RDMSR(PstateDef, (MSR_AMD_PSTATE_DEF_BASE
+ PstateLimit.Family_17h.PstateMaxVal));
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MIN)] = COF.Q;
} else {
@@ -8189,8 +8200,7 @@
/* Handle only valid P-States. */
if (PstateDef.Family_17h.PstateEn)
{
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
PUBLIC(RO(Core, AT(cpu)))->Boost[sort[pstate]] = COF.Q;
}
@@ -8201,8 +8211,7 @@
RDMSR(PstateCtrl, MSR_AMD_PERF_CTL);
RDMSR(PstateDef, MSR_AMD_PSTATE_DEF_BASE + PstateCtrl.PstateCmd);
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(TGT)] = COF.Q;
@@ -8308,8 +8317,7 @@
if (PstateDef.Family_17h.PstateEn)
{
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
if (COF.Q == target) {
RdWrMSR = 1;
break;
@@ -8350,8 +8358,7 @@
if (pClockZen->pClockMod->cpu == -1) { /* Request an absolute COF */
COF.Q = pClockZen->pClockMod->Ratio;
} else { /* Compute the requested COF based on a frequency offset */
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
COF.Q = COF.Q + pClockZen->pClockMod->Offset;
}
@@ -8399,8 +8406,7 @@
RDMSR(PstateDef, pClockZen->PstateAddr);
PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] = \
- AMD_Zen_CoreCOF(PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId).Q;
+ AMD_Zen_CoreCOF(PstateDef).Q;
cpu_data(cpu).loops_per_jiffy = \
COMPUTE_LPJ( PUBLIC(RO(Core, AT(cpu)))->Clock.Hz,
@@ -8417,8 +8423,7 @@
RDMSR(PstateDef, pClockZen->PstateAddr);
PUBLIC(RO(Core, AT(cpu)))->Boost[BOOST(MAX)] = \
- AMD_Zen_CoreCOF(PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId).Q;
+ AMD_Zen_CoreCOF(PstateDef).Q;
cpu_data(cpu).loops_per_jiffy = \
COMPUTE_LPJ( PUBLIC(RO(Core, AT(cpu)))->Clock.Hz,
@@ -19942,15 +19947,13 @@
RDMSR(PstateCtrl, MSR_AMD_PERF_CTL);
RDMSR(PstateDef, MSR_AMD_PSTATE_DEF_BASE + PstateCtrl.PstateCmd);
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
PUBLIC(RO(Core, AT(Core->Bind)))->Boost[BOOST(TGT)] = COF.Q;
/* Read the Boosted Frequency and voltage VID. */
RDMSR(PstateDef, MSR_AMD_F17H_HW_PSTATE_STATUS);
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
Core->Ratio.COF = COF;
if (Core->Bind == PUBLIC(RO(Proc))->Service.Core)
@@ -21752,8 +21755,7 @@
if (PstateDef.Family_17h.PstateEn)
{
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
if (COF.Q == (*ratio)) {
WrModRd = 1;
break;
@@ -21774,8 +21776,7 @@
PstateDef.value = 0;
RDMSR(PstateDef, MSR_AMD_PSTATE_DEF_BASE + pstate);
- COF = AMD_Zen_CoreCOF( PstateDef.Family_17h.CpuFid,
- PstateDef.Family_17h.CpuDfsId );
+ COF = AMD_Zen_CoreCOF(PstateDef);
Core->Boost[BOOST(TGT)] = COF.Q;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/x86_64/corefreqk.h
new/CoreFreq-1.98.3/x86_64/corefreqk.h
--- old/CoreFreq-1.98.2/x86_64/corefreqk.h 2024-08-12 00:35:24.000000000
+0200
+++ new/CoreFreq-1.98.3/x86_64/corefreqk.h 2024-08-25 13:09:07.000000000
+0200
@@ -628,6 +628,8 @@
#define COMPATIBLE 0xffff
#define W83627 0x5ca3
#define IT8720 0x8720
+/* Voltage Curve Optimizer */
+#define AMD_VCO 0xfacc
/*
* --- Core_AMD_SMN_Read and Core_AMD_SMN_Write ---
@@ -12222,7 +12224,15 @@
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN3,
+#if defined(HWM_CHIPSET)
+#if (HWM_CHIPSET == AMD_VCO)
+ .voltageFormula = VOLTAGE_FORMULA_ZEN3_VCO,
+#else
+ .voltageFormula = VOLTAGE_FORMULA_AMD_19h,
+#endif
+#else
.voltageFormula = VOLTAGE_FORMULA_AMD_19h,
+#endif
.powerFormula = POWER_FORMULA_AMD_19h,
.PCI_ids = PCI_AMD_19h_ids,
.Uncore = {
@@ -12390,7 +12400,15 @@
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_ZEN4,
- .voltageFormula = VOLTAGE_FORMULA_AMD_19_61h,
+#if defined(HWM_CHIPSET)
+#if (HWM_CHIPSET == AMD_VCO)
+ .voltageFormula = VOLTAGE_FORMULA_ZEN4_VCO,
+#else
+ .voltageFormula = VOLTAGE_FORMULA_AMD_ZEN4,
+#endif
+#else
+ .voltageFormula = VOLTAGE_FORMULA_AMD_ZEN4,
+#endif
.powerFormula = POWER_FORMULA_AMD_19h,
.PCI_ids = PCI_AMD_19h_ids,
.Uncore = {
@@ -12582,7 +12600,15 @@
.ClockMod = ClockMod_AMD_Zen,
.TurboClock = TurboClock_AMD_Zen,
.thermalFormula = THERMAL_FORMULA_AMD_1Ah,
+#if defined(HWM_CHIPSET)
+#if (HWM_CHIPSET == AMD_VCO)
+ .voltageFormula = VOLTAGE_FORMULA_ZEN5_VCO,
+#else
.voltageFormula = VOLTAGE_FORMULA_AMD_1Ah,
+#endif
+#else
+ .voltageFormula = VOLTAGE_FORMULA_AMD_1Ah,
+#endif
.powerFormula = POWER_FORMULA_AMD_1Ah,
.PCI_ids = PCI_AMD_1Ah_ids,
.Uncore = {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.98.2/x86_64/coretypes.h
new/CoreFreq-1.98.3/x86_64/coretypes.h
--- old/CoreFreq-1.98.2/x86_64/coretypes.h 2024-08-12 00:35:24.000000000
+0200
+++ new/CoreFreq-1.98.3/x86_64/coretypes.h 2024-08-25 13:09:07.000000000
+0200
@@ -582,7 +582,9 @@
VOLTAGE_KIND_AMD_15h = 0b000001000001000000000000,
VOLTAGE_KIND_AMD_17h = 0b000100000001000000000000,
VOLTAGE_KIND_AMD_RMB = 0b000010000001000000000000,
- VOLTAGE_KIND_AMD_19_61h = 0b000000100001000000000000,
+ VOLTAGE_KIND_ZEN3_VCO = 0b000000100001000000000000,
+ VOLTAGE_KIND_ZEN4_VCO = 0b000000010001000000000000,
+ VOLTAGE_KIND_ZEN5_VCO = 0b000000001001000000000000,
VOLTAGE_KIND_WINBOND_IO = 0b001000000000000000000000,
VOLTAGE_KIND_ITETECH_IO = 0b010000000000000000000000
};
@@ -602,13 +604,15 @@
VOLTAGE_FORMULA_AMD_17h =(VOLTAGE_KIND_AMD_17h << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_AMD_RMB =(VOLTAGE_KIND_AMD_RMB << 8) | FORMULA_SCOPE_PKG,
VOLTAGE_FORMULA_AMD_ZEN4 =(VOLTAGE_KIND_AMD_RMB << 8) | FORMULA_SCOPE_SMT,
-VOLTAGE_FORMULA_AMD_19_61h =(VOLTAGE_KIND_AMD_19_61h << 8) | FORMULA_SCOPE_SMT,
+VOLTAGE_FORMULA_ZEN3_VCO =(VOLTAGE_KIND_ZEN3_VCO << 8) | FORMULA_SCOPE_SMT,
+VOLTAGE_FORMULA_ZEN4_VCO =(VOLTAGE_KIND_ZEN4_VCO << 8) | FORMULA_SCOPE_SMT,
+VOLTAGE_FORMULA_ZEN5_VCO =(VOLTAGE_KIND_ZEN5_VCO << 8) | FORMULA_SCOPE_SMT,
VOLTAGE_FORMULA_WINBOND_IO =(VOLTAGE_KIND_WINBOND_IO << 8) | FORMULA_SCOPE_PKG,
VOLTAGE_FORMULA_ITETECH_IO =(VOLTAGE_KIND_ITETECH_IO << 8) | FORMULA_SCOPE_PKG
};
#define VOLTAGE_FORMULA_AMD_19h VOLTAGE_FORMULA_AMD_17h
-#define VOLTAGE_FORMULA_AMD_1Ah VOLTAGE_FORMULA_AMD_19_61h
+#define VOLTAGE_FORMULA_AMD_1Ah VOLTAGE_FORMULA_AMD_ZEN4
enum POWER_KIND {
POWER_KIND_NONE = 0b000000000000000000000000,
@@ -781,7 +785,7 @@
#define COMPUTE_VOLTAGE_AMD_RMB(Vcore, VID) \
(Vcore = 0.00625 * (double) (VID))
-#define COMPUTE_VOLTAGE_AMD_19_61h(Vcore, VID) \
+#define COMPUTE_VOLTAGE_AMD_VCO(Vcore, VID) \
( Vcore = 2.09 - ((0.005 * (double) (VID)) + 0.245) )
#define COMPUTE_VOLTAGE_WINBOND_IO(Vcore, VID) \
