Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package libdrm for openSUSE:Factory checked in at 2021-04-10 15:26:12 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/libdrm (Old) and /work/SRC/openSUSE:Factory/.libdrm.new.2401 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "libdrm" Sat Apr 10 15:26:12 2021 rev:153 rq:883802 version:2.4.105 Changes: -------- --- /work/SRC/openSUSE:Factory/libdrm/libdrm.changes 2021-02-01 13:24:25.757749585 +0100 +++ /work/SRC/openSUSE:Factory/.libdrm.new.2401/libdrm.changes 2021-04-10 15:26:31.890318758 +0200 @@ -1,0 +2,18 @@ +Wed Apr 7 23:25:55 UTC 2021 - Dirk M??ller <dmuel...@suse.com> + +- update to 2.4.105: + * amdgpu: add function of INFO ioctl for querying video caps + * amdgpu: sync up amdgpu_drm.h with latest from kernel + * xf86drmMode: set FB_MODIFIERS flag when modifiers are supplied + * xf86drmMode: introduce drmModeGetPropertyType + * intel: Keep libdrm working without pread/pwrite ioctls + * xf86drm: fix null pointer deref in drmGetBufInfo + * intel: Add support for JSL + * xf86drm: warn about GEM handle reference counting + * xf86drmMode: add drmIsKMS + * intel: add INTEL_ADLS_IDS to the pciids list + * intel: sync i915_pciids.h with kernel + * amdgpu: update marketing names + * tests and build system fixes + +------------------------------------------------------------------- Old: ---- libdrm-2.4.104.tar.xz New: ---- libdrm-2.4.105.tar.xz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ libdrm.spec ++++++ --- /var/tmp/diff_new_pack.QcCxMK/_old 2021-04-10 15:26:32.354319304 +0200 +++ /var/tmp/diff_new_pack.QcCxMK/_new 2021-04-10 15:26:32.358319308 +0200 @@ -17,7 +17,7 @@ Name: libdrm -Version: 2.4.104 +Version: 2.4.105 Release: 0 Summary: Userspace Interface for Kernel DRM Services License: MIT @@ -28,21 +28,19 @@ # Source URL: https://dri.freedesktop.org/libdrm/ Source: https://dri.freedesktop.org/libdrm/%{name}-%{version}.tar.xz Source2: baselibs.conf - BuildRequires: fdupes BuildRequires: meson >= 0.43 BuildRequires: pkgconfig # needed for rst2man to create manual pages BuildRequires: python3-docutils BuildRequires: pkgconfig(pciaccess) >= 0.10 +Provides: libdrm23 = %{version} +Obsoletes: libdrm23 < %{version} %if 0%{?with_valgrind_support:1} %ifarch %{ix86} x86_64 ppc ppc64 ppc64le s390x %{arm} BuildRequires: pkgconfig(valgrind) %endif %endif - -Provides: libdrm23 = %{version} -Obsoletes: libdrm23 < %{version} # bug437293 %ifarch ppc64 Obsoletes: libdrm-64bit < %{version} @@ -302,7 +300,7 @@ %files tools %{_bindir}/drmdevice -%ifarch %arm aarch64 +%ifarch %{arm} aarch64 %{_bindir}/etnaviv_2d_test %{_bindir}/etnaviv_bo_cache_test %{_bindir}/etnaviv_cmd_stream_test @@ -368,10 +366,10 @@ %ifarch %{arm} aarch64 %files -n libdrm_etnaviv1 -%_libdir/libdrm_etnaviv.so.1* +%{_libdir}/libdrm_etnaviv.so.1* %files -n libdrm_exynos1 -%_libdir/libdrm_exynos.so.1* +%{_libdir}/libdrm_exynos.so.1* %files -n libdrm_freedreno1 %{_libdir}/libdrm_freedreno.so.1* ++++++ libdrm-2.4.104.tar.xz -> libdrm-2.4.105.tar.xz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/amdgpu/amdgpu-symbols.txt new/libdrm-2.4.105/amdgpu/amdgpu-symbols.txt --- old/libdrm-2.4.104/amdgpu/amdgpu-symbols.txt 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/amdgpu/amdgpu-symbols.txt 2021-04-07 16:09:24.163843400 +0200 @@ -66,6 +66,7 @@ amdgpu_query_hw_ip_info amdgpu_query_info amdgpu_query_sensor_info +amdgpu_query_video_caps_info amdgpu_read_mm_registers amdgpu_va_range_alloc amdgpu_va_range_free diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/amdgpu/amdgpu.h new/libdrm-2.4.105/amdgpu/amdgpu.h --- old/libdrm-2.4.104/amdgpu/amdgpu.h 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/amdgpu/amdgpu.h 2021-04-07 16:09:24.163843400 +0200 @@ -1238,6 +1238,23 @@ unsigned size, void *value); /** + * Query information about video capabilities + * + * The return sizeof(struct drm_amdgpu_info_video_caps) + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE) + * \param size - \c [in] Size of the returned value. + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, + unsigned size, void *value); + +/** * Read a set of consecutive memory-mapped registers. * Not all registers are allowed to be read by userspace. * diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/amdgpu/amdgpu_gpu_info.c new/libdrm-2.4.105/amdgpu/amdgpu_gpu_info.c --- old/libdrm-2.4.104/amdgpu/amdgpu_gpu_info.c 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/amdgpu/amdgpu_gpu_info.c 2021-04-07 16:09:24.163843400 +0200 @@ -331,3 +331,18 @@ return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info)); } + +drm_public int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type, + unsigned size, void *value) +{ + struct drm_amdgpu_info request; + + memset(&request, 0, sizeof(request)); + request.return_pointer = (uintptr_t)value; + request.return_size = size; + request.query = AMDGPU_INFO_VIDEO_CAPS; + request.sensor_info.type = cap_type; + + return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, + sizeof(struct drm_amdgpu_info)); +} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/amdgpu/meson.build new/libdrm-2.4.105/amdgpu/meson.build --- old/libdrm-2.4.104/amdgpu/meson.build 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/amdgpu/meson.build 2021-04-07 16:09:24.163843400 +0200 @@ -21,7 +21,7 @@ datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm') -libdrm_amdgpu = shared_library( +libdrm_amdgpu = library( 'drm_amdgpu', [ files( @@ -36,7 +36,7 @@ ], include_directories : [inc_root, inc_drm], link_with : libdrm, - dependencies : [dep_pthread_stubs, dep_atomic_ops], + dependencies : [dep_pthread_stubs, dep_atomic_ops, dep_rt], version : '1.0.0', install : true, ) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/core-symbols.txt new/libdrm-2.4.105/core-symbols.txt --- old/libdrm-2.4.104/core-symbols.txt 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/core-symbols.txt 2021-04-07 16:09:24.163843400 +0200 @@ -83,6 +83,7 @@ drmHashLookup drmHashNext drmIoctl +drmIsKMS drmIsMaster drmMalloc drmMap diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/data/amdgpu.ids new/libdrm-2.4.105/data/amdgpu.ids --- old/libdrm-2.4.104/data/amdgpu.ids 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/data/amdgpu.ids 2021-04-07 16:09:24.163843400 +0200 @@ -254,6 +254,8 @@ 7300, CB, AMD Radeon (TM) R9 Fury Series 7300, CA, AMD Radeon (TM) R9 Fury Series 7312, 00, AMD Radeon Pro W5700 +731E, C6, AMD Radeon RX 5700XTB +731E, C7, AMD Radeon RX 5700B 731F, C0, AMD Radeon RX 5700 XT 50th Anniversary 731F, C1, AMD Radeon RX 5700 XT 731F, C2, AMD Radeon RX 5600M @@ -265,9 +267,13 @@ 7340, C1, Radeon RX 5500M 7340, C5, Radeon RX 5500 XT 7340, C7, Radeon RX 5500 +7340, C9, AMD Radeon RX 5500XTB 7340, CF, Radeon RX 5300 7341, 00, AMD Radeon Pro W5500 7347, 00, AMD Radeon Pro W5500M +73BF, C0, AMD Radeon RX 6900 XT +73BF, C1, AMD Radeon RX 6800 XT +73BF, C3, AMD Radeon RX 6800 9874, C4, AMD Radeon R7 Graphics 9874, C5, AMD Radeon R6 Graphics 9874, C6, AMD Radeon R6 Graphics diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/etnaviv/meson.build new/libdrm-2.4.105/etnaviv/meson.build --- old/libdrm-2.4.104/etnaviv/meson.build 2021-01-11 19:15:27.364696700 +0100 +++ new/libdrm-2.4.105/etnaviv/meson.build 2021-04-07 16:09:24.163843400 +0200 @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_etnaviv = shared_library( +libdrm_etnaviv = library( 'drm_etnaviv', [ files( diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/exynos/meson.build new/libdrm-2.4.105/exynos/meson.build --- old/libdrm-2.4.104/exynos/meson.build 2021-01-11 19:15:27.368030000 +0100 +++ new/libdrm-2.4.105/exynos/meson.build 2021-04-07 16:09:24.163843400 +0200 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_exynos = shared_library( +libdrm_exynos = library( 'drm_exynos', [files('exynos_drm.c', 'exynos_fimg2d.c'), config_file], c_args : libdrm_c_args, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/freedreno/meson.build new/libdrm-2.4.105/freedreno/meson.build --- old/libdrm-2.4.104/freedreno/meson.build 2021-01-11 19:15:27.368030000 +0100 +++ new/libdrm-2.4.105/freedreno/meson.build 2021-04-07 16:09:24.167843300 +0200 @@ -39,7 +39,7 @@ ) endif -libdrm_freedreno = shared_library( +libdrm_freedreno = library( 'drm_freedreno', [files_freedreno, config_file], c_args : libdrm_c_args, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/include/drm/amdgpu_drm.h new/libdrm-2.4.105/include/drm/amdgpu_drm.h --- old/libdrm-2.4.104/include/drm/amdgpu_drm.h 2021-01-11 19:15:27.368030000 +0100 +++ new/libdrm-2.4.105/include/drm/amdgpu_drm.h 2021-04-07 16:09:24.167843300 +0200 @@ -502,15 +502,15 @@ #define AMDGPU_VM_MTYPE_MASK (0xf << 5) /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) -/* Use NC MTYPE instead of default MTYPE */ +/* Use Non Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_NC (1 << 5) -/* Use WC MTYPE instead of default MTYPE */ +/* Use Write Combine MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_WC (2 << 5) -/* Use CC MTYPE instead of default MTYPE */ +/* Use Cache Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_CC (3 << 5) -/* Use UC MTYPE instead of default MTYPE */ +/* Use UnCached MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_UC (4 << 5) -/* Use RW MTYPE instead of default MTYPE */ +/* Use Read Write MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_RW (5 << 5) struct drm_amdgpu_gem_va { @@ -667,12 +667,13 @@ }; }; -/** +/* * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * */ #define AMDGPU_IDS_FLAGS_FUSION 0x1 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 +#define AMDGPU_IDS_FLAGS_TMZ 0x4 /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 @@ -723,6 +724,8 @@ #define AMDGPU_INFO_FW_TA 0x13 /* Subquery id: Query DMCUB firmware version */ #define AMDGPU_INFO_FW_DMCUB 0x14 + /* Subquery id: Query TOC firmware version */ + #define AMDGPU_INFO_FW_TOC 0x15 /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f @@ -779,6 +782,12 @@ #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F /* query ras mask of enabled features*/ #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS 0x21 + /* Subquery id: Decode */ + #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 + /* Subquery id: Encode */ + #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 /* RAS MASK: UMC (VRAM) */ #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) @@ -875,6 +884,10 @@ struct { __u32 type; } sensor_info; + + struct { + __u32 type; + } video_cap; }; }; @@ -945,6 +958,7 @@ #define AMDGPU_VRAM_TYPE_DDR3 7 #define AMDGPU_VRAM_TYPE_DDR4 8 #define AMDGPU_VRAM_TYPE_GDDR6 9 +#define AMDGPU_VRAM_TYPE_DDR5 10 struct drm_amdgpu_info_device { /** PCI Device ID */ @@ -1070,6 +1084,30 @@ __u32 pad; }; +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 +#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 + +struct drm_amdgpu_info_video_codec_info { + __u32 valid; + __u32 max_width; + __u32 max_height; + __u32 max_pixels_per_frame; + __u32 max_level; + __u32 pad; +}; + +struct drm_amdgpu_info_video_caps { + struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; +}; + /* * Supported GPU families */ @@ -1082,6 +1120,7 @@ #define AMDGPU_FAMILY_AI 141 /* Vega10 */ #define AMDGPU_FAMILY_RV 142 /* Raven */ #define AMDGPU_FAMILY_NV 143 /* Navi10 */ +#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ #if defined(__cplusplus) } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/intel/i915_pciids.h new/libdrm-2.4.105/intel/i915_pciids.h --- old/libdrm-2.4.104/intel/i915_pciids.h 2021-01-11 19:15:27.371363600 +0100 +++ new/libdrm-2.4.105/intel/i915_pciids.h 2021-04-07 16:09:24.167843300 +0200 @@ -170,9 +170,9 @@ #define INTEL_HSW_ULT_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */ + INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */ #define INTEL_HSW_ULX_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ @@ -181,26 +181,26 @@ INTEL_HSW_ULT_GT1_IDS(info), \ INTEL_HSW_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ + INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \ INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ + INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */ #define INTEL_HSW_ULT_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */ + INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \ #define INTEL_HSW_ULX_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ @@ -209,45 +209,45 @@ INTEL_HSW_ULT_GT2_IDS(info), \ INTEL_HSW_ULX_GT2_IDS(info), \ INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ + INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \ INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ + INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */ #define INTEL_HSW_ULT_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */ #define INTEL_HSW_GT3_IDS(info) \ INTEL_HSW_ULT_GT3_IDS(info), \ INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ + INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \ + INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \ INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ + INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \ INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ #define INTEL_HSW_IDS(info) \ INTEL_HSW_GT1_IDS(info), \ @@ -329,17 +329,20 @@ INTEL_VGA_DEVICE(0x22b3, info) #define INTEL_SKL_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */ #define INTEL_SKL_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */ #define INTEL_SKL_GT1_IDS(info) \ INTEL_SKL_ULT_GT1_IDS(info), \ INTEL_SKL_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ + INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */ #define INTEL_SKL_ULT_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ @@ -352,26 +355,26 @@ INTEL_SKL_ULT_GT2_IDS(info), \ INTEL_SKL_ULX_GT2_IDS(info), \ INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ #define INTEL_SKL_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */ + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \ + INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */ #define INTEL_SKL_GT3_IDS(info) \ INTEL_SKL_ULT_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \ + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \ + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */ #define INTEL_SKL_GT4_IDS(info) \ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ + INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \ + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \ + INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */ #define INTEL_SKL_IDS(info) \ INTEL_SKL_GT1_IDS(info), \ @@ -403,8 +406,8 @@ INTEL_KBL_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ + INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \ + INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */ #define INTEL_KBL_ULT_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ @@ -416,10 +419,10 @@ #define INTEL_KBL_GT2_IDS(info) \ INTEL_KBL_ULT_GT2_IDS(info), \ INTEL_KBL_ULX_GT2_IDS(info), \ - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ #define INTEL_KBL_ULT_GT3_IDS(info) \ @@ -444,10 +447,10 @@ /* CML GT1 */ #define INTEL_CML_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x9BA5, info), \ - INTEL_VGA_DEVICE(0x9BA8, info), \ + INTEL_VGA_DEVICE(0x9BA2, info), \ INTEL_VGA_DEVICE(0x9BA4, info), \ - INTEL_VGA_DEVICE(0x9BA2, info) + INTEL_VGA_DEVICE(0x9BA5, info), \ + INTEL_VGA_DEVICE(0x9BA8, info) #define INTEL_CML_U_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x9B21, info), \ @@ -456,11 +459,11 @@ /* CML GT2 */ #define INTEL_CML_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x9BC5, info), \ - INTEL_VGA_DEVICE(0x9BC8, info), \ - INTEL_VGA_DEVICE(0x9BC4, info), \ INTEL_VGA_DEVICE(0x9BC2, info), \ + INTEL_VGA_DEVICE(0x9BC4, info), \ + INTEL_VGA_DEVICE(0x9BC5, info), \ INTEL_VGA_DEVICE(0x9BC6, info), \ + INTEL_VGA_DEVICE(0x9BC8, info), \ INTEL_VGA_DEVICE(0x9BE6, info), \ INTEL_VGA_DEVICE(0x9BF6, info) @@ -494,8 +497,8 @@ INTEL_VGA_DEVICE(0x3E9C, info) #define INTEL_CFL_H_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ - INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ + INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \ + INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */ /* CFL U GT2 */ #define INTEL_CFL_U_GT2_IDS(info) \ @@ -540,73 +543,81 @@ /* CNL */ #define INTEL_CNL_PORT_F_IDS(info) \ - INTEL_VGA_DEVICE(0x5A54, info), \ - INTEL_VGA_DEVICE(0x5A5C, info), \ INTEL_VGA_DEVICE(0x5A44, info), \ - INTEL_VGA_DEVICE(0x5A4C, info) + INTEL_VGA_DEVICE(0x5A4C, info), \ + INTEL_VGA_DEVICE(0x5A54, info), \ + INTEL_VGA_DEVICE(0x5A5C, info) #define INTEL_CNL_IDS(info) \ INTEL_CNL_PORT_F_IDS(info), \ - INTEL_VGA_DEVICE(0x5A51, info), \ - INTEL_VGA_DEVICE(0x5A59, info), \ + INTEL_VGA_DEVICE(0x5A40, info), \ INTEL_VGA_DEVICE(0x5A41, info), \ - INTEL_VGA_DEVICE(0x5A49, info), \ - INTEL_VGA_DEVICE(0x5A52, info), \ - INTEL_VGA_DEVICE(0x5A5A, info), \ INTEL_VGA_DEVICE(0x5A42, info), \ + INTEL_VGA_DEVICE(0x5A49, info), \ INTEL_VGA_DEVICE(0x5A4A, info), \ INTEL_VGA_DEVICE(0x5A50, info), \ - INTEL_VGA_DEVICE(0x5A40, info) + INTEL_VGA_DEVICE(0x5A51, info), \ + INTEL_VGA_DEVICE(0x5A52, info), \ + INTEL_VGA_DEVICE(0x5A59, info), \ + INTEL_VGA_DEVICE(0x5A5A, info) /* ICL */ #define INTEL_ICL_PORT_F_IDS(info) \ INTEL_VGA_DEVICE(0x8A50, info), \ - INTEL_VGA_DEVICE(0x8A5C, info), \ - INTEL_VGA_DEVICE(0x8A59, info), \ - INTEL_VGA_DEVICE(0x8A58, info), \ INTEL_VGA_DEVICE(0x8A52, info), \ + INTEL_VGA_DEVICE(0x8A53, info), \ + INTEL_VGA_DEVICE(0x8A54, info), \ + INTEL_VGA_DEVICE(0x8A56, info), \ + INTEL_VGA_DEVICE(0x8A57, info), \ + INTEL_VGA_DEVICE(0x8A58, info), \ + INTEL_VGA_DEVICE(0x8A59, info), \ INTEL_VGA_DEVICE(0x8A5A, info), \ INTEL_VGA_DEVICE(0x8A5B, info), \ - INTEL_VGA_DEVICE(0x8A57, info), \ - INTEL_VGA_DEVICE(0x8A56, info), \ - INTEL_VGA_DEVICE(0x8A71, info), \ + INTEL_VGA_DEVICE(0x8A5C, info), \ INTEL_VGA_DEVICE(0x8A70, info), \ - INTEL_VGA_DEVICE(0x8A53, info), \ - INTEL_VGA_DEVICE(0x8A54, info) + INTEL_VGA_DEVICE(0x8A71, info) #define INTEL_ICL_11_IDS(info) \ INTEL_ICL_PORT_F_IDS(info), \ INTEL_VGA_DEVICE(0x8A51, info), \ INTEL_VGA_DEVICE(0x8A5D, info) -/* EHL/JSL */ +/* EHL */ #define INTEL_EHL_IDS(info) \ - INTEL_VGA_DEVICE(0x4500, info), \ - INTEL_VGA_DEVICE(0x4571, info), \ - INTEL_VGA_DEVICE(0x4551, info), \ INTEL_VGA_DEVICE(0x4541, info), \ - INTEL_VGA_DEVICE(0x4E71, info), \ - INTEL_VGA_DEVICE(0x4557, info), \ + INTEL_VGA_DEVICE(0x4551, info), \ INTEL_VGA_DEVICE(0x4555, info), \ - INTEL_VGA_DEVICE(0x4E61, info), \ - INTEL_VGA_DEVICE(0x4E57, info), \ + INTEL_VGA_DEVICE(0x4557, info), \ + INTEL_VGA_DEVICE(0x4571, info) + +/* JSL */ +#define INTEL_JSL_IDS(info) \ + INTEL_VGA_DEVICE(0x4E51, info), \ INTEL_VGA_DEVICE(0x4E55, info), \ - INTEL_VGA_DEVICE(0x4E51, info) + INTEL_VGA_DEVICE(0x4E57, info), \ + INTEL_VGA_DEVICE(0x4E61, info), \ + INTEL_VGA_DEVICE(0x4E71, info) /* TGL */ -#define INTEL_TGL_12_IDS(info) \ +#define INTEL_TGL_12_GT1_IDS(info) \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info) + +#define INTEL_TGL_12_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x9A40, info), \ INTEL_VGA_DEVICE(0x9A49, info), \ INTEL_VGA_DEVICE(0x9A59, info), \ - INTEL_VGA_DEVICE(0x9A60, info), \ - INTEL_VGA_DEVICE(0x9A68, info), \ - INTEL_VGA_DEVICE(0x9A70, info), \ INTEL_VGA_DEVICE(0x9A78, info), \ INTEL_VGA_DEVICE(0x9AC0, info), \ INTEL_VGA_DEVICE(0x9AC9, info), \ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) +#define INTEL_TGL_12_IDS(info) \ + INTEL_TGL_12_GT1_IDS(info), \ + INTEL_TGL_12_GT2_IDS(info) + /* RKL */ #define INTEL_RKL_IDS(info) \ INTEL_VGA_DEVICE(0x4C80, info), \ @@ -618,6 +629,20 @@ /* DG1 */ #define INTEL_DG1_IDS(info) \ - INTEL_VGA_DEVICE(0x4905, info) + INTEL_VGA_DEVICE(0x4905, info), \ + INTEL_VGA_DEVICE(0x4906, info), \ + INTEL_VGA_DEVICE(0x4907, info), \ + INTEL_VGA_DEVICE(0x4908, info) + +/* ADL-S */ +#define INTEL_ADLS_IDS(info) \ + INTEL_VGA_DEVICE(0x4680, info), \ + INTEL_VGA_DEVICE(0x4681, info), \ + INTEL_VGA_DEVICE(0x4682, info), \ + INTEL_VGA_DEVICE(0x4683, info), \ + INTEL_VGA_DEVICE(0x4690, info), \ + INTEL_VGA_DEVICE(0x4691, info), \ + INTEL_VGA_DEVICE(0x4692, info), \ + INTEL_VGA_DEVICE(0x4693, info) #endif /* _I915_PCIIDS_H */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/intel/intel_bufmgr_gem.c new/libdrm-2.4.105/intel/intel_bufmgr_gem.c --- old/libdrm-2.4.104/intel/intel_bufmgr_gem.c 2021-01-11 19:15:27.374697000 +0100 +++ new/libdrm-2.4.105/intel/intel_bufmgr_gem.c 2021-04-07 16:09:24.171843300 +0200 @@ -1732,6 +1732,82 @@ return drm_intel_gem_bo_unmap(bo); } +static bool is_cache_coherent(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_caching arg = {}; + + arg.handle = bo_gem->gem_handle; + if (drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_CACHING, &arg)) + assert(false); + return arg.caching != I915_CACHING_NONE; +} + +static void set_domain(drm_intel_bo *bo, uint32_t read, uint32_t write) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_domain arg = {}; + + arg.handle = bo_gem->gem_handle; + arg.read_domains = read; + arg.write_domain = write; + if (drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &arg)) + assert(false); +} + +static int mmap_write(drm_intel_bo *bo, unsigned long offset, + unsigned long length, const void *buf) +{ + void *map = NULL; + + if (!length) + return 0; + + if (is_cache_coherent(bo)) { + map = drm_intel_gem_bo_map__cpu(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); + } + if (!map) { + map = drm_intel_gem_bo_map__wc(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); + } + + assert(map); + memcpy((char *)map + offset, buf, length); + drm_intel_gem_bo_unmap(bo); + return 0; +} + +static int mmap_read(drm_intel_bo *bo, unsigned long offset, + unsigned long length, void *buf) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + void *map = NULL; + + if (!length) + return 0; + + if (bufmgr_gem->has_llc || is_cache_coherent(bo)) { + map = drm_intel_gem_bo_map__cpu(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_CPU, 0); + } + if (!map) { + map = drm_intel_gem_bo_map__wc(bo); + if (map) + set_domain(bo, I915_GEM_DOMAIN_WC, 0); + } + + assert(map); + memcpy(buf, (char *)map + offset, length); + drm_intel_gem_bo_unmap(bo); + return 0; +} + static int drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset, unsigned long size, const void *data) @@ -1752,14 +1828,20 @@ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite); - if (ret != 0) { + if (ret) ret = -errno; + + if (ret != 0 && ret != -EOPNOTSUPP) { DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n", __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, (int)size, strerror(errno)); + return ret; } - return ret; + if (ret == -EOPNOTSUPP) + mmap_write(bo, offset, size, data); + + return 0; } static int @@ -1807,14 +1889,20 @@ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread); - if (ret != 0) { + if (ret) ret = -errno; + + if (ret != 0 && ret != -EOPNOTSUPP) { DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n", __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, (int)size, strerror(errno)); + return ret; } - return ret; + if (ret == -EOPNOTSUPP) + mmap_read(bo, offset, size, data); + + return 0; } /** Waits for all GPU rendering with the object to have completed. */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/intel/intel_chipset.c new/libdrm-2.4.105/intel/intel_chipset.c --- old/libdrm-2.4.104/intel/intel_chipset.c 2021-01-11 19:15:27.374697000 +0100 +++ new/libdrm-2.4.105/intel/intel_chipset.c 2021-04-07 16:09:24.171843300 +0200 @@ -35,9 +35,11 @@ uint16_t gen; } pciids[] = { /* Keep ids sorted by gen; latest gen first */ + INTEL_ADLS_IDS(12), INTEL_RKL_IDS(12), INTEL_DG1_IDS(12), INTEL_TGL_12_IDS(12), + INTEL_JSL_IDS(11), INTEL_EHL_IDS(11), INTEL_ICL_11_IDS(11), INTEL_CNL_IDS(10), diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/intel/meson.build new/libdrm-2.4.105/intel/meson.build --- old/libdrm-2.4.104/intel/meson.build 2021-01-11 19:15:27.374697000 +0100 +++ new/libdrm-2.4.105/intel/meson.build 2021-04-07 16:09:24.171843300 +0200 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_intel = shared_library( +libdrm_intel = library( 'drm_intel', [ files( diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/libkms/meson.build new/libdrm-2.4.105/libkms/meson.build --- old/libdrm-2.4.104/libkms/meson.build 2021-01-11 19:15:27.378030300 +0100 +++ new/libdrm-2.4.105/libkms/meson.build 2021-04-07 16:09:24.171843300 +0200 @@ -41,7 +41,7 @@ libkms_include += include_directories('../exynos') endif -libkms = shared_library( +libkms = library( 'kms', [files_libkms, config_file], c_args : libdrm_c_args, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/meson.build new/libdrm-2.4.105/meson.build --- old/libdrm-2.4.104/meson.build 2021-01-11 19:15:27.378030300 +0100 +++ new/libdrm-2.4.105/meson.build 2021-04-07 16:09:24.175843200 +0200 @@ -21,7 +21,7 @@ project( 'libdrm', ['c'], - version : '2.4.104', + version : '2.4.105', license : 'MIT', meson_version : '>= 0.43', default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], @@ -261,7 +261,7 @@ endif with_man_pages = get_option('man-pages') -prog_rst2man = find_program('rst2man', required: with_man_pages == 'true') +prog_rst2man = find_program('rst2man', 'rst2man.py', required: with_man_pages == 'true') with_man_pages = with_man_pages != 'false' and prog_rst2man.found() config.set10('HAVE_VISIBILITY', @@ -294,7 +294,7 @@ inc_root = include_directories('.') inc_drm = include_directories('include/drm') -libdrm = shared_library( +libdrm = library( 'drm', [files( 'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c', diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/nouveau/meson.build new/libdrm-2.4.105/nouveau/meson.build --- old/libdrm-2.4.104/nouveau/meson.build 2021-01-11 19:15:27.378030300 +0100 +++ new/libdrm-2.4.105/nouveau/meson.build 2021-04-07 16:09:24.175843200 +0200 @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_nouveau = shared_library( +libdrm_nouveau = library( 'drm_nouveau', [files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file], c_args : libdrm_c_args, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/omap/meson.build new/libdrm-2.4.105/omap/meson.build --- old/libdrm-2.4.104/omap/meson.build 2021-01-11 19:15:27.381363900 +0100 +++ new/libdrm-2.4.105/omap/meson.build 2021-04-07 16:09:24.175843200 +0200 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_omap = shared_library( +libdrm_omap = library( 'drm_omap', [files('omap_drm.c'), config_file], include_directories : [inc_root, inc_drm], diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/radeon/meson.build new/libdrm-2.4.105/radeon/meson.build --- old/libdrm-2.4.104/radeon/meson.build 2021-01-11 19:15:27.381363900 +0100 +++ new/libdrm-2.4.105/radeon/meson.build 2021-04-07 16:09:24.175843200 +0200 @@ -19,7 +19,7 @@ # SOFTWARE. -libdrm_radeon = shared_library( +libdrm_radeon = library( 'drm_radeon', [ files( diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tegra/meson.build new/libdrm-2.4.105/tegra/meson.build --- old/libdrm-2.4.104/tegra/meson.build 2021-01-11 19:15:27.381363900 +0100 +++ new/libdrm-2.4.105/tegra/meson.build 2021-04-07 16:09:24.175843200 +0200 @@ -18,7 +18,7 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -libdrm_tegra = shared_library( +libdrm_tegra = library( 'drm_tegra', [files('tegra.c'), config_file], include_directories : [inc_root, inc_drm], diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/amdgpu/amdgpu_test.c new/libdrm-2.4.105/tests/amdgpu/amdgpu_test.c --- old/libdrm-2.4.104/tests/amdgpu/amdgpu_test.c 2021-01-11 19:15:27.381363900 +0100 +++ new/libdrm-2.4.105/tests/amdgpu/amdgpu_test.c 2021-04-07 16:09:24.175843200 +0200 @@ -496,12 +496,6 @@ "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - /* This test was ran on GFX8 and GFX9 only */ if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV) if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE)) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/amdgpu/basic_tests.c new/libdrm-2.4.105/tests/amdgpu/basic_tests.c --- old/libdrm-2.4.104/tests/amdgpu/basic_tests.c 2021-01-11 19:15:27.384697200 +0100 +++ new/libdrm-2.4.105/tests/amdgpu/basic_tests.c 2021-04-07 16:09:24.175843200 +0200 @@ -923,6 +923,15 @@ 0, &vram_info); CU_ASSERT_EQUAL(r, 0); + r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, + 0, >t_info); + CU_ASSERT_EQUAL(r, 0); + + if (vram_info.max_allocation > gtt_info.heap_size/3) { + vram_info.max_allocation = gtt_info.heap_size/3; + gtt_info.max_allocation = vram_info.max_allocation; + } + r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]); CU_ASSERT_EQUAL(r, 0); @@ -930,10 +939,6 @@ AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]); CU_ASSERT_EQUAL(r, 0); - r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, - 0, >t_info); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]); CU_ASSERT_EQUAL(r, 0); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/amdgpu/bo_tests.c new/libdrm-2.4.105/tests/amdgpu/bo_tests.c --- old/libdrm-2.4.104/tests/amdgpu/bo_tests.c 2021-01-11 19:15:27.384697200 +0100 +++ new/libdrm-2.4.105/tests/amdgpu/bo_tests.c 2021-04-07 16:09:24.179843000 +0200 @@ -168,7 +168,7 @@ struct amdgpu_bo_info info = {0}; int r; - meta.size_metadata = 1; + meta.size_metadata = 4; meta.umd_metadata[0] = 0xdeadbeef; r = amdgpu_bo_set_metadata(buffer_handle, &meta); @@ -177,7 +177,7 @@ r = amdgpu_bo_query_info(buffer_handle, &info); CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(info.metadata.size_metadata, 1); + CU_ASSERT_EQUAL(info.metadata.size_metadata, 4); CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef); } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/amdgpu/syncobj_tests.c new/libdrm-2.4.105/tests/amdgpu/syncobj_tests.c --- old/libdrm-2.4.104/tests/amdgpu/syncobj_tests.c 2021-01-11 19:15:27.384697200 +0100 +++ new/libdrm-2.4.105/tests/amdgpu/syncobj_tests.c 2021-04-07 16:09:24.179843000 +0200 @@ -99,7 +99,7 @@ uint32_t expired; int i, r; uint64_t seq_no; - static uint32_t *ptr; + uint32_t *ptr; r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/amdgpu/vcn_tests.c new/libdrm-2.4.105/tests/amdgpu/vcn_tests.c --- old/libdrm-2.4.104/tests/amdgpu/vcn_tests.c 2021-01-11 19:15:27.384697200 +0100 +++ new/libdrm-2.4.105/tests/amdgpu/vcn_tests.c 2021-04-07 16:09:24.179843000 +0200 @@ -102,8 +102,6 @@ return CU_FALSE; family_id = device_handle->info.family_id; - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; asic_id = device_handle->info.asic_id; chip_rev = device_handle->info.chip_rev; chip_id = device_handle->info.chip_external_rev; @@ -142,7 +140,9 @@ reg.cntl = 0x81c6; } } else if (family_id == AMDGPU_FAMILY_NV) { - if (chip_id == (chip_rev + 0x28)) { + if (chip_id == (chip_rev + 0x28) || + chip_id == (chip_rev + 0x32) || + chip_id == (chip_rev + 0x3c)) { reg.data0 = 0x10; reg.data1 = 0x11; reg.cmd = 0xf; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/util/kms.c new/libdrm-2.4.105/tests/util/kms.c --- old/libdrm-2.4.104/tests/util/kms.c 2021-01-11 19:15:27.391364000 +0100 +++ new/libdrm-2.4.105/tests/util/kms.c 2021-04-07 16:09:24.183843000 +0200 @@ -149,6 +149,7 @@ "armada-drm", "komeda", "imx-dcss", + "mxsfb-drm", }; int util_open(const char *device, const char *module) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/tests/util/pattern.c new/libdrm-2.4.105/tests/util/pattern.c --- old/libdrm-2.4.104/tests/util/pattern.c 2021-01-11 19:15:27.391364000 +0100 +++ new/libdrm-2.4.105/tests/util/pattern.c 2021-04-07 16:09:24.183843000 +0200 @@ -985,7 +985,6 @@ unsigned int stride) { const struct util_rgb_info *rgb = &info->rgb; - void *mem_base = mem; unsigned int x, y; /* TODO: Give this actual fp16 precision */ @@ -1113,7 +1112,7 @@ unsigned int width, unsigned int height, unsigned int stride) { - int i, j; + unsigned int i, j; for (i = 0; i < height / 2; i++) { uint32_t *row = mem; @@ -1141,7 +1140,7 @@ unsigned int width, unsigned int height, unsigned int stride) { - int i, j; + unsigned int i, j; for (i = 0; i < height / 2; i++) { uint64_t *row = mem; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/xf86drm.c new/libdrm-2.4.105/xf86drm.c --- old/libdrm-2.4.104/xf86drm.c 2021-01-11 19:15:27.391364000 +0100 +++ new/libdrm-2.4.105/xf86drm.c 2021-04-07 16:09:24.183843000 +0200 @@ -1351,7 +1351,12 @@ retval = drmMalloc(sizeof(*retval)); retval->count = info.count; - retval->list = drmMalloc(info.count * sizeof(*retval->list)); + if (!(retval->list = drmMalloc(info.count * sizeof(*retval->list)))) { + drmFree(retval); + drmFree(info.list); + return NULL; + } + for (i = 0; i < info.count; i++) { retval->list[i].count = info.list[i].count; retval->list[i].size = info.list[i].size; @@ -4272,6 +4277,10 @@ } closedir(sysdir); + + if (devices != NULL) + return MIN2(device_count, max_devices); + return device_count; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/xf86drm.h new/libdrm-2.4.105/xf86drm.h --- old/libdrm-2.4.104/xf86drm.h 2021-01-11 19:15:27.391364000 +0100 +++ new/libdrm-2.4.105/xf86drm.h 2021-04-07 16:09:24.183843000 +0200 @@ -813,6 +813,24 @@ extern char *drmGetDeviceNameFromFd2(int fd); extern int drmGetNodeTypeFromFd(int fd); +/* Convert between GEM handles and DMA-BUF file descriptors. + * + * Warning: since GEM handles are not reference-counted and are unique per + * DRM file description, the caller is expected to perform its own reference + * counting. drmPrimeFDToHandle is guaranteed to return the same handle for + * different FDs if they reference the same underlying buffer object. This + * could even be a buffer object originally created on the same DRM FD. + * + * When sharing a DRM FD with an API such as EGL or GBM, the caller must not + * use drmPrimeHandleToFD nor drmPrimeFDToHandle. A single user-space + * reference-counting implementation is necessary to avoid double-closing GEM + * handles. + * + * Two processes can't share the same DRM FD and both use it to create or + * import GEM handles, even when using a single user-space reference-counting + * implementation like GBM, because GBM doesn't share its state between + * processes. + */ extern int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd); extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/xf86drmMode.c new/libdrm-2.4.105/xf86drmMode.c --- old/libdrm-2.4.104/xf86drmMode.c 2021-01-11 19:15:27.391364000 +0100 +++ new/libdrm-2.4.105/xf86drmMode.c 2021-04-07 16:09:24.183843000 +0200 @@ -146,6 +146,16 @@ * ModeSetting functions. */ +drm_public int drmIsKMS(int fd) +{ + struct drm_mode_card_res res = {0}; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res) != 0) + return 0; + + return res.count_crtcs > 0 && res.count_connectors > 0 && res.count_encoders > 0; +} + drm_public drmModeResPtr drmModeGetResources(int fd) { struct drm_mode_card_res res, counts; @@ -279,8 +289,10 @@ memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); - if (modifier) + if (modifier) { + f.flags |= DRM_MODE_FB_MODIFIERS; memcpy(f.modifier, modifier, 4 * sizeof(modifier[0])); + } if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) return ret; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/libdrm-2.4.104/xf86drmMode.h new/libdrm-2.4.105/xf86drmMode.h --- old/libdrm-2.4.104/xf86drmMode.h 2021-01-11 19:15:27.391364000 +0100 +++ new/libdrm-2.4.105/xf86drmMode.h 2021-04-07 16:09:24.183843000 +0200 @@ -151,6 +151,11 @@ return property->flags & type; } +static inline uint32_t drmModeGetPropertyType(const drmModePropertyRes *prop) +{ + return prop->flags & (DRM_MODE_PROP_LEGACY_TYPE | DRM_MODE_PROP_EXTENDED_TYPE); +} + typedef struct _drmModeCrtc { uint32_t crtc_id; uint32_t buffer_id; /**< FB id to connect to 0 = disconnect */ @@ -260,6 +265,13 @@ extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr); /** + * Check whether the DRM node supports Kernel Mode-Setting. + * + * Returns 1 if suitable for KMS, 0 otherwise. + */ +extern int drmIsKMS(int fd); + +/** * Retrieves all of the resources associated with a card. */ extern drmModeResPtr drmModeGetResources(int fd);
