Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package spirv-headers for openSUSE:Factory checked in at 2025-09-25 18:43:46 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/spirv-headers (Old) and /work/SRC/openSUSE:Factory/.spirv-headers.new.11973 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "spirv-headers" Thu Sep 25 18:43:46 2025 rev:52 rq:1306801 version:1.6.4+sdk321+gc8ad050 Changes: -------- --- /work/SRC/openSUSE:Factory/spirv-headers/spirv-headers.changes 2025-07-20 15:29:06.884175485 +0200 +++ /work/SRC/openSUSE:Factory/.spirv-headers.new.11973/spirv-headers.changes 2025-09-25 18:43:53.926663989 +0200 @@ -1,0 +2,7 @@ +Tue Sep 23 10:17:38 UTC 2025 - Jan Engelhardt <[email protected]> + +- Update to snapshot 1.6.4+sdk321+gc8ad050 (Git c8ad050) + * Added SPV_QCOM_cooperative_matrix_conversion, + SPV_INTEL_function_variants + +------------------------------------------------------------------- Old: ---- 2a611a970fdbc41ac2e3e328802aed9985352dca.tar.gz New: ---- c8ad050fcb29e42a2f57d9f59e97488f465c436d.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ spirv-headers.spec ++++++ --- /var/tmp/diff_new_pack.RU3GAA/_old 2025-09-25 18:43:54.726697475 +0200 +++ /var/tmp/diff_new_pack.RU3GAA/_new 2025-09-25 18:43:54.734697809 +0200 @@ -30,9 +30,9 @@ %endif Name: spirv-headers -Version: 1.6.4+sdk321 +Version: 1.6.4+sdk321+gc8ad050 %define innerver 1.4.321 -%define rev 2a611a970fdbc41ac2e3e328802aed9985352dca +%define rev c8ad050fcb29e42a2f57d9f59e97488f465c436d Release: 0 Summary: Machine-readable files from the SPIR-V registry License: MIT ++++++ _scmsync.obsinfo ++++++ --- /var/tmp/diff_new_pack.RU3GAA/_old 2025-09-25 18:43:54.782699819 +0200 +++ /var/tmp/diff_new_pack.RU3GAA/_new 2025-09-25 18:43:54.790700153 +0200 @@ -1,5 +1,5 @@ -mtime: 1752734329 -commit: e918d0f8cf07656603defca3e583bda98d971efe8715877ff61fa912d4fe9ace +mtime: 1758660709 +commit: 10ef8b754390730e0801f8b186817487d2830d557e87fe2349e51ab5104f5879 url: https://src.opensuse.org/jengelh/spirv-headers revision: master ++++++ build.specials.obscpio ++++++ ++++++ build.specials.obscpio ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/.gitignore new/.gitignore --- old/.gitignore 1970-01-01 01:00:00.000000000 +0100 +++ new/.gitignore 2025-09-23 22:51:59.000000000 +0200 @@ -0,0 +1 @@ +.osc ++++++ 2a611a970fdbc41ac2e3e328802aed9985352dca.tar.gz -> c8ad050fcb29e42a2f57d9f59e97488f465c436d.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/.github/workflows/presubmit.yml new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/.github/workflows/presubmit.yml --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/.github/workflows/presubmit.yml 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/.github/workflows/presubmit.yml 2025-07-03 10:33:06.000000000 +0200 @@ -131,3 +131,16 @@ run: | cmake -S tests/pkg_config -B tests/pkg_config/build/ -D CMAKE_PREFIX_PATH=${GITHUB_WORKSPACE}/build/install cmake --build tests/pkg_config/build/ + + license-check: + name: Verify repository license compliance + runs-on: ubuntu-latest + # We now refer to the container by its SHA instead of the name, to prevent + # caching problems when updating the image. + # container: khronosgroup/docker-images:asciidoctor-spec.20240726 + container: khronosgroup/docker-images@sha256:724f67d8562445523644abf017d5d192b369fafc122de75e9d26792c649821a0 + + steps: + - uses: actions/checkout@v4 + - name: REUSE license checker + run: reuse lint \ No newline at end of file diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/LICENSES/CC-BY-4.0.txt new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/LICENSES/CC-BY-4.0.txt --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/LICENSES/CC-BY-4.0.txt 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/LICENSES/CC-BY-4.0.txt 2025-07-03 10:33:06.000000000 +0200 @@ -1,396 +1,156 @@ -Attribution 4.0 International +Creative Commons Attribution 4.0 International -======================================================================= - -Creative Commons Corporation ("Creative Commons") is not a law firm and -does not provide legal services or legal advice. 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If the provision cannot be reformed, it shall be severed from this Public License without affecting the enforceability of the remaining terms and conditions. + + c. No term or condition of this Public License will be waived and no failure to comply consented to unless expressly agreed to by the Licensor. + + d. Nothing in this Public License constitutes or may be interpreted as a limitation upon, or waiver of, any privileges and immunities that apply to the Licensor or You, including from the legal processes of any jurisdiction or authority. + +Creative Commons is not a party to its public licenses. Notwithstanding, Creative Commons may elect to apply one of its public licenses to material it publishes and in those instances will be considered the “Licensor.” Except for the limited purpose of indicating that material is shared under a Creative Commons public license or as otherwise permitted by the Creative Commons policies published at creativecommons.org/policies, Creative Commons does not authorize the use of the trademark “Creative Commons” or any other trademark or logo of Creative Commons without its prior written consent including, without limitation, in connection with any unauthorized modifications to any of its public licenses or any other arrangements, understandings, or agreements concerning use of licensed material. For the avoidance of doubt, this paragraph does not form part of the public licenses. + +Creative Commons may be contacted at creativecommons.org. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/MODULE.bazel new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/MODULE.bazel --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/MODULE.bazel 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/MODULE.bazel 2025-07-03 10:33:06.000000000 +0200 @@ -1,3 +1,5 @@ +# SPDX-FileCopyrightText: The Khronos Group, Inc. +# SPDX-License-Identifier: MIT """SPIRV-Headers""" module( diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/REUSE.toml new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/REUSE.toml --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/REUSE.toml 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/REUSE.toml 2025-07-03 10:33:06.000000000 +0200 @@ -30,6 +30,7 @@ [[annotations]] path = [ "BUILD.bazel", + "MODULE.bazel", "cmake/SPIRV-Headers.pc.in", "tools/buildHeaders/CMakeLists.txt", "tools/buildHeaders/bin/makeExtinstHeaders.py", diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/TOSA.001000.1.h new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/TOSA.001000.1.h --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/TOSA.001000.1.h 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/TOSA.001000.1.h 2025-07-03 10:33:06.000000000 +0200 @@ -1,4 +1,5 @@ -// (c) 2022-2025 Arm Ltd. +// SPDX-FileCopyrightText: 2022-2025 Arm Ltd. +// SPDX-License-Identifier: MIT #ifndef SPIRV_UNIFIED1_TOSA_001000_1_H_ #define SPIRV_UNIFIED1_TOSA_001000_1_H_ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/extinst.tosa.001000.1.grammar.json new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/extinst.tosa.001000.1.grammar.json --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/extinst.tosa.001000.1.grammar.json 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/extinst.tosa.001000.1.grammar.json 2025-07-03 10:33:06.000000000 +0200 @@ -1,6 +1,7 @@ { "copyright": [ - "(c) 2022-2025 Arm Ltd." + "SPDX-FileCopyrightText: 2022-2025 Arm Ltd.", + "SPDX-License-Identifier: MIT" ], "version": 1000000, "revision": 1, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.bf new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.bf --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.bf 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.bf 2025-07-03 10:33:06.000000000 +0200 @@ -655,6 +655,7 @@ HostAccessINTEL = 6188, InitModeINTEL = 6190, ImplementInRegisterMapINTEL = 6191, + ConditionalINTEL = 6247, CacheControlLoadINTEL = 6442, CacheControlStoreINTEL = 6443, Max = 0x7fffffff, @@ -1137,6 +1138,7 @@ TextureBoxFilterQCOM = 4485, TextureBlockMatchQCOM = 4486, TileShadingQCOM = 4495, + CooperativeMatrixConversionQCOM = 4496, TextureBlockMatch2QCOM = 4498, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, @@ -1312,6 +1314,8 @@ Subgroup2DBlockTransposeINTEL = 6230, SubgroupMatrixMultiplyAccumulateINTEL = 6236, TernaryBitwiseFunctionINTEL = 6241, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, GroupUniformArithmeticKHR = 6400, TensorFloat32RoundingINTEL = 6425, MaskedGatherScatterINTEL = 6427, @@ -2078,10 +2082,14 @@ OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2472,6 +2480,13 @@ OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.core.grammar.json new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.core.grammar.json --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.core.grammar.json 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.core.grammar.json 2025-07-03 10:33:06.000000000 +0200 @@ -5269,6 +5269,18 @@ "version" : "None" }, { + "opname" : "OpBitCastArrayQCOM", + "class" : "Conversion", + "opcode" : 4497, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Array" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, + { "opname" : "OpImageBlockMatchWindowSSDQCOM", "class" : "Image", "opcode" : 4500, @@ -5333,6 +5345,43 @@ "version" : "None" }, { + "opname" : "OpCompositeConstructCoopMatQCOM", + "class" : "Composite", + "opcode" : 4540, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Array" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, + { + "opname" : "OpCompositeExtractCoopMatQCOM", + "class" : "Composite", + "opcode" : 4541, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Cooperative Matrix" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, + { + "opname" : "OpExtractSubArrayQCOM", + "class" : "Composite", + "opcode" : 4542, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Array" }, + { "kind" : "IdRef", "name" : "index" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, + { "opname" : "OpGroupIAddNonUniformAMD", "class" : "Group", "opcode" : 5000, @@ -10778,6 +10827,101 @@ "version" : "None" }, { + "opname" : "OpConditionalExtensionINTEL", + "class" : "Extension", + "opcode" : 6248, + "operands" : [ + { "kind" : "IdRef", "name" : "Condition" }, + { "kind" : "LiteralString", "name" : "Name" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { + "opname" : "OpConditionalEntryPointINTEL", + "class" : "Mode-Setting", + "opcode" : 6249, + "operands" : [ + { "kind" : "IdRef", "name" : "Condition" }, + { "kind" : "ExecutionModel" }, + { "kind" : "IdRef", "name" : "Entry Point" }, + { "kind" : "LiteralString", "name" : "Name" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "Interface" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { + "opname" : "OpConditionalCapabilityINTEL", + "class" : "Mode-Setting", + "opcode" : 6250, + "operands" : [ + { "kind" : "IdRef", "name" : "Condition" }, + { "kind" : "Capability", "name" : "Capability" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { + "opname" : "OpSpecConstantTargetINTEL", + "class" : "Constant-Creation", + "opcode" : 6251, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "LiteralInteger", "name" : "Target" }, + { "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Features" } + ], + "capabilities" : [ "FunctionVariantsINTEL" ], + "provisional" : true, + "version": "None" + }, + { + "opname" : "OpSpecConstantArchitectureINTEL", + "class" : "Constant-Creation", + "opcode" : 6252, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "LiteralInteger", "name" : "Category" }, + { "kind" : "LiteralInteger", "name" : "Family" }, + { "kind" : "LiteralInteger", "name" : "Opcode" }, + { "kind" : "LiteralInteger", "name" : "Architecture" } + ], + "capabilities" : [ "FunctionVariantsINTEL" ], + "provisional" : true, + "version": "None" + }, + { + "opname" : "OpSpecConstantCapabilitiesINTEL", + "class" : "Constant-Creation", + "opcode" : 6253, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "Capability", "quantifier" : "*", "name" : "Capabilities" } + ], + "capabilities" : [ "FunctionVariantsINTEL" ], + "provisional" : true, + "version": "None" + }, + { + "opname" : "OpConditionalCopyObjectINTEL", + "class" : "Composite", + "opcode" : 6254, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "Condition 0, Operand 0, +\nCondition 1, Operand 1, +\n..." } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { "opname" : "OpGroupIMulKHR", "class" : "Group", "opcode" : 6401, @@ -14901,6 +15045,16 @@ "version" : "None" }, { + "enumerant" : "ConditionalINTEL", + "value" : 6247, + "parameters": [ + { "kind" : "IdRef", "name" : "Condition" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { "enumerant" : "CacheControlLoadINTEL", "value" : 6442, "capabilities" : [ "CacheControlsINTEL" ], @@ -16584,6 +16738,13 @@ "version" : "None" }, { + "enumerant" : "CooperativeMatrixConversionQCOM", + "value" : 4496, + "capabilities" : [ "CooperativeMatrixKHR" ], + "extensions" : [ "SPV_QCOM_cooperative_matrix_conversion" ], + "version" : "None" + }, + { "enumerant" : "TextureBlockMatch2QCOM", "value" : 4498, "extensions" : [ "SPV_QCOM_image_processing2" ], @@ -17564,6 +17725,21 @@ "version" : "None" }, { + "enumerant" : "SpecConditionalINTEL", + "value" : 6245, + "extensions" : [ "SPV_INTEL_function_variants" ], + "provisional" : true, + "version": "None" + }, + { + "enumerant" : "FunctionVariantsINTEL", + "value" : 6246, + "capabilities" : [ "SpecConditionalINTEL" ], + "extensions" : [ "SPV_INTEL_function_variants" ], + "provisional" : true, + "version": "None" + }, + { "enumerant" : "GroupUniformArithmeticKHR", "value" : 6400, "extensions" : [ "SPV_KHR_uniform_group_instructions"], diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.cs new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.cs --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.cs 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.cs 2025-07-03 10:33:06.000000000 +0200 @@ -654,6 +654,7 @@ HostAccessINTEL = 6188, InitModeINTEL = 6190, ImplementInRegisterMapINTEL = 6191, + ConditionalINTEL = 6247, CacheControlLoadINTEL = 6442, CacheControlStoreINTEL = 6443, Max = 0x7fffffff, @@ -1136,6 +1137,7 @@ TextureBoxFilterQCOM = 4485, TextureBlockMatchQCOM = 4486, TileShadingQCOM = 4495, + CooperativeMatrixConversionQCOM = 4496, TextureBlockMatch2QCOM = 4498, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, @@ -1311,6 +1313,8 @@ Subgroup2DBlockTransposeINTEL = 6230, SubgroupMatrixMultiplyAccumulateINTEL = 6236, TernaryBitwiseFunctionINTEL = 6241, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, GroupUniformArithmeticKHR = 6400, TensorFloat32RoundingINTEL = 6425, MaskedGatherScatterINTEL = 6427, @@ -2077,10 +2081,14 @@ OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2471,6 +2479,13 @@ OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.h new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.h --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.h 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.h 2025-07-03 10:33:06.000000000 +0200 @@ -642,6 +642,7 @@ SpvDecorationHostAccessINTEL = 6188, SpvDecorationInitModeINTEL = 6190, SpvDecorationImplementInRegisterMapINTEL = 6191, + SpvDecorationConditionalINTEL = 6247, SpvDecorationCacheControlLoadINTEL = 6442, SpvDecorationCacheControlStoreINTEL = 6443, SpvDecorationMax = 0x7fffffff, @@ -1107,6 +1108,7 @@ SpvCapabilityTextureBoxFilterQCOM = 4485, SpvCapabilityTextureBlockMatchQCOM = 4486, SpvCapabilityTileShadingQCOM = 4495, + SpvCapabilityCooperativeMatrixConversionQCOM = 4496, SpvCapabilityTextureBlockMatch2QCOM = 4498, SpvCapabilityFloat16ImageAMD = 5008, SpvCapabilityImageGatherBiasLodAMD = 5009, @@ -1282,6 +1284,8 @@ SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230, SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236, SpvCapabilityTernaryBitwiseFunctionINTEL = 6241, + SpvCapabilitySpecConditionalINTEL = 6245, + SpvCapabilityFunctionVariantsINTEL = 6246, SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityTensorFloat32RoundingINTEL = 6425, SpvCapabilityMaskedGatherScatterINTEL = 6427, @@ -2012,10 +2016,14 @@ SpvOpImageBoxFilterQCOM = 4481, SpvOpImageBlockMatchSSDQCOM = 4482, SpvOpImageBlockMatchSADQCOM = 4483, + SpvOpBitCastArrayQCOM = 4497, SpvOpImageBlockMatchWindowSSDQCOM = 4500, SpvOpImageBlockMatchWindowSADQCOM = 4501, SpvOpImageBlockMatchGatherSSDQCOM = 4502, SpvOpImageBlockMatchGatherSADQCOM = 4503, + SpvOpCompositeConstructCoopMatQCOM = 4540, + SpvOpCompositeExtractCoopMatQCOM = 4541, + SpvOpExtractSubArrayQCOM = 4542, SpvOpGroupIAddNonUniformAMD = 5000, SpvOpGroupFAddNonUniformAMD = 5001, SpvOpGroupFMinNonUniformAMD = 5002, @@ -2406,6 +2414,13 @@ SpvOpSubgroup2DBlockStoreINTEL = 6235, SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237, SpvOpBitwiseFunctionINTEL = 6242, + SpvOpConditionalExtensionINTEL = 6248, + SpvOpConditionalEntryPointINTEL = 6249, + SpvOpConditionalCapabilityINTEL = 6250, + SpvOpSpecConstantTargetINTEL = 6251, + SpvOpSpecConstantArchitectureINTEL = 6252, + SpvOpSpecConstantCapabilitiesINTEL = 6253, + SpvOpConditionalCopyObjectINTEL = 6254, SpvOpGroupIMulKHR = 6401, SpvOpGroupFMulKHR = 6402, SpvOpGroupBitwiseAndKHR = 6403, @@ -2836,10 +2851,14 @@ case SpvOpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpBitCastArrayQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchWindowSSDQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchWindowSADQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchGatherSSDQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchGatherSADQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpCompositeConstructCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpCompositeExtractCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpExtractSubArrayQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -3225,6 +3244,13 @@ case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; @@ -3765,6 +3791,7 @@ case SpvDecorationHostAccessINTEL: return "HostAccessINTEL"; case SpvDecorationInitModeINTEL: return "InitModeINTEL"; case SpvDecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; + case SpvDecorationConditionalINTEL: return "ConditionalINTEL"; case SpvDecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL"; case SpvDecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL"; default: return "Unknown"; @@ -4055,6 +4082,7 @@ case SpvCapabilityTextureBoxFilterQCOM: return "TextureBoxFilterQCOM"; case SpvCapabilityTextureBlockMatchQCOM: return "TextureBlockMatchQCOM"; case SpvCapabilityTileShadingQCOM: return "TileShadingQCOM"; + case SpvCapabilityCooperativeMatrixConversionQCOM: return "CooperativeMatrixConversionQCOM"; case SpvCapabilityTextureBlockMatch2QCOM: return "TextureBlockMatch2QCOM"; case SpvCapabilityFloat16ImageAMD: return "Float16ImageAMD"; case SpvCapabilityImageGatherBiasLodAMD: return "ImageGatherBiasLodAMD"; @@ -4204,6 +4232,8 @@ case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; case SpvCapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; + case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; @@ -4809,10 +4839,14 @@ case SpvOpImageBoxFilterQCOM: return "OpImageBoxFilterQCOM"; case SpvOpImageBlockMatchSSDQCOM: return "OpImageBlockMatchSSDQCOM"; case SpvOpImageBlockMatchSADQCOM: return "OpImageBlockMatchSADQCOM"; + case SpvOpBitCastArrayQCOM: return "OpBitCastArrayQCOM"; case SpvOpImageBlockMatchWindowSSDQCOM: return "OpImageBlockMatchWindowSSDQCOM"; case SpvOpImageBlockMatchWindowSADQCOM: return "OpImageBlockMatchWindowSADQCOM"; case SpvOpImageBlockMatchGatherSSDQCOM: return "OpImageBlockMatchGatherSSDQCOM"; case SpvOpImageBlockMatchGatherSADQCOM: return "OpImageBlockMatchGatherSADQCOM"; + case SpvOpCompositeConstructCoopMatQCOM: return "OpCompositeConstructCoopMatQCOM"; + case SpvOpCompositeExtractCoopMatQCOM: return "OpCompositeExtractCoopMatQCOM"; + case SpvOpExtractSubArrayQCOM: return "OpExtractSubArrayQCOM"; case SpvOpGroupIAddNonUniformAMD: return "OpGroupIAddNonUniformAMD"; case SpvOpGroupFAddNonUniformAMD: return "OpGroupFAddNonUniformAMD"; case SpvOpGroupFMinNonUniformAMD: return "OpGroupFMinNonUniformAMD"; @@ -5198,6 +5232,13 @@ case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; case SpvOpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; + case SpvOpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; + case SpvOpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; + case SpvOpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; + case SpvOpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; + case SpvOpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case SpvOpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case SpvOpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; case SpvOpGroupIMulKHR: return "OpGroupIMulKHR"; case SpvOpGroupFMulKHR: return "OpGroupFMulKHR"; case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.hpp new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.hpp --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.hpp 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.hpp 2025-07-03 10:33:06.000000000 +0200 @@ -638,6 +638,7 @@ DecorationHostAccessINTEL = 6188, DecorationInitModeINTEL = 6190, DecorationImplementInRegisterMapINTEL = 6191, + DecorationConditionalINTEL = 6247, DecorationCacheControlLoadINTEL = 6442, DecorationCacheControlStoreINTEL = 6443, DecorationMax = 0x7fffffff, @@ -1103,6 +1104,7 @@ CapabilityTextureBoxFilterQCOM = 4485, CapabilityTextureBlockMatchQCOM = 4486, CapabilityTileShadingQCOM = 4495, + CapabilityCooperativeMatrixConversionQCOM = 4496, CapabilityTextureBlockMatch2QCOM = 4498, CapabilityFloat16ImageAMD = 5008, CapabilityImageGatherBiasLodAMD = 5009, @@ -1278,6 +1280,8 @@ CapabilitySubgroup2DBlockTransposeINTEL = 6230, CapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236, CapabilityTernaryBitwiseFunctionINTEL = 6241, + CapabilitySpecConditionalINTEL = 6245, + CapabilityFunctionVariantsINTEL = 6246, CapabilityGroupUniformArithmeticKHR = 6400, CapabilityTensorFloat32RoundingINTEL = 6425, CapabilityMaskedGatherScatterINTEL = 6427, @@ -2008,10 +2012,14 @@ OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2402,6 +2410,13 @@ OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403, @@ -2832,10 +2847,14 @@ case OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; case OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; case OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; + case OpBitCastArrayQCOM: *hasResult = true; *hasResultType = true; break; case OpImageBlockMatchWindowSSDQCOM: *hasResult = true; *hasResultType = true; break; case OpImageBlockMatchWindowSADQCOM: *hasResult = true; *hasResultType = true; break; case OpImageBlockMatchGatherSSDQCOM: *hasResult = true; *hasResultType = true; break; case OpImageBlockMatchGatherSADQCOM: *hasResult = true; *hasResultType = true; break; + case OpCompositeConstructCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case OpCompositeExtractCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case OpExtractSubArrayQCOM: *hasResult = true; *hasResultType = true; break; case OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -3221,6 +3240,13 @@ case OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; case OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; case OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; + case OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; + case OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; + case OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; + case OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; + case OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; @@ -3761,6 +3787,7 @@ case DecorationHostAccessINTEL: return "HostAccessINTEL"; case DecorationInitModeINTEL: return "InitModeINTEL"; case DecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; + case DecorationConditionalINTEL: return "ConditionalINTEL"; case DecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL"; case DecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL"; default: return "Unknown"; @@ -4051,6 +4078,7 @@ case CapabilityTextureBoxFilterQCOM: return "TextureBoxFilterQCOM"; case CapabilityTextureBlockMatchQCOM: return "TextureBlockMatchQCOM"; case CapabilityTileShadingQCOM: return "TileShadingQCOM"; + case CapabilityCooperativeMatrixConversionQCOM: return "CooperativeMatrixConversionQCOM"; case CapabilityTextureBlockMatch2QCOM: return "TextureBlockMatch2QCOM"; case CapabilityFloat16ImageAMD: return "Float16ImageAMD"; case CapabilityImageGatherBiasLodAMD: return "ImageGatherBiasLodAMD"; @@ -4200,6 +4228,8 @@ case CapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; case CapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; case CapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; + case CapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case CapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; case CapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; @@ -4805,10 +4835,14 @@ case OpImageBoxFilterQCOM: return "OpImageBoxFilterQCOM"; case OpImageBlockMatchSSDQCOM: return "OpImageBlockMatchSSDQCOM"; case OpImageBlockMatchSADQCOM: return "OpImageBlockMatchSADQCOM"; + case OpBitCastArrayQCOM: return "OpBitCastArrayQCOM"; case OpImageBlockMatchWindowSSDQCOM: return "OpImageBlockMatchWindowSSDQCOM"; case OpImageBlockMatchWindowSADQCOM: return "OpImageBlockMatchWindowSADQCOM"; case OpImageBlockMatchGatherSSDQCOM: return "OpImageBlockMatchGatherSSDQCOM"; case OpImageBlockMatchGatherSADQCOM: return "OpImageBlockMatchGatherSADQCOM"; + case OpCompositeConstructCoopMatQCOM: return "OpCompositeConstructCoopMatQCOM"; + case OpCompositeExtractCoopMatQCOM: return "OpCompositeExtractCoopMatQCOM"; + case OpExtractSubArrayQCOM: return "OpExtractSubArrayQCOM"; case OpGroupIAddNonUniformAMD: return "OpGroupIAddNonUniformAMD"; case OpGroupFAddNonUniformAMD: return "OpGroupFAddNonUniformAMD"; case OpGroupFMinNonUniformAMD: return "OpGroupFMinNonUniformAMD"; @@ -5194,6 +5228,13 @@ case OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; case OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; case OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; + case OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; + case OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; + case OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; + case OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; + case OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; case OpGroupIMulKHR: return "OpGroupIMulKHR"; case OpGroupFMulKHR: return "OpGroupFMulKHR"; case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.hpp11 new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.hpp11 --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.hpp11 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.hpp11 2025-07-03 10:33:06.000000000 +0200 @@ -638,6 +638,7 @@ HostAccessINTEL = 6188, InitModeINTEL = 6190, ImplementInRegisterMapINTEL = 6191, + ConditionalINTEL = 6247, CacheControlLoadINTEL = 6442, CacheControlStoreINTEL = 6443, Max = 0x7fffffff, @@ -1103,6 +1104,7 @@ TextureBoxFilterQCOM = 4485, TextureBlockMatchQCOM = 4486, TileShadingQCOM = 4495, + CooperativeMatrixConversionQCOM = 4496, TextureBlockMatch2QCOM = 4498, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, @@ -1278,6 +1280,8 @@ Subgroup2DBlockTransposeINTEL = 6230, SubgroupMatrixMultiplyAccumulateINTEL = 6236, TernaryBitwiseFunctionINTEL = 6241, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, GroupUniformArithmeticKHR = 6400, TensorFloat32RoundingINTEL = 6425, MaskedGatherScatterINTEL = 6427, @@ -2008,10 +2012,14 @@ OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2402,6 +2410,13 @@ OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403, @@ -2832,10 +2847,14 @@ case Op::OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpBitCastArrayQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchWindowSSDQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchWindowSADQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchGatherSSDQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchGatherSADQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpCompositeConstructCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpCompositeExtractCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpExtractSubArrayQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -3221,6 +3240,13 @@ case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; @@ -3761,6 +3787,7 @@ case Decoration::HostAccessINTEL: return "HostAccessINTEL"; case Decoration::InitModeINTEL: return "InitModeINTEL"; case Decoration::ImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; + case Decoration::ConditionalINTEL: return "ConditionalINTEL"; case Decoration::CacheControlLoadINTEL: return "CacheControlLoadINTEL"; case Decoration::CacheControlStoreINTEL: return "CacheControlStoreINTEL"; default: return "Unknown"; @@ -4051,6 +4078,7 @@ case Capability::TextureBoxFilterQCOM: return "TextureBoxFilterQCOM"; case Capability::TextureBlockMatchQCOM: return "TextureBlockMatchQCOM"; case Capability::TileShadingQCOM: return "TileShadingQCOM"; + case Capability::CooperativeMatrixConversionQCOM: return "CooperativeMatrixConversionQCOM"; case Capability::TextureBlockMatch2QCOM: return "TextureBlockMatch2QCOM"; case Capability::Float16ImageAMD: return "Float16ImageAMD"; case Capability::ImageGatherBiasLodAMD: return "ImageGatherBiasLodAMD"; @@ -4200,6 +4228,8 @@ case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; case Capability::SubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; case Capability::TernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; + case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL"; + case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL"; case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; @@ -4805,10 +4835,14 @@ case Op::OpImageBoxFilterQCOM: return "OpImageBoxFilterQCOM"; case Op::OpImageBlockMatchSSDQCOM: return "OpImageBlockMatchSSDQCOM"; case Op::OpImageBlockMatchSADQCOM: return "OpImageBlockMatchSADQCOM"; + case Op::OpBitCastArrayQCOM: return "OpBitCastArrayQCOM"; case Op::OpImageBlockMatchWindowSSDQCOM: return "OpImageBlockMatchWindowSSDQCOM"; case Op::OpImageBlockMatchWindowSADQCOM: return "OpImageBlockMatchWindowSADQCOM"; case Op::OpImageBlockMatchGatherSSDQCOM: return "OpImageBlockMatchGatherSSDQCOM"; case Op::OpImageBlockMatchGatherSADQCOM: return "OpImageBlockMatchGatherSADQCOM"; + case Op::OpCompositeConstructCoopMatQCOM: return "OpCompositeConstructCoopMatQCOM"; + case Op::OpCompositeExtractCoopMatQCOM: return "OpCompositeExtractCoopMatQCOM"; + case Op::OpExtractSubArrayQCOM: return "OpExtractSubArrayQCOM"; case Op::OpGroupIAddNonUniformAMD: return "OpGroupIAddNonUniformAMD"; case Op::OpGroupFAddNonUniformAMD: return "OpGroupFAddNonUniformAMD"; case Op::OpGroupFMinNonUniformAMD: return "OpGroupFMinNonUniformAMD"; @@ -5194,6 +5228,13 @@ case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; case Op::OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; + case Op::OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; + case Op::OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; + case Op::OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; + case Op::OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; + case Op::OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case Op::OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case Op::OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; case Op::OpGroupIMulKHR: return "OpGroupIMulKHR"; case Op::OpGroupFMulKHR: return "OpGroupFMulKHR"; case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.json new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.json --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.json 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.json 2025-07-03 10:33:06.000000000 +0200 @@ -661,6 +661,7 @@ "HostAccessINTEL": 6188, "InitModeINTEL": 6190, "ImplementInRegisterMapINTEL": 6191, + "ConditionalINTEL": 6247, "CacheControlLoadINTEL": 6442, "CacheControlStoreINTEL": 6443 } @@ -1079,6 +1080,7 @@ "TextureBoxFilterQCOM": 4485, "TextureBlockMatchQCOM": 4486, "TileShadingQCOM": 4495, + "CooperativeMatrixConversionQCOM": 4496, "TextureBlockMatch2QCOM": 4498, "Float16ImageAMD": 5008, "ImageGatherBiasLodAMD": 5009, @@ -1254,6 +1256,8 @@ "Subgroup2DBlockTransposeINTEL": 6230, "SubgroupMatrixMultiplyAccumulateINTEL": 6236, "TernaryBitwiseFunctionINTEL": 6241, + "SpecConditionalINTEL": 6245, + "FunctionVariantsINTEL": 6246, "GroupUniformArithmeticKHR": 6400, "TensorFloat32RoundingINTEL": 6425, "MaskedGatherScatterINTEL": 6427, @@ -1989,10 +1993,14 @@ "OpImageBoxFilterQCOM": 4481, "OpImageBlockMatchSSDQCOM": 4482, "OpImageBlockMatchSADQCOM": 4483, + "OpBitCastArrayQCOM": 4497, "OpImageBlockMatchWindowSSDQCOM": 4500, "OpImageBlockMatchWindowSADQCOM": 4501, "OpImageBlockMatchGatherSSDQCOM": 4502, "OpImageBlockMatchGatherSADQCOM": 4503, + "OpCompositeConstructCoopMatQCOM": 4540, + "OpCompositeExtractCoopMatQCOM": 4541, + "OpExtractSubArrayQCOM": 4542, "OpGroupIAddNonUniformAMD": 5000, "OpGroupFAddNonUniformAMD": 5001, "OpGroupFMinNonUniformAMD": 5002, @@ -2383,6 +2391,13 @@ "OpSubgroup2DBlockStoreINTEL": 6235, "OpSubgroupMatrixMultiplyAccumulateINTEL": 6237, "OpBitwiseFunctionINTEL": 6242, + "OpConditionalExtensionINTEL": 6248, + "OpConditionalEntryPointINTEL": 6249, + "OpConditionalCapabilityINTEL": 6250, + "OpSpecConstantTargetINTEL": 6251, + "OpSpecConstantArchitectureINTEL": 6252, + "OpSpecConstantCapabilitiesINTEL": 6253, + "OpConditionalCopyObjectINTEL": 6254, "OpGroupIMulKHR": 6401, "OpGroupFMulKHR": 6402, "OpGroupBitwiseAndKHR": 6403, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.lua new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.lua --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.lua 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.lua 2025-07-03 10:33:06.000000000 +0200 @@ -629,6 +629,7 @@ HostAccessINTEL = 6188, InitModeINTEL = 6190, ImplementInRegisterMapINTEL = 6191, + ConditionalINTEL = 6247, CacheControlLoadINTEL = 6442, CacheControlStoreINTEL = 6443, Max = 0x7fffffff, @@ -1094,6 +1095,7 @@ TextureBoxFilterQCOM = 4485, TextureBlockMatchQCOM = 4486, TileShadingQCOM = 4495, + CooperativeMatrixConversionQCOM = 4496, TextureBlockMatch2QCOM = 4498, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, @@ -1269,6 +1271,8 @@ Subgroup2DBlockTransposeINTEL = 6230, SubgroupMatrixMultiplyAccumulateINTEL = 6236, TernaryBitwiseFunctionINTEL = 6241, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, GroupUniformArithmeticKHR = 6400, TensorFloat32RoundingINTEL = 6425, MaskedGatherScatterINTEL = 6427, @@ -1999,10 +2003,14 @@ OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2393,6 +2401,13 @@ OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.py new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.py --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spirv.py 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spirv.py 2025-07-03 10:33:06.000000000 +0200 @@ -611,6 +611,7 @@ 'HostAccessINTEL' : 6188, 'InitModeINTEL' : 6190, 'ImplementInRegisterMapINTEL' : 6191, + 'ConditionalINTEL' : 6247, 'CacheControlLoadINTEL' : 6442, 'CacheControlStoreINTEL' : 6443, }, @@ -1065,6 +1066,7 @@ 'TextureBoxFilterQCOM' : 4485, 'TextureBlockMatchQCOM' : 4486, 'TileShadingQCOM' : 4495, + 'CooperativeMatrixConversionQCOM' : 4496, 'TextureBlockMatch2QCOM' : 4498, 'Float16ImageAMD' : 5008, 'ImageGatherBiasLodAMD' : 5009, @@ -1240,6 +1242,8 @@ 'Subgroup2DBlockTransposeINTEL' : 6230, 'SubgroupMatrixMultiplyAccumulateINTEL' : 6236, 'TernaryBitwiseFunctionINTEL' : 6241, + 'SpecConditionalINTEL' : 6245, + 'FunctionVariantsINTEL' : 6246, 'GroupUniformArithmeticKHR' : 6400, 'TensorFloat32RoundingINTEL' : 6425, 'MaskedGatherScatterINTEL' : 6427, @@ -1942,10 +1946,14 @@ 'OpImageBoxFilterQCOM' : 4481, 'OpImageBlockMatchSSDQCOM' : 4482, 'OpImageBlockMatchSADQCOM' : 4483, + 'OpBitCastArrayQCOM' : 4497, 'OpImageBlockMatchWindowSSDQCOM' : 4500, 'OpImageBlockMatchWindowSADQCOM' : 4501, 'OpImageBlockMatchGatherSSDQCOM' : 4502, 'OpImageBlockMatchGatherSADQCOM' : 4503, + 'OpCompositeConstructCoopMatQCOM' : 4540, + 'OpCompositeExtractCoopMatQCOM' : 4541, + 'OpExtractSubArrayQCOM' : 4542, 'OpGroupIAddNonUniformAMD' : 5000, 'OpGroupFAddNonUniformAMD' : 5001, 'OpGroupFMinNonUniformAMD' : 5002, @@ -2336,6 +2344,13 @@ 'OpSubgroup2DBlockStoreINTEL' : 6235, 'OpSubgroupMatrixMultiplyAccumulateINTEL' : 6237, 'OpBitwiseFunctionINTEL' : 6242, + 'OpConditionalExtensionINTEL' : 6248, + 'OpConditionalEntryPointINTEL' : 6249, + 'OpConditionalCapabilityINTEL' : 6250, + 'OpSpecConstantTargetINTEL' : 6251, + 'OpSpecConstantArchitectureINTEL' : 6252, + 'OpSpecConstantCapabilitiesINTEL' : 6253, + 'OpConditionalCopyObjectINTEL' : 6254, 'OpGroupIMulKHR' : 6401, 'OpGroupFMulKHR' : 6402, 'OpGroupBitwiseAndKHR' : 6403, diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spv.d new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spv.d --- old/SPIRV-Headers-2a611a970fdbc41ac2e3e328802aed9985352dca/include/spirv/unified1/spv.d 2025-06-19 09:05:44.000000000 +0200 +++ new/SPIRV-Headers-c8ad050fcb29e42a2f57d9f59e97488f465c436d/include/spirv/unified1/spv.d 2025-07-03 10:33:06.000000000 +0200 @@ -657,6 +657,7 @@ HostAccessINTEL = 6188, InitModeINTEL = 6190, ImplementInRegisterMapINTEL = 6191, + ConditionalINTEL = 6247, CacheControlLoadINTEL = 6442, CacheControlStoreINTEL = 6443, Max = 0x7fffffff, @@ -1139,6 +1140,7 @@ TextureBoxFilterQCOM = 4485, TextureBlockMatchQCOM = 4486, TileShadingQCOM = 4495, + CooperativeMatrixConversionQCOM = 4496, TextureBlockMatch2QCOM = 4498, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, @@ -1314,6 +1316,8 @@ Subgroup2DBlockTransposeINTEL = 6230, SubgroupMatrixMultiplyAccumulateINTEL = 6236, TernaryBitwiseFunctionINTEL = 6241, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, GroupUniformArithmeticKHR = 6400, TensorFloat32RoundingINTEL = 6425, MaskedGatherScatterINTEL = 6427, @@ -2080,10 +2084,14 @@ OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2474,6 +2482,13 @@ OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403,
