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Package is "cpuid" Mon Mar 30 18:34:33 2026 rev:25 rq:1343709 version:20260220 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2025-06-30 13:06:37.850264786 +0200 +++ /work/SRC/openSUSE:Factory/.cpuid.new.1999/cpuid.changes 2026-03-30 18:38:42.417636102 +0200 @@ -1,0 +2,11 @@ +Mon Mar 30 14:22:28 UTC 2026 - Jan Engelhardt <[email protected]> + +- Update to release 20260220 + * Support for Panther Lake Cougar Cove/Darkmont, + Intel Core Ultra 300 series. + * APX EGPR descriptions + * Differentiate EPYC 4000 <-> Ryzen 7000 (both Raphael) + * Differentiate EPYC 4005 <-> Ryzen 9000 (Granite Ridge) + * Report EPYC 6th Gen (Venice) + +------------------------------------------------------------------- Old: ---- cpuid-20250513.src.tar.gz New: ---- cpuid-20260220.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.0xnagk/_old 2026-03-30 18:38:43.089664165 +0200 +++ /var/tmp/diff_new_pack.0xnagk/_new 2026-03-30 18:38:43.089664165 +0200 @@ -1,7 +1,7 @@ # # spec file for package cpuid # -# Copyright (c) 2025 SUSE LLC +# Copyright (c) 2026 SUSE LLC and contributors # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: cpuid -Version: 20250513 +Version: 20260220 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later ++++++ _scmsync.obsinfo ++++++ --- /var/tmp/diff_new_pack.0xnagk/_old 2026-03-30 18:38:43.125665668 +0200 +++ /var/tmp/diff_new_pack.0xnagk/_new 2026-03-30 18:38:43.129665835 +0200 @@ -1,5 +1,5 @@ -mtime: 1749152225 -commit: 263afc192bff0c81021f009aba564e0851bf3405a55ae62ea6d7807eadedacc6 +mtime: 1774880551 +commit: 38d36fc00de49cef2d4ae4559a59bf0a2e2287fd90ad1e226cf58194903baae8 url: https://src.opensuse.org/jengelh/cpuid revision: master ++++++ build.specials.obscpio ++++++ ++++++ build.specials.obscpio ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/.gitignore new/.gitignore --- old/.gitignore 1970-01-01 01:00:00.000000000 +0100 +++ new/.gitignore 2026-03-30 16:22:42.000000000 +0200 @@ -0,0 +1 @@ +.osc ++++++ cpuid-20250513.src.tar.gz -> cpuid-20260220.src.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/ChangeLog new/cpuid-20260220/ChangeLog --- old/cpuid-20250513/ChangeLog 2025-05-13 13:20:58.000000000 +0200 +++ new/cpuid-20260220/ChangeLog 2026-02-20 14:43:56.000000000 +0100 @@ -1,3 +1,149 @@ +Fri Feb 20 2026 Todd Allen <[email protected]> + * Made new release. + +Fri Feb 20 2026 Todd Allen <[email protected]> + * cpuid.protospec: Renamed cpuid.proto.spec to be more friendly to + rpmbuild -tb. + +Thu Feb 19 2026 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for (0,6),(12,12) Intel Core Ultra 3xx. + * cpuid.man: Added Intel docs 869992 & 872188. + * cpuid.c: Expanded synth decoding for (0,6),(6,12) to include D-1800. + * cpuid.man: Added Intel doc 714069. + +Wed Feb 18 2026 Todd Allen <[email protected]> + * cpuid.c: In synth decoding for (10,15),(6,0), differentiate EPYC 4000 + from Ryzen 7000 (both Raphael). + * cpuid.c: In synth decoding for (11,15),(4,0-7), differentiate + EPYC 4005 (Grado) from Ryzen 9000 (Granite Ridge). + +Wed Feb 18 2026 Todd Allen <[email protected]> + * cpuid.c: Added hypervisor+6/eax (Microsoft) use VMFUNC for alias map + switch. + +Wed Feb 18 2026 Todd Allen <[email protected]> + * cpuid.c: Added d/0/eax APX EGPR description. The bit isn't documented, + but I infer its existence from the present of sub-leaf 19 with + "APX EGPR" state. + * cpuid.c: Added support for walking sub-leaves of 0x29, in case any + additional sub-leafs are defined. + * cpuid.c: Added 0x29/0/ebx NCI, NDD, NF support. + +Tue Feb 17 2026 Todd Allen <[email protected]> + * cpuid.c: Added uarch synth for (0,6),(12,12) (Panther Lake): + Cougar Cove+Darkmont. + * cpuid.c: Added uarch synth for (0,6),(13,5) (Wildcat Lake): + Cougar Cove+Darkmont. + * cpuid.c: Changed uarch synth for (0,6),(11,12) process to TSMC N3B, + like other Lion Cove/Skymont CPUs. + +Tue Feb 17 2026 Todd Allen <[email protected]> + * cpuid.c: Updated (0,6),(10,13),1 stepping to include L0, from ILPMDF*. + * cpuid.c: Added (0,6),(10,14),1 B0/B1 steppings, from ILPMDF*. + +Mon Feb 16 2026 Todd Allen <[email protected]> + * cpuid.c: Added 7/1/ebx SEC-TEE-ATTESTATION (which is not described). + * cpuid.c: Narrowed 0x28/1/eax length of capacity bit mask field. + +Sun Feb 15 2026 Todd Allen <[email protected]> + * cpuid.c: In do_real, moved loop intended to iterate over 0x80000026 + sub-leaves out of the block iterating over 0x0+ leaves, and into + the block iterating over 0x80000000+ leaves (bugfix). + * cpuid.c: In decode_mp_synth & print_apic_synth, for AMD/HYGON CPU's, + use the 0x80000026 topology information, if present. It mirrors the + logic for Intel's 0x1f leaf, but with a different set of topological + layers. Also, v2TopoToCotopo is split into intel vs. amd variants. + * cpuid.c: Change uarch decoding for (11,15),(8,*) to Zen 6, from + LX* patch. + +Sun Feb 15 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0x8000000a/ecx x2AVIC_EXT field. Eliminated duplicate + headers for each 0x8000000a register. + * cpuid.c: Added 0x80000021/eax PerfEvtSel2 MSR PreciseRetire support. + * cpuid.c: Renamed 0x80000021/eax WRMSR to FS/GS base is not serializing. + * cpuid.c: Renamed 0x80000021/eax FP512 is downgraded to FP256. + * cpuid.c: Widened 0x80000021/ebx microcode patch size field to 16 bits. + * cpuid.c: Added 0x80000025/ebx number of RMP segments reduced. + +Sun Feb 15 2026 Todd Allen <[email protected]> + * cpuid.c: Added 0xa/edx TMA slots/cycle. + +Wed Sep 17 2025 Todd Allen <[email protected]> + * cpuid.c: Updated synth decoding for (11,15),(5,0) Venice to report + EPYC (6th Gen). + +Tue Sep 16 2025 Todd Allen <[email protected]> + * cpuid.c: Changed synth stepping for (0,6),(12,6,2) Arrow Lake-S/HX to + just B0, based on 834774-011 spec update typo correction. + +Wed Aug 20 2025 Todd Allen <[email protected]> + * cpuid.c: Changed uarch decoding for (0,6),(11,5) Atom from Skymont + to Crestmont, per SSG*. Evidently, Arrow Lake-U (mobile) uses the + older cores. + +Wed Aug 20 2025 Todd Allen <[email protected]> + * cpuid.c: Added 0x8000001f/ebx not vulnerable to SNP cache coherency + flag, from LX*. + +Mon Aug 4 2025 Todd Allen <[email protected]> + * cpuid.c: Added preliminary synth & uarch decodings for + (3,15),(0,1) Nova Lake & (3,15),(0,3) Nova Lake-L. + +Sun Aug 3 2025 Todd Allen <[email protected]> + * cpuid.c: Generalized (0,6),(12,6) synth decoding to include + Arrow Lake-HX. + +Sun Jul 13 2025 Todd Allen <[email protected]> + * cpuid.c: Correct fallback for (0,6),(3,7),9 for when the brand wasn't + understood, to mention stepping D1 as well as D0. + +Wed Jul 9 2025 Todd Allen <[email protected]> + * cpuid.c: Added AMD TSA mitigation bits from LX* (not yet documented): + 0x80000021/eax bit 5: VERW memory form mitigates TSA, + 0x80000021/ecx bit 1: not vulnerable to TSA-SQ, + 0x80000021/ecx bit 2: not vulnerable to TSA-L1, + * cpuid.c: Added 0x23/0/ebx: RDPMC_USR_DISABLE supported. + * cpuid.c: For 0x23/4/ebx, corrected bit offsets for XER support to + match updated Intel docs, added XER R16-R31 support, and renamed + existing fields to be more descriptive. + +Thu Jul 3 2025 Todd Allen <[email protected]> + * cpuid.c: Renamed 7/0/edx field "fast short REP MOVSB" to match updated + Intel docs. + * cpuid.c: Added 7/1/edx SLSM: IA32_INTEGRITY_STATUS MSR. + +Wed Jun 11 2025 Todd Allen <[email protected]> + * cpuid.c: Corrected synth decoding for (0,6),(11,5): Core Ultra 2xxU. + * cpuid.c: Corrected synth decoding for (0,6),(12,5): Core Ultra 2xxH. + +Tue May 27 2025 Todd Allen <[email protected]> + * cpuid.c: Based on info from Zhaoxin's Tony W Wang (LKML 2023-05-30): + * cpuid.c: print_c0000001_edx: Added bit fields for PARALLAX, TM3, RNG2, + PHE2, and RSA hardware support, although many evidently are present in + VIA Isaiah, too. + +Tue May 27 2025 Todd Allen <[email protected]> + * cpuid.c: print_80860001_ebx_ecx: Fixed leaf name typo. + * cpuid.c: Added 0x80860001/ecx Transmeta nominal core clock frequency. + * cpuid.c: print_80000001_eax_transmeta: Added type field. + * cpuid.c: print_80860001_eax: Added type field. + +Mon May 26 2025 Todd Allen <[email protected]> + * cpuid.c: Added synth decoding for AMD EPYC 7A53 (Trento), based on + info via instlatx64 from geekbench. + * cpuid.c: Renamed synth decoding for Zen5c Sorano (which came entirely + from early "leaks") to Turin-Dense. + +Sun May 18 2025 Todd Allen <[email protected]> + * cpuid.c: Based on Linux patch from AMD's Yazen Ghannem: + * cpuid.c: Changed uarch decoding for (11,15),(5,*) to Zen 6 (TSMC N2). + * cpuid.c: Added uarch decoding for (11,15),({9,10,12},*) to Zen 6 + (TSMC N2). No synth decoding for these yet. + +Thu May 15 2025 Todd Allen <[email protected]> + * cpuid.c: Update synth decoding for (11,15),(6,*) and (11,15),(7,*) + with Ryzen AI 300. + Tue May 13 2025 Todd Allen <[email protected]> * Made new release. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/FAMILY.NOTES new/cpuid-20260220/FAMILY.NOTES --- old/cpuid-20250513/FAMILY.NOTES 2025-05-12 14:05:43.000000000 +0200 +++ new/cpuid-20260220/FAMILY.NOTES 2026-02-18 15:17:20.000000000 +0100 @@ -28,46 +28,46 @@ Intel *Bridge, *well, *Lake, *Cove: - (Desktop) ========================Server (Xeon)======================== - Launch Marketing uArch Relationships Core Socket Gen uArch Platform Socket - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 2011 2000 Series Sandy Bridge new architecture LGA 1155 (same) LGA 2011: R - 2012 3000 Series Ivy Bridge shrink of Sandy Bridge (22nm) LGA 1155 (same) LGA 2011: R - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 2013 4000 Series Haswell new architecture LGA 1150 (same) Grantley LGA 2011-v3: R3 - 2014 5000 Series Broadwell shrink of Haswell (14nm) LGA 1150 (same) Grantley LGA 2011-v3: R3 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 2015 6000 Series Skylake new architecture LGA 1151/2066 1st (same) Purley LGA 3647-0: P - 2019 Cascade Lake optim of Skylake, DL Boost, spectre/meltdown LGA 2066 2nd (same) Purley LGA 3647-0: P - 2020 Cooper Lake optim of Cascade Lake, bfloat16, more cores 3rd (same) Whitley LGA 4189: P+ + (Desktop) =======================Server (Xeon)======================= + Launch Marketing uArch Relationships Core Socket Gen uArch Platform Socket + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2011 2000 Series Sandy Bridge new architecture LGA 1155 (same) LGA 2011: R + 2012 3000 Series Ivy Bridge shrink of Sandy Bridge (22nm) LGA 1155 (same) LGA 2011: R + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2013 4000 Series Haswell new architecture LGA 1150 (same) Grantley LGA 2011-v3: R3 + 2014 5000 Series Broadwell shrink of Haswell (14nm) LGA 1150 (same) Grantley LGA 2011-v3: R3 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2015 6000 Series Skylake new architecture LGA 1151/2066 1st (same) Purley LGA 3647-0: P + 2019 Cascade Lake optim of Skylake, DL Boost, spectre/meltdown LGA 2066 2nd (same) Purley LGA 3647-0: P + 2020 Cooper Lake optim of Cascade Lake, bfloat16, more cores 3rd (same) Whitley LGA 4189: P+ 2016 7000 Series Kaby Lake optim of Skylake, higher clock (14nm+) LGA 1151/2066 2016 Kaby Lake R refresh of Kaby Lake named 8000 Series LGA 1151 2017 8000 Series Coffee Lake optim of Kaby Lake, 1.5x CPUs/die (14nm++) LGA 1151 - 2018 Whiskey Lake *optim of Kaby Lake, mobile (U) (14nm++) - 2018 Amber Lake *optim of Kaby Lake, extreme low power (Y) - 2018 Palm Cove shrink of Kaby Lake (10nm), AVX-512 (Cannon Lake) + 2018 Whiskey Lake *optim of Kaby Lake, mobile (U) (14nm++) + 2018 Amber Lake *optim of Kaby Lake, extreme low power (Y) + 2018 Palm Cove shrink of Kaby Lake (10nm), AVX-512 (Cannon Lake) 2017 9000 Series Coffee Lake refresh of Coffee Lake, spectre/meltdown LGA 1151 2019 10000 Series Comet Lake *optim of {Coffee, Whiskey} Lake (K,U) LGA 1200 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 2019 10000 Series Sunny Cove new architecture (Ice Lake) (10nm) 3rd (same) Whitley LGA 4189: P+ - 2020 11000 Series Willow Cove optim of Sunny Cove (Tiger Lake) (10nm) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2019 10000 Series Sunny Cove new architecture (Ice Lake) (10nm) 3rd (same) Whitley LGA 4189: P+ + 2020 11000 Series Willow Cove optim of Sunny Cove (Tiger Lake) (10nm) 2021 Cypress Cove backport of Willow Cove (Rocket Lake) (14nm) LGA 1200 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 2021 12000 Series Golden Cove new architecture (Alder Lake) (Intel 7) LGA 1700 4th Sapphire Rapids Eagle Stream LGA 4677 - 2022 13000 Series Raptor Cove modified Golden Cove (Raptor Lake) (Intel 7) LGA 1700 5th Emerald Rapids (H2'23) Eagle Stream LGA 4677 - 2023 14000 Series Raptor Cove refreshed Raptor Cove (Intel 7) - 2023 Core Ultra 100 Redwood Cove modified Raptor Cove (Meteor Lake) (Intel 4) <-?-> 6th Granite Rapids (2024) Birch Stream LGA 7529 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2021 12000 Series Golden Cove new architecture (Alder Lake) (Intel 7) LGA 1700 4th Sapphire Rapids Eagle Stream LGA 4677 + 2022 13000 Series Raptor Cove modified Golden Cove (Raptor Lake) (Intel 7) LGA 1700 5th Emerald Rapids Eagle Stream LGA 4677 + 2023 14000 Series Raptor Cove refreshed Raptor Cove (Intel 7) + 2023 Core Ultra 100 Redwood Cove modified Raptor Cove (Meteor Lake) (Intel 4) 6th Granite Rapids Birch Stream LGA 7529 + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2024 Core Ultra 200 Lion Cove new architecture (Arrow Lake (TSMC N3) desktop) LGA 1851 2024 " " " (Lunar Lake (TSMC N3B) AI/low power) BGA 2833 - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - ? Raptor Cove (Bartlett Lake?) (Q2'25?) LGA 1700? - ? Core Ultra 300? Lion Cove refresh of Lion Cove (Arrow Lake? (Intel 20A)) (2025) LGA 1851? - ? Cougar Cove? (Panther Lake (Intel 18A?)) (mobile-only?) (2025) LGA 1851? - ? Cougar Cove? (Wildcat Lake (Intel 18A?)) - ? - Panther Cove? <-?-> 7th Diamond Rapids (2025) Mountain Stream LGA 9324? - ? Core Ultra 400? Coyote Cove? (Nova Lake? (Intel 18A?)) (2026) - --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2026 Core Ultra 300 Cougar Cove modified Lion Cove (Panther Lake (Intel 18A) mobile) n/a + 2026 " " " (Wildcat Lake (Intel 18A) mobile) n/a + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + ? Core Ultra 300? Lion Cove refresh of Lion Cove (Arrow Lake? (Intel 20A)) (2026) LGA 1851? + ? Raptor Cove (Bartlett Lake?) (2026?) LGA 1700? + ? - Panther Cove? <-?-> 7th Diamond Rapids (2026) Oak Stream LGA 9324? + ? Core Ultra 400? Coyote Cove? (Nova Lake? (Intel 18A?)) (2H 2026?) + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * = I'm not treating this as a distinct uarch, but just as a core within its parent uarch, Kaby Lake @@ -89,21 +89,24 @@ Hybrids: - Launch Combined P-cores E-cores - ---------------------------------------------------------------------------- - 2020 Lakefield 1x Sunny Cove + 4x Tremont (more of a prototype) - ---------------------------------------------------------------------------- - 2021 Alder Lake {2,6,8}x Golden Cove + {0,8}x Gracemont - 2022 Raptor Lake 8x Raptor Cove + 16x Gracemont - ---------------------------------------------------------------------------- - 2023 Meteor Lake {2,4,6}x Redwood Cove + {4,8}x Crestmont - ---------------------------------------------------------------------------- - 2024 Arrow Lake {6,8}x Lion Cove + {8,12,16}x Skymont (desktop) - 2024 Lunar Lake 4x Lion Cove + 4x Skymont (AI/low power: niche, one-off) - ---------------------------------------------------------------------------- - ? Panther Lake Cougar Cove? + Darkmont? (old speculation is Darkmont, news articles say Skymont, LX* says Crestmont(!)) - ? Nova Lake Coyote Cove? + Arctic Wolf? - ---------------------------------------------------------------------------- + Launch Combined P-cores E-cores + ----------------------------------------------------------------------------- + 2020 Lakefield 1x Sunny Cove + 4x Tremont (more of a prototype) + ----------------------------------------------------------------------------- + 2021 Alder Lake {2,6,8}x Golden Cove + {0,8}x Gracemont + 2022 Raptor Lake 8x Raptor Cove + 16x Gracemont + ----------------------------------------------------------------------------- + 2023 Meteor Lake {2,4,6}x Redwood Cove + {4,8}x Crestmont + ----------------------------------------------------------------------------- + 2024 Arrow Lake {6,8}x Lion Cove + {8,12,16}x Skymont (desktop) + 2024 Lunar Lake 4x Lion Cove + 4x Skymont (AI/low power: niche, one-off) + ----------------------------------------------------------------------------- + 2026 Panther Lake 4x Cougar Cove + 12x Darkmont + 2026 Wildcat Lake 2x Cougar Cove + 4x Darkmont + ----------------------------------------------------------------------------- + ? 2026? Nova Lake Coyote Cove? + Arctic Wolf? + ? 2027? Razer Lake? Griffin Cove? + Golden Eagle? + ----------------------------------------------------------------------------- Intel Atom architectures: @@ -135,8 +138,12 @@ 2024 Skymont Arrow Lake Lunar Lake ----------------------------------------------------------------------------------------------------------------------------------------- - Darkmont Panther Lake? Clearwater Forest - ? Arctic Wolf Nova Lake? + 2026 Darkmont Panther Lake Clearwater Forest + Wildcat Lake + ----------------------------------------------------------------------------------------------------------------------------------------- + ? 2026? Arctic Wolf Nova Lake? + ----------------------------------------------------------------------------------------------------------------------------------------- + ? 2028? Titan Lake? ----------------------------------------------------------------------------------------------------------------------------------------- Server: @@ -212,56 +219,55 @@ Intel Phi (brand name) / MIC (architecture name): - (research) : Larrabee (derived from P54C) - Knights Ferry : 24 Aubrey Isle {K1OM}, derived from Larrabee cores - Knights Corner : 50 (Aubrey Isle-derived) {K1OM} cores - Knights Landing : 72 Airmont cores - Knights Hill : (canceled; would've shrunk Knights Landing to 10nm) - Knights Mill : 72 Airmont(?) cores + 2009 (research) : Larrabee (derived from P54C) (canceled) + 2010 Knights Ferry : 24 Aubrey Isle {K1OM}, derived from Larrabee cores + 2012 Knights Corner : 50 (Aubrey Isle-derived) {K1OM} cores + 2013 Knights Landing : 72 Airmont cores + 2017 Knights Mill : 72 Airmont(?) cores + 2017 Knights Hill : (canceled; would've shrunk Knights Landing to 10nm) Intel AI: - Spring Hill : 2x Sunny Cove (derived) cores + 12 ICE (Vision P6 DSP) + 2019 Spring Hill : 2x Sunny Cove (derived) cores + 12 ICE (Vision P6 DSP) ====================================================================================================================================== AMD K8-based Platforms (includes K10 & its derivatives): - Mobile Platform Athlon m-Athlon Sempron m-Sempron Turion - -------------------------------------------------------------------------------------------- - Initial (CG) NewCastle Clawhammer/Odessa Paris Dublin - Initial (D0) Winchester Oakville Palermo Sonora - Initial (E3) Venice Palermo Palermo - Initial (E4) San Diego - Initial (E5) Newark Lancaster/Richmond - Initial (E6) Venice Palermo Albany/Roma - Kite (F2) Orleans Manila Keene Taylor/Trinidad - Kite R (G1) Brisbane Sparta Sherman Tyler - Puma Lion Sable Lion - Yukon Huron/Brisbane Huron - Congo - Tigris/Danube Sargas/Regor Sargas Caspian/Champlain - Nile Geneva - -------------------------------------------------------------------------------------------- - -AMD Bobcat - Puma (2014): - - - Desktop Mobile Server Embedded - --------------------------------------------------------------------------------------------------------------------------------------- - Bobcat Ontario/Desna/Zacate Ontario/Zacate - --------------------------------------------------------------------------------------------------------------------------------------- - Bulldozer Zambezi Interlagos/Valencia/Zurich - Piledriver Trinity Trinity Trinity - (update) Richland Richland - Steamroller Kaveri Kaveri Berlin (canceled) Bald Eagle - (refresh) Godavari - Excavator Carrizo Carrizo Toronto Brown Falcon/Merlin Falcon - (+) Bristol Ridge/Stoney Ridge Bristol Ridge/Stoney Ridge Prairie Falcon - --------------------------------------------------------------------------------------------------------------------------------------- - Jaguar Kabini/(PS4)/(Xbox One) Kabini/Temash Kyoto Kabini NOTE: derived from Bobcat - Puma (2014) Beema/Mullins Steppe Eagle (SoC)/Crowned Eagle (CPU) - --------------------------------------------------------------------------------------------------------------------------------------- + Launch Mobile Platform Athlon m-Athlon Sempron m-Sempron Turion + --------------------------------------------------------------------------------------------------- + 2003 Initial (CG) NewCastle Clawhammer/Odessa Paris Dublin + 2004 Initial (D0) Winchester Oakville Palermo Sonora + 2005 Initial (E3) Venice Palermo Palermo + 2005 Initial (E4) San Diego + 2005 Initial (E5) Newark Lancaster/Richmond + 2005 Initial (E6) Venice Palermo Albany/Roma + 2006 Kite (F2) Orleans Manila Keene Taylor/Trinidad + 2007 Kite R (G1) Brisbane Sparta Sherman Tyler + 2008 Puma Lion Sable Lion + 2009 Yukon Huron/Brisbane Huron + 2009 Congo + 2009 Tigris/Danube Sargas/Regor Sargas Caspian/Champlain + 2010 Nile Geneva + 2011 Sabine (Fusion) Llano + --------------------------------------------------------------------------------------------------- + +AMD Bulldozer - Excavator (high power & cost) & Bobcat - Puma (low power & cost): + + Launch uArch Desktop Mobile Server Embedded + ---------------------------------------------------------------------------------------------------------------------------------------------- + 2011 Bobcat Ontario/Desna/Zacate Ontario/Zacate + 2013 Jaguar Kabini/(PS4)/(Xbox One) Kabini/Temash Kyoto Kabini + 2014 Puma Beema/Mullins Steppe Eagle (SoC)/Crowned Eagle (CPU) + ---------------------------------------------------------------------------------------------------------------------------------------------- + 2011 Bulldozer Zambezi Interlagos/Valencia/Zurich + 2012 Piledriver Trinity Trinity Trinity + (update) Richland Richland + 2014 Steamroller Kaveri Kaveri Berlin (canceled) Bald Eagle + 2015 (refresh) Godavari + 2015 Excavator Carrizo Carrizo Toronto Brown Falcon/Merlin Falcon + 2016 (+) Bristol Ridge/Stoney Ridge Bristol Ridge/Stoney Ridge Prairie Falcon + ---------------------------------------------------------------------------------------------------------------------------------------------- A-Series = APU (Desktop/Mobile) E-Series = cheaper version of A-Series @@ -269,49 +275,52 @@ AMD Zen and later: - Desktop Desktop Enthusiast Mobile Server Embedded - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - Zen (14nm) 1000: Summit Ridge 1000: Whitehaven 2000: Raven Ridge 1st Gen: 7cp1: Naples V1000: Great Horned Owl/R1000: Banded Kestrel - 1st Gen: 3cp1: Snowy Owl - 1000: Dali 1000: Dali - Zen+ (12nm) 2000: Pinnacle Ridge 2000: Colfax - 3000: Picasso 3000: Picasso - Zen 2 (7nm) 3000: Castle Peak 2nd Gen: 7cp2: Rome==Starship V2000: Grey Hawk - (update) 3000: Matisse 4000: Renoir - 5000: Lucienne - 7000: Mendocino - Cardinal (PS5) Van Gogh (Steam Deck) - ProjectX (Xbox X) Mero (MagicLeap Demophon) - Zen 3 (7nm) 5000: Vermeer 5000: Chagall==Genesis Peak 5000: Cezanne/Barcelo 3rd Gen: 7cp3: Milan - 6000/7000: Rembrandt V3000: still Rembrandt? - Trento (Frontier super) - Badami (?) - Zen 4 (5nm) 7000: Raphael 7000: Storm Peak 7000/8000: Phoenix 4th Gen: 9cp4: Genoa{==Stones?}(standard) - 4th Gen: 4cp4: Raphael - 7000: Dragon Range - (MI300 super) - 8000: Hawk Point - Zen 4c (N5) 4th Gen: 97p4: Bergamo{==Stones-dense?}(cloud) - 4th Gen: 8cp4: Siena{==Stones-dense?}(edge) - Zen 5 (N4P) 9000: Granite Ridge AI 300: Strix Point 5th Gen: 9cp5: Turin{==Breithorn} - Zen 5c (N3) 5th Gen: 9cp5: Sorano{==Breithorn-dense}(cloud?) - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - ? 9000: Shimada Peak? 9000: Fire Range 5th Gen: 4cp5: Grado? - ? 9000: Krackan Point(edge)? - ? AI ???: Strix Halo==Sarlak? - ? AI ???: Bald Eagle Point? - ? ????: Gorgon Point? AI ???: Gorgon Point? - ? Escher? - ? Zen 6 10000: Medusa (2026)? 6th Gen: Venice{==Weisshorn} - Zen 6c 6th Gen: Monarch - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + Launch uArch Desktop Desktop Enthusiast Mobile Server Embedded + ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 2017 Zen (14nm) 1000: Summit Ridge 1000: Whitehaven 2000: Raven Ridge 1st Gen: 7cp1: Naples R1000: Banded Kestrel + 1st Gen: 3cp1: Snowy Owl V1000: Great Horned Owl + 1000: Dali 1000: Dali + 2018 Zen+ (12nm) 2000: Pinnacle Ridge 2000: Colfax + 3000: Picasso 3000: Picasso + 2019 Zen 2 (7nm) 3000: Castle Peak 2nd Gen: 7cp2: Rome==Starship V2000: Grey Hawk + (update) 3000: Matisse 4000: Renoir + 5000: Lucienne + 7000: Mendocino + Cardinal (PS5) Van Gogh (Steam Deck) + ProjectX (Xbox X) Mero (MagicLeap Demophon) + 2020 Zen 3 (7nm) 5000: Vermeer 5000: Chagall==Genesis Peak 5000: Cezanne/Barcelo 3rd Gen: 7cp3: Milan + 6000/7000: Rembrandt V3000: still Rembrandt? + 3rd Gen: 7A53: Trento (Frontier super) + Badami (?) + 2022 Zen 4 (5nm) 7000: Raphael 7000: Storm Peak 7000/8000: Phoenix 4th Gen: 9cp4: Genoa{==Stones?}(standard) + 4th Gen: 4cp4: Raphael + 7000: Dragon Range + (MI300 super) + 8000: Hawk Point + 2023 Zen 4c (N5) 4th Gen: 97p4: Bergamo{==Stones-dense?}(cloud) + 4th Gen: 8cp4: Siena{==Stones-dense?}(edge) + 2024 Zen 5 (N4P) 9000: Granite Ridge 9000: Shimada Peak AI 300: Krackan Point 5th Gen: 9cp5: Turin{==Breithorn} + 5th Gen: 4cp5: Grado + AI 300: Strix Point + AI 300: Strix Halo{==Sarlak} + 2024 Zen 5c (N3) 5th Gen: 9cp5: Turin-Dense{==Breithorn-dense} + ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + ? 200: Hawk Point Refresh + ? 9000: Fire Range + ? Annapurna Embedded + ? AI ???: Bald Eagle Point? + ? ????: Gorgon Point? AI ???: Gorgon Point? + ? Escher? + ? 2027? Zen 6 10000: Medusa (2026)? 6th Gen: Venice{==Weisshorn} + Zen 6c 6th Gen: Monarch + ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Ryzen = Desktop/Mobile Ryzen Threadripper = Desktop Enthusiast (64-core) EPYC = Server Ryzen numbering, before circa 2022: - single digit: + single digit: 3 = mainstream (4-core) 5 = high performance (6-core) 7 = enthusiast (8-core) @@ -354,7 +363,7 @@ 2 = Zen 2 3 = Zen 3 4 = Zen 4 - 5 = Zen 5 + 5 = Zen 5 4th digit: segment 0 = lower 5 = higher @@ -393,6 +402,7 @@ EPYC numbering, generations 4-5: 1st digit: product series + 4 = entry-level server 9 = server (socket SP5) 2nd digit: core count (c): 0 = 8 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/Makefile new/cpuid-20260220/Makefile --- old/cpuid-20250513/Makefile 2025-05-13 13:10:50.000000000 +0200 +++ new/cpuid-20260220/Makefile 2026-02-20 14:38:05.000000000 +0100 @@ -9,7 +9,7 @@ INSTALL_STRIP=-s PACKAGE=cpuid -VERSION=20250513 +VERSION=20260220 RELEASE=1 PROG=$(PACKAGE) @@ -32,12 +32,12 @@ SRCS=cpuid.c OTHER_SRCS=Makefile $(PROG).man cpuinfo2cpuid \ - $(PACKAGE).proto.spec $(PACKAGE).spec \ + $(PACKAGE).protospec $(PACKAGE).spec \ ChangeLog FUTURE FAMILY.NOTES LICENSE OTHER_BINS=$(PROG).man cpuinfo2cpuid.man REL_DIR=../$(shell date +%Y-%m-%d) -WEB_DIR=/toad2/apps.mine/www/www/$(PROG) +WEB_DIR=/toad2/apps.mine/www/local/$(PROG) BUILDROOT=$(DESTDIR) @@ -98,7 +98,7 @@ # Release rules -$(PACKAGE).spec: $(PACKAGE).proto.spec +$(PACKAGE).spec: $(PACKAGE).protospec @(echo "%define version $(VERSION)"; \ echo "%define release $(RELEASE)"; \ cat $<) > $@ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/cpuid.c new/cpuid-20260220/cpuid.c --- old/cpuid-20250513/cpuid.c 2025-05-13 13:10:09.000000000 +0200 +++ new/cpuid-20260220/cpuid.c 2026-02-19 15:38:09.000000000 +0100 @@ -1,7 +1,7 @@ /* ** cpuid dumps CPUID information for each CPU. ** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017,2018, -** 2020,2021,2022,2023,2024,2025 by Todd Allen. +** 2020,2021,2022,2023,2024,2025,2026 by Todd Allen. ** ** This program is free software; you can redistribute it and/or ** modify it under the terms of the GNU General Public License @@ -406,21 +406,21 @@ // This enum combines the topological layers from both Intel & AMD. enum Cotopo { - Smt, - Core, - Cu, - Module, - Tile, - Die, - DieGrp, - Pkg, + Smt, // SMT thread: symmetric multi-thread (aka Logical Processor) + Core, // Intel Core or AMD CMT thread (aka Core: they insist) + Cu, // AMD Compute unit (aka Complex) + Module, // Intel Module or AMD CCD: Core Complex DIE + Tile, // Intel Tile + Die, // Intel Die or AMD Socket + DieGrp, // Intel Die Group + Pkg, // implied catch-all, not explicitly described NumCotopos, Invalid = NumCotopos, }; -#define V2_TOPO_NUM 7 +#define INTEL_V2_TOPO_NUM 7 -static unsigned int v2TopoToCotopo[V2_TOPO_NUM] +static unsigned int intelV2TopoToCotopo[INTEL_V2_TOPO_NUM] = { /* invalid (0) => */ Invalid, /* thread (1) => */ Smt, /* core (2) => */ Core, @@ -429,12 +429,22 @@ /* die (5) => */ Die, /* die group (6) => */ DieGrp }; +#define AMD_V2_TOPO_NUM 5 + +static unsigned int amdV2TopoToCotopo[AMD_V2_TOPO_NUM] + = { /* invalid (0) => */ Invalid, + /* core (1) => */ Core, + /* complex (2) => */ Cu, + /* die (3) => */ Module, // aka CCD "core complex die" + /* socket (4) => */ Die }; + typedef struct { vendor_t vendor; boolean saw_4; boolean saw_b; boolean saw_1f; boolean saw_8000001e; + boolean saw_80000026; unsigned int val_0_eax; unsigned int val_1_eax; unsigned int val_1_ebx; @@ -446,9 +456,9 @@ unsigned int val_b_ebx[2]; unsigned int val_b_edx; unsigned int val_1a_0_eax; - unsigned int val_1f_eax[V2_TOPO_NUM]; - unsigned int val_1f_ebx[V2_TOPO_NUM]; - unsigned int val_1f_ecx[V2_TOPO_NUM]; + unsigned int val_1f_eax[INTEL_V2_TOPO_NUM]; + unsigned int val_1f_ebx[INTEL_V2_TOPO_NUM]; + unsigned int val_1f_ecx[INTEL_V2_TOPO_NUM]; unsigned int val_1f_edx; unsigned int val_80000001_eax; unsigned int val_80000001_ebx; @@ -457,6 +467,10 @@ unsigned int val_80000008_ecx; unsigned int val_8000001e_eax; unsigned int val_8000001e_ebx; + unsigned int val_80000026_eax[AMD_V2_TOPO_NUM]; + unsigned int val_80000026_ebx[AMD_V2_TOPO_NUM]; + unsigned int val_80000026_ecx[AMD_V2_TOPO_NUM]; + unsigned int val_80000026_edx; unsigned int transmeta_proc_rev; char brand[48+1]; char transmeta_info[64+1]; @@ -571,7 +585,7 @@ #define NIL_STASH { VENDOR_UNKNOWN, \ FALSE, FALSE, FALSE, FALSE, \ - 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ { 0, 0 }, \ { 0, 0 }, \ 0, \ @@ -580,14 +594,19 @@ { 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0 }, \ 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, \ + { 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0 }, \ + { 0, 0, 0, 0, 0 }, \ + 0, \ + 0, \ "", "", "", "", \ HYPERVISOR_UNKNOWN, \ { NULL, { 0, 0, 0, 0, 0, 0, 0, 0 } }, \ { FALSE, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ - FALSE, FALSE, FALSE, FALSE }, \ + FALSE, FALSE, FALSE, FALSE }, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ @@ -2295,15 +2314,15 @@ FM ( 0, 6, 10,13, *u = "Granite Rapids", *ciu = TRUE, *f = "Redwood Cove, shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,14, *u = "Granite Rapids", *ciu = TRUE, *f = "Redwood Cove, shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX* FM ( 0, 6, 10,15, *u = "Crestmont", *p = "Intel 3"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA - FMQ ( 0, 6, 11, 5, Ha, *u = "Skymont", *p = "TSMC N3B"); // MSR_CPUID_table* + FMQ ( 0, 6, 11, 5, Ha, *u = "Crestmont", *p = "TSMC N3B"); // MSR_CPUID_table*, SSG* FMQ ( 0, 6, 11, 5, Hc, *u = "Lion Cove", *p = "TSMC N3B"); // MSR_CPUID_table* FM ( 0, 6, 11, 6, *u = "Crestmont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; SSG* specifies Crestmont FMQ ( 0, 6, 11, 7, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF* FMQ ( 0, 6, 11, 7, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF* FMQ ( 0, 6, 11,10, Ha, *u = "Gracemont", *p = "Intel 7"); // DPTF*; Coreboot* FMQ ( 0, 6, 11,10, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot* - FMQ ( 0, 6, 11,12, Ha, *u = "Skymont", *p = "Intel 18A"); - FMQ ( 0, 6, 11,12, Hc, *u = "Lion Cove", *p = "Intel 18A"); + FMQ ( 0, 6, 11,12, Ha, *u = "Skymont", *p = "TSMC N3B"); + FMQ ( 0, 6, 11,12, Hc, *u = "Lion Cove", *p = "TSMC N3B"); FMQ ( 0, 6, 11,13, Ha, *u = "Skymont", *p = "TSMC N3B"); FMQ ( 0, 6, 11,13, Hc, *u = "Lion Cove", *p = "TSMC N3B"); FMQ ( 0, 6, 11,14, Ha, *u = "Gracemont", *p = "Intel 7"); @@ -2314,12 +2333,11 @@ FMQ ( 0, 6, 12, 5, Hc, *u = "Lion Cove", *p = "TSMC N3"); FMQ ( 0, 6, 12, 6, Ha, *u = "Skymont", *p = "TSMC N3"); FMQ ( 0, 6, 12, 6, Hc, *u = "Lion Cove", *p = "TSMC N3"); - // Whatever uarch namess are correct for (0,6),(12,12) Panther Lake (expect Intel 18A) - // P-core: News articles suggest Cougar Cove. - // E-core: Old speculation is Darkmont, news articles say Skymont, LX* says Crestmont(!) + FMQ ( 0, 6, 12,12, Ha, *u = "Cougar Cove", *p = "Intel 18A"); + FMQ ( 0, 6, 12,12, Hc, *u = "Darkmont", *p = "Intel 18A"); FM ( 0, 6, 12,15, *u = "Emerald Rapids", *ciu = TRUE, *f = "Raptor Cove, optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX* - // Whatever uarch names are correct for (0,6),(13,5) Wildcat Lake (expect Intel 18A) - // Speculation is that it's similar to Panther Lake, so Cougar Cove + Darkmont. + FMQ ( 0, 6, 13, 5, Ha, *u = "Cougar Cove", *p = "Intel 18A"); + FMQ ( 0, 6, 13, 5, Hc, *u = "Darkmont", *p = "Intel 18A"); FM ( 0, 6, 13, 7, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // LX* FM ( 0, 6, 13,13, *u = "Darkmont", *p = "Intel 18A"); // MSR_CPUID_table*; LX* F ( 0, 7, *u = "Itanium"); @@ -2338,6 +2356,10 @@ F ( 1,15, *u = "Itanium2"); F ( 2, 0, *u = "Itanium2", *p = "90nm"); F ( 2, 1, *u = "Itanium2"); + FMQ ( 3,15, 0, 1, Ha, *u = "Arctic Wolf", *p = "Intel 18A"); // LX*, might change to TSMC 2N + FMQ ( 3,15, 0, 1, Hc, *u = "Coyote Cove", *p = "Intel 18A"); // LX*, might change to TSMC 2N + FMQ ( 3,15, 0, 3, Ha, *u = "Arctic Wolf", *p = "Intel 18A"); // LX*, might change to TSMC 2N + FMQ ( 3,15, 0, 3, Hc, *u = "Coyote Cove", *p = "Intel 18A"); // LX*, might change to TSMC 2N FM ( 4,15, 0, 0, *u = "Panther Cove", *p = "Intel 18A"); // MSR_CPUID_table* (-054, quickly retracted in -055), LX* FM ( 4,15, 0, 1, *u = "Panther Cove", *p = "Intel 18A"); // MSR_CPUID_table*, LX* DEFAULT ((void)NULL); @@ -2470,12 +2492,23 @@ FMm (11,15, 3, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 4, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LX* & engr sample via instlatx64 from einsteinathome.org (13142934) FMm (11,15, 4, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 5, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 5, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 5, 0, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian & Yazen Ghannam + FMm (11,15, 5, 8, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian & Yazen Ghannam FMm (11,15, 6, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but engr sample via instlatx64 from @kepler_l2 FMm (11,15, 6, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 7, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LX* & engr sample via instlatx64 from @kepler_l2 FMm (11,15, 7, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 8, 0, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but linux patch from AMD's Borislav Petkov + FMm (11,15, 8, 8, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but linux patch from AMD's Borislav Petkov + FMm (11,15, 9, 0, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Yazen Ghannam + FMm (11,15, 9, 8, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Yazen Ghannam + FMm (11,15, 10, 0, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Yazen Ghannam + FMm (11,15, 10, 8, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Yazen Ghannam + FMm (11,15, 12, 0, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Yazen Ghannam + FMm (11,15, 12, 8, *u = "Zen 6", *p = "TSMC N2"); // undocumented, but LLVM patch from AMD's Yazen Ghannam + FMm (11,15, 13, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Umesh Kalvakuntla + FMm (11,15, 14, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Umesh Kalvakuntla + FMm (11,15, 14, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Umesh Kalvakuntla DEFAULT ((void)NULL); } @@ -3266,7 +3299,7 @@ FMSQ( 0, 6, 3, 7, 9, da, "Intel Atom E3800 (Bay Trail-I D0)"); FMSQ( 0, 6, 3, 7, 9, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M/D D0/D1)"); // only MRG* 2018-03-06 FMSQ( 0, 6, 3, 7, 9, dP, "Intel Pentium J1800 / J1900 (Bay Trail-M/D D0/D1)"); // only MRG* 2018-03-06 - FMS ( 0, 6, 3, 7, 9, "Intel Atom (unknown type) (Bay Trail D0)"); + FMS ( 0, 6, 3, 7, 9, "Intel Atom (unknown type) (Bay Trail D0/D1)"); FM ( 0, 6, 3, 7, "Intel Atom (unknown type) (Bay Trail-M / Bay Trail-T / Bay Trail-I)"); // Intel docs (326766, 326770, 326774, 329376). // How to differentiate Gladden from Ivy Bridge here? @@ -3459,10 +3492,10 @@ // Intel docs (335901) omit almost all details for the Core versions of // (0,6),(5,5). // Other Intel docs provide some: - // 336065: Xeon Scalable steppings 2 & 4, - // 338848: Xeon Scalable (2nd gen) stepping 7 - // 338854: Xeon D-2000 stepping 2 - // 634897: Xeon Scalable (3rd gen) steppings 10 & 11 + // 336065/613537: Xeon Scalable steppings 2 & 4 + // 338848: Xeon Scalable (2nd gen) stepping 7 + // 338854: Xeon D-2000 stepping 2 + // 634897: Xeon Scalable (3rd gen) steppings 10 & 11 // MRG* 2019-11-13 mentions stepping 3, but doesn't mention stepping name. // geekbench.com has an "Intel Xeon Gold 6230" example of a stepping 5, but // no stepping name. @@ -3565,11 +3598,12 @@ FMQ ( 0, 6, 6,10, sS, "Intel Xeon Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP)"); FM ( 0, 6, 6,10, "Intel Xeon (unknown type) (Ice Lake-SP)"); // Intel docs (714071) claim stepping 1 is U1/U2. + // Intel doc 714069 adds D-1800. // ILPMDF* 20221108 claims ICL-D (Ice Lake Xeon D), and says B0 stepping. // DPTF* claims this is Meteor Lake S - FMSQ( 0, 6, 6,12, 1, sX, "Intel Xeon D-1700/2700 (Ice Lake-D U1/U2)"); + FMSQ( 0, 6, 6,12, 1, sX, "Intel Xeon D-1700/1800/2700 (Ice Lake-D U1/U2)"); FMS ( 0, 6, 6,12, 1, "Intel (unknown type) (Ice Lake-D U1/U2)"); - FMQ ( 0, 6, 6,12, sX, "Intel Xeon D-1700/2700 (Ice Lake-D)"); + FMQ ( 0, 6, 6,12, sX, "Intel Xeon D-1700/1800/2700 (Ice Lake-D)"); FM ( 0, 6, 6,12, "Intel (unknown type) (Ice Lake-D)"); // No spec update; only MRG* 2018-03-06, 2019-08-31. It is some sort of Atom, // but no idea which uarch or core. @@ -3882,13 +3916,16 @@ FM ( 0, 6, 10,11, "Intel (unknown type) (Meteor Lake-N)"); // DPTF* FM ( 0, 6, 10,12, "Intel (unknown type) (Meteor Lake-S)"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA // Intel doc 835486 + // SSG* mentions stepping 0, but no name. // ILPMDF* 20250512 names stepping 1 as B0/H0. - FMSQ( 0, 6, 10,13, 1, sX, "Intel Xeon 6 6x00 (Granite Rapids B0/H0)"); - FMS ( 0, 6, 10,13, 1, "Intel (unknown type) (Granite Rapids B0/H0)"); + FMSQ( 0, 6, 10,13, 1, sX, "Intel Xeon 6 6x00 (Granite Rapids B0/H0/L0)"); + FMS ( 0, 6, 10,13, 1, "Intel (unknown type) (Granite Rapids B0/H0/L0)"); FMQ ( 0, 6, 10,13, sX, "Intel Xeon 6 6x00 (Granite Rapids)"); FM ( 0, 6, 10,13, "Intel (unknown type) (Granite Rapids)"); // Intel doc 843306 // Mentions stepping 1, but with no name. + FMSQ( 0, 6, 10,14, 1, sX, "Intel Xeon 6 6x00P (Granite Rapids B0/B1)"); + FMS ( 0, 6, 10,14, 1, "Intel (unknown type) (Granite Rapids B0/B1)"); FMQ ( 0, 6, 10,14, sX, "Intel Xeon 6 6x00P (Granite Rapids)"); FM ( 0, 6, 10,14, "Intel (unknown type) (Granite Rapids)"); // Intel doc 820922 @@ -3899,9 +3936,9 @@ // Intel doc 834774 // 834774 names stepping 0 as A0. ILPMDF* 20250512 names it as A1. // Preferring 834774. - FMSQ( 0, 6, 11, 5, 0, dU, "Intel Core Ultra 2xxS (Arrow Lake-U A0)"); + FMSQ( 0, 6, 11, 5, 0, dU, "Intel Core Ultra 2xxU (Arrow Lake-U A0)"); FMS ( 0, 6, 11, 5, 0, "Intel (unknown type) (Arrow Lake-U A0)"); - FMQ ( 0, 6, 11, 5, dU, "Intel Core Ultra 2xxS (Arrow Lake-U)"); + FMQ ( 0, 6, 11, 5, dU, "Intel Core Ultra 2xxU (Arrow Lake-U)"); FM ( 0, 6, 11, 5, "Intel (unknown type) (Arrow Lake-U)"); // Grand Ridge: Atom P6900 name from: // https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01194.html @@ -3927,6 +3964,7 @@ // Intel doc 743844 provides steppings 2 & 3, with names! // ILPMDF* 20230214 contradicts it, saying 2=Q0, but it's prone to cut&paste // errors, so adhering to the official docs. + // SSG* mentions stepping 8, but no name. FMSQ( 0, 6, 11,10, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-H/U/P J0)"); FMSQ( 0, 6, 11,10, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-H/U/P J0)"); FMSQ( 0, 6, 11,10, 2, dc, "Intel Core i*-13000 (Raptor Lake-H/U/P J0)"); @@ -3966,6 +4004,9 @@ // Intel doc 740518 provides steppings 2 & 5, but without names // Intel doc 743844 provides steppings 2 & 5, with names: C0 & H0. // ILPMDF* 20231114 confirms steppings C0 & H0. + // https://browser.geekbench.com/v6/cpu/12794012 finds a CPU with stepping 6, + // but with brand Intel Core 3 201TE, which Intel claims is "Bartlett Lake". + // Perhaps Bartlett Lake is just a branding distinction? FMSQ( 0, 6, 11,15, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 2, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)"); @@ -3980,17 +4021,18 @@ FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/HX/P)"); // Intel doc 834774 // ILPMDF* 20250512 confirms stepping 2 as A1. - FMSQ( 0, 6, 12, 5, 2, dU, "Intel Core Ultra 2xxS (Arrow Lake-H A1)"); + FMSQ( 0, 6, 12, 5, 2, dU, "Intel Core Ultra 2xxH (Arrow Lake-H A1)"); FMS ( 0, 6, 12, 5, 2, "Intel (unknown type) (Arrow Lake-H A1)"); - FMQ ( 0, 6, 12, 5, dU, "Intel Core Ultra 2xxS (Arrow Lake-H)"); + FMQ ( 0, 6, 12, 5, dU, "Intel Core Ultra 2xxH (Arrow Lake-H)"); FM ( 0, 6, 12, 5, "Intel (unknown type) (Arrow Lake)"); // Intel doc 834774 - // ILPMDF* 20250512 confirms stepping 2 as B0 (doesn't mention A0). - FMSQ( 0, 6, 12, 6, 2, dU, "Intel Core Ultra 2xxS (Arrow Lake-S A0/B0)"); - FMS ( 0, 6, 12, 6, 2, "Intel (unknown type) (Arrow Lake-S A0/B0)"); - FMQ ( 0, 6, 12, 6, dU, "Intel Core Ultra 2xxS (Arrow Lake-S)"); - FM ( 0, 6, 12, 6, "Intel (unknown type) (Arrow Lake-S)"); - FM ( 0, 6, 12,12, "Intel (unknown type) (Panther Lake)"); // MSR_CPUID_table*, LX* + // ILPMDF* 20250512 confirms stepping 2 as B0. + FMSQ( 0, 6, 12, 6, 2, dU, "Intel Core Ultra 2xxS/HX (Arrow Lake-S/HX B0)"); + FMS ( 0, 6, 12, 6, 2, "Intel (unknown type) (Arrow Lake-S B0)"); + FMQ ( 0, 6, 12, 6, dU, "Intel Core Ultra 2xxS/HX (Arrow Lake-S/HX)"); + FM ( 0, 6, 12, 6, "Intel (unknown type) (Arrow Lake-S/HX)"); + // Intel docs 872118 & 869992 mention steppings 2 & 3, but with no names. + FM ( 0, 6, 12,12, "Intel Core Ultra 3xx (Panther Lake)"); // Intel docs (793902) provides stepping A1/R1. // ILPMDF* 20240312 provides stepping A0. FMSQ( 0, 6, 12,15, 1, sS, "Intel Xeon Scalable (5th Gen) Bronze/Silver/Gold/Platinum (Emerald Rapids A0)"); @@ -4185,6 +4227,12 @@ FMS ( 2, 1, 0, 0, 5, "Intel Itanium2 Processor 9700 (Kittson E0), 22nm"); FM ( 2, 1, 0, 0, "Intel Itanium2 (unknown model) (Poulson/Kittson)"); F ( 2, 1, "Intel Itanium2 (unknown model)"); + FMQ ( 3,15, 0, 1, Ha, "Intel (unknown type) E-core (Nova Lake)"); // LX* + FMQ ( 3,15, 0, 1, Hc, "Intel (unknown type) P-core (Nova Lake)"); // LX* + FM ( 3,15, 0, 1, "Intel (unknown type) (Nova Lake)"); // LX* + FMQ ( 3,15, 0, 3, Ha, "Intel (unknown type) E-core (Nova Lake-L)"); // LX* + FMQ ( 3,15, 0, 3, Hc, "Intel (unknown type) P-core (Nova Lake-L)"); // LX* + FM ( 3,15, 0, 3, "Intel (unknown type) (Nova Lake-L)"); // LX* FM ( 4,15, 0, 0, "Intel (unknown type) (Diamond Rapids)"); // MSR_CPUID_table* (-054, quickly retracted in -055), LX* FM ( 4,15, 0, 1, "Intel (unknown type) (Diamond Rapids)"); // MSR_CPUID_table*, LX* DEFAULT ("unknown"); @@ -4944,37 +4992,47 @@ // The AMD Ryzen Threadripper Pro CPU (Family 19h Model 18h and ... FMm (10,15, 1, 8, "AMD Ryzen Threadripper 7000 (Storm Peak %c%u)"); // undocumented, but samples from instlatx64 FMm (10,15, 2, 0, "AMD Ryzen 5000 (Vermeer %c%u)"); // PPR 56214 - FMm (10,15, 3, 0, "AMD Ryzen (Badami %c%u)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ + FMmQ(10,15, 3, 0, sE, "AMD EPYC 7A53 (3rd Gen) (Trento %c%u)"); // undocumented, but sample via instlatx64 from geekbench.com + FMmQ(10,15, 3, 0, dR, "AMD Ryzen (Badami %c%u)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ + FMm (10,15, 3, 0, "AMD (unknown type) (Badami/Trento %c%u)"); FMm (10,15, 4, 0, "AMD Ryzen 6000/7000 (Rembrandt %c%u)"); // undocumented, but instlatx64 samples FMm (10,15, 5, 0, "AMD Ryzen 5000 (Cezanne/Barcelo %c%u)"); // PPR 56569 - FMm (10,15, 6, 0, "AMD Ryzen 7000 (Raphael %c%u)"); // PPR 56713 + FMmQ(10,15, 6, 0, sE, "AMD EPYC 4000 (Raphael %c%u)"); // PPR 56713 + FMmQ(10,15, 6, 0, dR, "AMD Ryzen 7000 (Raphael %c%u)"); // PPR 56713 + FMm (10,15, 6, 0, "AMD (unknown type) (Raphael %c%u)"); // PPR 56713 FMm (10,15, 7, 0, "AMD Ryzen 7000/8000 (Phoenix/Hawk Point %c%u)"); // PPR 57019, instlatx64 sample of Ryzen 7 8845HS, which AMD also says is Hawk Point FM (10,15, 7,12, "AMD Ryzen (Hawk Point %c%u)"); // sample via instlatx64 from geekbench.com (special case only for model 12?) FMm (10,15, 7, 8, "AMD Ryzen (Phoenix 2 %c%u)"); // Coreboot* FMm (10,15, 8, 0, "AMD Instinct MI300C"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam FMm (10,15, 9, 0, "AMD Instinct MI300A"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam + // Rev Guide 57926 FMm (10,15, 10, 0, "AMD EPYC (4th Gen) (Bergamo/Siena %c%u)"); // PPR 57228 F (10,15, "AMD (unknown model)"); FMm (11,15, 0, 0, "AMD EPYC (5th Gen) (Turin %c%u)"); // PPR 57238, 58251 // https://docs.amd.com/v/u/en-US/dh300-amd-ryzen-threadripper-tr5: // The AMD Ryzen Threadripper Pro CPU (... and Model 1Ah Model 08h) FMm (11,15, 0, 8, "AMD EPYC (5th Gen) (Shimada Peak %c%u)"); - FMm (11,15, 1, 0, "AMD EPYC (5th Gen) (Sorano %c%u)"); // PPR 58730, LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 1, 8, "AMD EPYC (5th Gen) (Sorano %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 1, 0, "AMD EPYC (5th Gen) (Turin-Dense %c%u)"); // PPR 58730, LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 1, 8, "AMD EPYC (5th Gen) (Turin-Dense %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian // Are all these Strix Point's Ryzen AI 300 CPU's? // I suspect the latter ones are not. FMm (11,15, 2, 0, "AMD Ryzen AI 300 (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 2, 8, "AMD Ryzen AI 300 (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 0, "AMD Ryzen (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 8, "AMD Ryzen (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 4, 0, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // PPR 57896 + FMmQ(11,15, 4, 0, sE, "AMD EPYC 4005 (Grado %c%u)"); // undocumented, but screenshot via instlatx64 from https://www.phoronix.com/image-viewer.php?id=amd-epyc-4545p&image=amd_epyc_4545p_4_lrg + FMmQ(11,15, 4, 0, dR, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // PPR 57896 + FMm (11,15, 4, 0, "AMD (unknown type) (Granite Ridge/Grado %c%u)"); // PPR 57896 FMm (11,15, 4, 8, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 5, 0, "AMD EPYC (unknown type) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 5, 8, "AMD EPYC (unknown type) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 6, 0, "AMD Ryzen (Krackan Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 6, 8, "AMD Ryzen (Krackan Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 7, 0, "AMD Ryzen (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian - FMm (11,15, 7, 8, "AMD Ryzen (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 5, 0, "AMD EPYC (6th Gen) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 5, 8, "AMD EPYC (6th Gen) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 6, 0, "AMD Ryzen AI 300 (Krackan Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian, sample from instlatx64 + FMm (11,15, 6, 8, "AMD Ryzen AI 300 (Krackan Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + // PPR 57930, but it mentions no products and no architecture names + FMm (11,15, 7, 0, "AMD Ryzen AI 300 (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + FMm (11,15, 7, 8, "AMD Ryzen AI 300 (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian + // An LLVM patch from AMD's Umesh Kalvakuntla mentions (11,15),(13,*) as + // "Annapurna", presumably EPYC Embedded Annapurna. F (11,15, "AMD (unknown model)"); DEFAULT ("unknown"); @@ -5225,8 +5283,10 @@ FMS (9,15, 0, 0, 2, "Hygon Dhyana (A2)"); FMS (9,15, 0, 1, 1, "Hygon Dhyana (B1)"); FMS (9,15, 0, 2, 2, "Hygon Dhyana (C2)"); + // instlatx64 mentions: // (9,15),(0,4),1 is branded as Hygon C86-4G; perhaps Dhyana (E1)? // (9,15),(0,6),0 is branded as Hygon C86-4G; perhaps Dhyana (G0)? + // (9,15),(1,0),0 is branded as Hygon C86-4G 3450/3450G (with sample) DEFAULT ("unknown"); return result; @@ -5483,8 +5543,8 @@ unsigned int sub; for (sub = 0; sub < LENGTH(stash->val_1f_ecx); sub++) { unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[sub]); - if (level < LENGTH(v2TopoToCotopo)) { - unsigned ct = v2TopoToCotopo[level]; + if (level < LENGTH(intelV2TopoToCotopo)) { + unsigned ct = intelV2TopoToCotopo[level]; if (ct != Invalid) { unsigned int count = GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[sub]); @@ -5528,7 +5588,24 @@ break; case VENDOR_AMD: case VENDOR_HYGON: - if (stash->saw_b) { + if (stash->saw_80000026) { + stash->mp.method = "AMD leaf 0x80000026"; + unsigned int last_count = 1; + unsigned int sub; + for (sub = 0; sub < LENGTH(stash->val_80000026_ecx); sub++) { + unsigned int level + = GET_V2_TOPO_LEVEL(stash->val_80000026_ecx[sub]); + if (level < LENGTH(amdV2TopoToCotopo)) { + unsigned ct = amdV2TopoToCotopo[level]; + if (ct != Invalid) { + unsigned int count + = GET_V2_TOPO_PROCESSORS(stash->val_80000026_ebx[sub]); + stash->mp.count[ct] = count / last_count; + last_count = count; + } + } + } + } else if (stash->saw_b) { /* ** Logic by analogy to Intel */ @@ -5721,8 +5798,8 @@ for (sub = 0; sub < LENGTH(stash->val_1f_ecx); sub++) { unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[sub]); unsigned int width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[sub]); - if (level < LENGTH(v2TopoToCotopo)) { - unsigned ct = v2TopoToCotopo[level]; + if (level < LENGTH(intelV2TopoToCotopo)) { + unsigned ct = intelV2TopoToCotopo[level]; if (ct != Invalid) { widths[ct] = width - last_width; } @@ -5760,7 +5837,23 @@ ** And leaf 0x8000001e/ebx is used for smt_count, because 1/ebx is ** unreliable. */ - if (stash->saw_b) { + if (stash->saw_80000026) { + unsigned int last_width = 0; + unsigned int sub; + for (sub = 0; sub < LENGTH(stash->val_80000026_ecx); sub++) { + unsigned int level + = GET_V2_TOPO_LEVEL(stash->val_80000026_ecx[sub]); + unsigned int width + = GET_V2_TOPO_WIDTH(stash->val_80000026_eax[sub]); + if (level < LENGTH(amdV2TopoToCotopo)) { + unsigned ct = amdV2TopoToCotopo[level]; + if (ct != Invalid) { + widths[ct] = width - last_width; + } + } + last_width = width; + } + } else if (stash->saw_b) { widths[Smt] = GET_X2APIC_WIDTH(stash->val_b_eax[0]); widths[Core] = GET_X2APIC_WIDTH(stash->val_b_eax[1]) - widths[Smt]; } else if (IS_HTT(stash->val_1_edx) @@ -5819,7 +5912,9 @@ } unsigned int apic_id; - if (stash->saw_8000001e && Synth_Family(stash->val_1_eax) != 0x15) { + if (stash->saw_80000026) { + apic_id = stash->val_80000026_edx; + } else if (stash->saw_8000001e && Synth_Family(stash->val_1_eax) != 0x15) { // The 0x8000001e/eax extended APIC ID appears to have unreliable values // in the Piledriver..Excavator timeframe. apic_id = stash->val_8000001e_eax; @@ -6566,7 +6661,7 @@ = { { "SGX-KEYS: SGX attestation services" , 1, 1, bools }, { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools }, { "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools }, - { "fast short REP MOV" , 4, 4, bools }, + { "fast short REP MOVSB" , 4, 4, bools }, { "UINTR: user interrupts" , 5, 5, bools }, { "AVX512_VP2INTERSECT: intersect mask regs", 8, 8, bools }, { "IA32_MCU_OPT_CTRL SRBDS mitigation MSR" , 9, 9, bools }, @@ -6665,7 +6760,9 @@ { "CET_SSS: shadow stacks w/o page faults" , 18, 18, bools }, { "AVX10 instructions" , 19, 19, bools }, { "APX advanced performance extensions" , 21, 21, bools }, + { "SEC-TEE-ATTESTATION" , 22, 22, bools }, { "MWAIT instruction" , 23, 23, bools }, + { "SLSM: IA32_INTEGRITY_STATUS MSR" , 24, 24, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); @@ -6750,6 +6847,7 @@ = { { "number of contiguous fixed counters" , 0, 4, NIL_IMAGES }, { "bit width of fixed counters" , 5, 12, NIL_IMAGES }, { "anythread deprecation" , 15, 15, bools }, + { "TMA slots/cycle" , 16, 19, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), @@ -6782,10 +6880,10 @@ print_b_1f_ecx(unsigned int value) { // If more levels are added here, be sure to check: - // V2_TOPO_NUM + // INTEL_V2_TOPO_NUM // val_1f_{eax,ebx,ecx} (in code_stash_t) // NIL_STASH - // v2TopotoCotopo + // intelV2TopoToCotopo // Cotopo static ccstring level_type[1<<8] = { "invalid (0)", "thread (1)", @@ -6831,6 +6929,11 @@ { " PKRU state" , 9, 9, bools }, { " XTILECFG state" , 17, 17, bools }, { " XTILEDATA state" , 18, 18, bools }, + // bit 19 doesn't appear to be documented anywhere, but sub-leaf 19, + // is described in "Intel Advanced Performance Extensions (Intel + // APX)", Intel doc 355828, and the sub-leaf only could be enumerated + // if bit 19 was set here. + { " APX EGPR" , 19, 19, bools }, }; print_names(value, names, LENGTH(names), @@ -7765,6 +7868,7 @@ static named_item names[] = { { "IA32_PERFEVTSELx UnitMask2 supported" , 0, 0, bools }, { "IA32_PERFEVTSELx EQ bit supported" , 1, 1, bools }, + { "RDPMC_USR_DISABLE supported" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), @@ -7820,11 +7924,13 @@ { "CNTR fixed-function subgroup support" , 5, 5, bools }, { "CNTR perf metrics subgroup support" , 6, 6, bools }, { "LBR bits support" , 8, 9, lbrs }, - { "XER XMMn support" , 16, 16, bools }, - { "XER YMMn Hi support" , 17, 17, bools }, - { "XER AVX-512 opmask support" , 20, 20, bools }, - { "XER AVX-512 ZMM_Hi256 support" , 21, 21, bools }, - { "XER AVX-512 Hi16_ZMM support" , 22, 22, bools }, + // Bits 17-23 correspond to XER bits 49-55 (32 bit offset) + { "XER XMMn support" , 17, 17, bools }, + { "XER YMMn Hi 128 support" , 18, 18, bools }, + { "XER R16-R31 support" , 19, 19, bools }, + { "XER AVX-512 opmask K0-K7 support" , 21, 21, bools }, + { "XER AVX-512 ZMM0-ZMM15 Hi 256 support" , 22, 22, bools }, + { "XER AVX-512 ZMM16-31 support" , 23, 23, bools }, { "general-purpose group is available" , 29, 29, bools }, { "auxiliary group is available" , 30, 30, bools }, }; @@ -7903,7 +8009,7 @@ print_28_1_eax(unsigned int value) { static named_item names[] - = { { "length of capacity bit mask" , 0, 7, MINUS1_IMAGES }, + = { { "length of capacity bit mask" , 0, 4, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), @@ -8003,6 +8109,17 @@ } static void +print_29_0_ebx(unsigned int value) +{ + static named_item names[] + = { { "NCI, NDD, NF support" , 0, 0, NIL_IMAGES }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 0); +} + +static void print_20000001_edx(unsigned int value) { // I found a vague reference to this leaf in Intel Xeon Phi Coprocessor @@ -8321,6 +8438,7 @@ { "synthetic timers are volatile" , 9, 9, bools }, { "hypervisor level of current guest" , 10, 13, NIL_IMAGES }, { "physical destination mode requested" , 14, 14, bools }, + { "use VMFUNC for alias map switch" , 15, 15, bools }, { "hardware memory zeroing support" , 16, 16, bools }, { "unrestricted guest support" , 17, 17, bools }, { "resource allocation support" , 18, 18, bools }, @@ -8562,6 +8680,7 @@ = { { "generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES }, + { "type" , 12, 13, NIL_IMAGES }, }; printf(" extended processor signature (0x80000001/eax):\n"); @@ -9423,9 +9542,8 @@ = { { "SvmRev: SVM revision" , 0, 7, NIL_IMAGES }, }; - printf(" SVM Secure Virtual Machine (0x8000000a/eax):\n"); print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 39); } static void @@ -9463,15 +9581,25 @@ { "EXITINFO1 non-interceptible shutdown" , 31, 31, bools }, }; - printf(" SVM Secure Virtual Machine (0x8000000a/edx):\n"); print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 39); +} + +static void +print_8000000a_ecx(unsigned int value) +{ + static named_item names[] + = { { "x2AVIC_EXT: 4096 vCPUs supported" , 6, 6, bools }, + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 39); } static void print_8000000a_ebx(unsigned int value) { - printf(" NASID: number of address space identifiers = 0x%x (%u):\n", + printf(" NASID: number of address space IDs = 0x%x (%u)\n", value, value); } @@ -9783,6 +9911,7 @@ = { { "encryption bit position in PTE" , 0, 5, NIL_IMAGES }, { "physical address space width reduction" , 6, 11, NIL_IMAGES }, { "number of VM permission levels" , 12, 15, NIL_IMAGES }, + { "not vulnerable to SNP cache coherency" , 31, 31, bools }, // LX* }; print_names(value, names, LENGTH(names), /* max_len => */ 40); @@ -9878,15 +10007,17 @@ { static named_item names[] = { { "no nested data-breakpoints" , 0, 0, bools }, - { "FsGsKernelGsBaseNonSerializing" , 1, 1, bools }, + { "WRMSR to FS/GS base is not serializing" , 1, 1, bools }, { "LFENCE always serializing" , 2, 2, bools }, { "SMM paging configuration lock support" , 3, 3, bools }, + { "VERW memory form mitigates TSA" , 5, 5, bools }, // LX*, Qemu* { "null selector clears base" , 6, 6, bools }, { "upper address ignore support" , 7, 7, bools }, { "automatic IBRS" , 8, 8, bools }, { "SMM_CTL MSR not supported" , 9, 9, bools }, { "FSRS: fast short REP STOSB support" , 10, 10, bools }, { "FSRC: fast short REP CMPSB support" , 11, 11, bools }, + { "PerfEvtSel2 MSR PreciseRetire support" , 12, 12, bools }, { "prefetch control MSR support" , 13, 13, bools }, { "L2TLB sizes are multiples of 32" , 14, 14, bools }, { "AMD enhanced REP MOVSB/STOSB" , 15, 15, bools }, @@ -9895,8 +10026,8 @@ { "enhanced predictive store forwarding" , 18, 18, bools }, { "fast short REP SCASB support" , 19, 19, bools }, { "IC PREFETCH support" , 20, 20, bools }, - { "FP512 to FP256 downgrade support" , 21, 21, bools }, - { "workload OS feedback support" , 22, 22, bools }, + { "FP512 is downgraded to FP256" , 21, 21, bools }, + { "workload OS feedback support" , 22, 22, bools }, // LX* calls this ABMC: Assignable Bandwidth Monitoring Counters { "ret addr predictor security support" , 24, 24, bools }, { "guest: selective branch pred barrier" , 27, 27, bools }, { "guest: PRED_CMD[IBPB] flushes br predict", 28, 28, bools }, @@ -9906,13 +10037,13 @@ }; print_names(value, names, LENGTH(names), - /* max_len => */ 0); + /* max_len => */ 40); } static void print_80000021_ebx(unsigned int value) { - unsigned int ups = BIT_EXTRACT_LE(value, 0, 12) * 16; + unsigned int ups = BIT_EXTRACT_LE(value, 0, 16) * 16; printf(" microcode patch size = "); if (ups == 0) { printf("<= 0x15c0 (5568) (legacy value)\n"); @@ -9926,6 +10057,18 @@ } static void +print_80000021_ecx(unsigned int value) +{ + static named_item names[] + = { { "not vulnerable to TSA-SQ" , 1, 1, bools }, // LX* + { "not vulnerable to TSA-L1" , 2, 2, bools }, // LX* + }; + + print_names(value, names, LENGTH(names), + /* max_len => */ 40); +} + +static void print_80000022_eax(unsigned int value) { static named_item names[] @@ -9991,6 +10134,7 @@ { static named_item names[] = { { "cacheable RMP segment definitions" , 0, 9, NIL_IMAGES }, + { "number of RMP segments reduced" , 10, 10, bools }, { "cached segments hard limit" , 11, 11, bools }, }; @@ -10046,6 +10190,12 @@ static void print_80000026_ecx(unsigned int value) { + // If more levels are added here, be sure to check: + // AMD_V2_TOPO_NUM + // val_80000026_{eax,ebx,ecx} (in code_stash_t) + // NIL_STASH + // amdV2TopoToCotopo + // Cotopo static ccstring level_type[1<<8] = { "invalid (0)", "core (1)", "complex (2)", @@ -10069,6 +10219,7 @@ = { { "generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES }, + { "type" , 12, 13, NIL_IMAGES }, }; printf(" Transmeta processor signature (0x80860001/eax):\n"); @@ -10133,7 +10284,7 @@ print_80860001_ebx_ecx(unsigned int val_ebx, unsigned int val_ecx) { - printf(" Transmeta processor revision (0x80000001/edx)" + printf(" Transmeta processor revision (0x80860001)" " = %u.%u-%u.%u-%u ", (val_ebx >> 24) & 0xff, (val_ebx >> 16) & 0xff, @@ -10189,6 +10340,18 @@ { "padlock hash engine (PHE) enabled" , 11, 11, bools }, { "padlock montgomery mult. (PMM)" , 12, 12, bools }, // LX* { "padlock montgomery mult. (PMM) enabled" , 13, 13, bools }, // LX* + // Following 10 bits all from: + // https://lore.kernel.org/all/[email protected] + { "PARALLAX voltage adjustment" , 16, 16, bools }, + { "PARALLAX voltage adjustment enabled" , 17, 17, bools }, + { "thermal monitor 3 (TM3)" , 20, 20, bools }, + { "thermal monitor 3 (TM3) enabled" , 21, 21, bools }, + { "random number generator 2 (RNG2)" , 22, 22, bools }, + { "random number generator 2 (RNG2) enabled" , 23, 23, bools }, + { "padlock hash engine 2 (PHE2)" , 25, 25, bools }, + { "padlock hash engine 2 (PHE2) enabled" , 26, 26, bools }, + { "RSA hardware support" , 27, 27, bools }, + { "RSA hardware support enabled" , 28, 28, bools }, }; printf(" extended feature flags (0xc0000001/edx):\n"); @@ -10591,6 +10754,20 @@ stash->saw_8000001e = TRUE; stash->val_8000001e_eax = words[WORD_EAX]; stash->val_8000001e_ebx = words[WORD_EBX]; + } else if (reg == 0x80000026) { + stash->saw_80000026 = TRUE; + if (sub == 0) { + stash->val_80000026_edx = words[WORD_EDX]; + } + if (sub < LENGTH(stash->val_1f_eax)) { + stash->val_80000026_eax[sub] = words[WORD_EAX]; + } + if (sub < LENGTH(stash->val_1f_ebx)) { + stash->val_80000026_ebx[sub] = words[WORD_EBX]; + } + if (sub < LENGTH(stash->val_1f_ecx)) { + stash->val_80000026_ecx[sub] = words[WORD_ECX]; + } } else if (reg == 0x80860003) { memcpy(&stash->transmeta_info[0], words, sizeof(unsigned int)*WORD_NUM); @@ -11066,6 +11243,13 @@ } else { print_reg_raw(reg, sub, words); } + } else if (reg == 0x29) { + if (sub == 0) { + printf(" Intel APX Advanced Performance Extensions (0x29):\n"); + print_29_0_ebx(words[WORD_EBX]); + } else { + print_reg_raw(reg, sub, words); + } } else if (reg == 0x20000000) { // max already set to words[WORD_EAX] in calling function } else if (reg == 0x20000001) { @@ -11295,8 +11479,10 @@ } else if (reg == 0x80000009) { /* reserved for Intel feature flag expansion */ } else if (reg == 0x8000000a) { + printf(" SVM Secure Virtual Machine (0x8000000a):\n"); print_8000000a_eax(words[WORD_EAX]); print_8000000a_edx(words[WORD_EDX]); + print_8000000a_ecx(words[WORD_ECX]); print_8000000a_ebx(words[WORD_EBX]); } else if (0x8000000b <= reg && reg <= 0x80000018) { /* reserved for vendors to be determined feature flag expansion */ @@ -11379,6 +11565,7 @@ printf(" Extended Feature 2 (0x80000021):\n"); print_80000021_eax(words[WORD_EAX]); print_80000021_ebx(words[WORD_EBX]); + print_80000021_ecx(words[WORD_ECX]); } else if (reg == 0x80000022) { printf(" Extended Performance Monitoring and Debugging (0x80000022):\n"); print_80000022_eax(words[WORD_EAX]); @@ -11415,6 +11602,8 @@ print_80860001_eax(words[WORD_EAX], opts); print_80860001_edx(words[WORD_EDX]); print_80860001_ebx_ecx(words[WORD_EBX], words[WORD_ECX]); + printf(" Transmeta nominal core clock frequency = %u MHz\n", + words[WORD_ECX]); } else if (reg == 0x80860002) { print_80860002_eax(words[WORD_EAX], stash); printf(" Transmeta CMS revision (0x80000002/ecx)" @@ -12094,14 +12283,14 @@ print_reg(reg, sub, words, opts, &stash); } } - } else if (reg == 0x80000026) { - print_reg(reg, 0, words, opts, &stash); - unsigned int sub; - for (sub = 1; sub < 256; sub++) { - real_get(cpuid_fd, reg, sub, words, FALSE); + } else if (reg == 0x29) { + unsigned int max_subs = words[WORD_EAX]; + unsigned int sub = 0; + for (;;) { print_reg(reg, sub, words, opts, &stash); - // exit when level type indicates invalid (0). - if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break; + sub++; + if (sub > max_subs) break; + real_get(cpuid_fd, reg, sub, words, FALSE); } } else { print_reg(reg, 0, words, opts, &stash); @@ -12221,6 +12410,15 @@ print_reg(reg, sub, words, opts, &stash); } } + } else if (reg == 0x80000026) { + print_reg(reg, 0, words, opts, &stash); + unsigned int sub; + for (sub = 1; sub < 256; sub++) { + real_get(cpuid_fd, reg, sub, words, FALSE); + print_reg(reg, sub, words, opts, &stash); + // exit when level type indicates invalid (0). + if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break; + } } else { print_reg(reg, 0, words, opts, &stash); } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/cpuid.man new/cpuid-20260220/cpuid.man --- old/cpuid-20250513/cpuid.man 2025-05-13 13:19:16.000000000 +0200 +++ new/cpuid-20260220/cpuid.man 2026-02-20 14:43:36.000000000 +0100 @@ -1,7 +1,7 @@ .\" -.\" $Id: cpuid.man,v 20250513 2025/05/13 05:18:57 todd $ +.\" $Id: cpuid.man,v 20260220 2026/02/20 06:43:23 todd $ .\" -.TH CPUID 1 "13 May 2025" "20250513" +.TH CPUID 1 "20 Feb 2026" "20260220" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS @@ -539,6 +539,8 @@ .br 709192: Intel Xeon E-2300 Processor Family Specification Update .br +714069: Intel Xeon D-1700 and D-1800 Processor Families Specification Update +.br 714071: Intel Xeon D-2700 Processor Family Specification Update .br 743844: 13th Generation Intel Core Processors Datasheet, Volume 1 of 2 @@ -568,6 +570,10 @@ .br 843306: Intel Xeon 6700P-B/6500P-B-Series SoC with P-Cores Specification Update .br +869992: Intel Core Ultra Processors (Series 3) Specification Update +.br +872188: Intel Core Ultra Processors (Series 3) Datasheet, Volume 1 of 2 +.br Intel Microcode Update Guidance .br Branch History Injection and Intra-mode Branch Target Injection / diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/cpuid.proto.spec new/cpuid-20260220/cpuid.proto.spec --- old/cpuid-20250513/cpuid.proto.spec 2020-02-02 15:59:52.000000000 +0100 +++ new/cpuid-20260220/cpuid.proto.spec 1970-01-01 01:00:00.000000000 +0100 @@ -1,34 +0,0 @@ -Summary: dumps CPUID information about the CPU(s) -Name: cpuid -Version: %{version} -Release: %{release} -License: GPL -Group: System Environment/Base -Source: cpuid-%{version}.src.tar.gz -Packager: Todd Allen <[email protected]> -URL: http://www.etallen.com/cpuid.html -BuildRoot: %{getenv:HOME}/rpmbuild/BUILDROOT/%{name}-%{version}-%{release}.%{_arch} -%description -cpuid dumps detailed information about the CPU(s) gathered from the CPUID -instruction, and also determines the exact model of CPU(s). - -%prep -%setup - -%build -%{__make} %{?_smp_mflags} CFLAGS="$RPM_OPT_FLAGS" - -%install -%{__make} install BUILDROOT=${RPM_BUILD_ROOT} INSTALL_STRIP= - -%clean -%{__rm} -rf $RPM_BUILD_DIR/$RPM_PACKAGE_NAME-$RPM_PACKAGE_VERSION - -%files -%defattr(-,root,root) -%{_bindir}/cpuid -%{_mandir}/man1/cpuid.1.gz -%{_bindir}/cpuinfo2cpuid -%{_mandir}/man1/cpuinfo2cpuid.1.gz -%doc ChangeLog FUTURE FAMILY.NOTES -%license LICENSE diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/cpuid.protospec new/cpuid-20260220/cpuid.protospec --- old/cpuid-20250513/cpuid.protospec 1970-01-01 01:00:00.000000000 +0100 +++ new/cpuid-20260220/cpuid.protospec 2020-02-02 15:59:52.000000000 +0100 @@ -0,0 +1,34 @@ +Summary: dumps CPUID information about the CPU(s) +Name: cpuid +Version: %{version} +Release: %{release} +License: GPL +Group: System Environment/Base +Source: cpuid-%{version}.src.tar.gz +Packager: Todd Allen <[email protected]> +URL: http://www.etallen.com/cpuid.html +BuildRoot: %{getenv:HOME}/rpmbuild/BUILDROOT/%{name}-%{version}-%{release}.%{_arch} +%description +cpuid dumps detailed information about the CPU(s) gathered from the CPUID +instruction, and also determines the exact model of CPU(s). + +%prep +%setup + +%build +%{__make} %{?_smp_mflags} CFLAGS="$RPM_OPT_FLAGS" + +%install +%{__make} install BUILDROOT=${RPM_BUILD_ROOT} INSTALL_STRIP= + +%clean +%{__rm} -rf $RPM_BUILD_DIR/$RPM_PACKAGE_NAME-$RPM_PACKAGE_VERSION + +%files +%defattr(-,root,root) +%{_bindir}/cpuid +%{_mandir}/man1/cpuid.1.gz +%{_bindir}/cpuinfo2cpuid +%{_mandir}/man1/cpuinfo2cpuid.1.gz +%doc ChangeLog FUTURE FAMILY.NOTES +%license LICENSE diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/cpuid-20250513/cpuid.spec new/cpuid-20260220/cpuid.spec --- old/cpuid-20250513/cpuid.spec 2025-05-13 13:21:24.000000000 +0200 +++ new/cpuid-20260220/cpuid.spec 2026-02-20 14:44:46.000000000 +0100 @@ -1,4 +1,4 @@ -%define version 20250513 +%define version 20260220 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid
