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Hello community,
here is the log from the commit of package spirv-llvm-translator for
openSUSE:Factory checked in at 2026-05-05 15:14:28
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/spirv-llvm-translator (Old)
and /work/SRC/openSUSE:Factory/.spirv-llvm-translator.new.30200 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "spirv-llvm-translator"
Tue May 5 15:14:28 2026 rev:31 rq:1350700 version:22.1.2
Changes:
--------
---
/work/SRC/openSUSE:Factory/spirv-llvm-translator/spirv-llvm-translator.changes
2026-04-23 17:09:32.036901026 +0200
+++
/work/SRC/openSUSE:Factory/.spirv-llvm-translator.new.30200/spirv-llvm-translator.changes
2026-05-05 15:14:29.493002159 +0200
@@ -1,0 +2,8 @@
+Sun May 3 20:45:24 UTC 2026 - Aaron Puchert <[email protected]>
+
+- Update to version 22.1.2.
+ * Add SPV_INTEL_subgroup_buffer_prefetch extension support.
+ * Extend INT4/FP4 packed conversions for i16, i64, and vector
+ packed inputs.
+
+-------------------------------------------------------------------
Old:
----
SPIRV-LLVM-Translator-22.1.1.tar.gz
New:
----
SPIRV-LLVM-Translator-22.1.2.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ spirv-llvm-translator.spec ++++++
--- /var/tmp/diff_new_pack.cOuYQd/_old 2026-05-05 15:14:29.949021043 +0200
+++ /var/tmp/diff_new_pack.cOuYQd/_new 2026-05-05 15:14:29.953021209 +0200
@@ -23,7 +23,7 @@
%define sover 22
Name: spirv-llvm-translator
-Version: 22.1.1
+Version: 22.1.2
Release: 0
Summary: LLVM/SPIR-V Bi-Directional Translator library
License: BSD-3-Clause
++++++ SPIRV-LLVM-Translator-22.1.1.tar.gz ->
SPIRV-LLVM-Translator-22.1.2.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/include/LLVMSPIRVExtensions.inc
new/SPIRV-LLVM-Translator-22.1.2/include/LLVMSPIRVExtensions.inc
--- old/SPIRV-LLVM-Translator-22.1.1/include/LLVMSPIRVExtensions.inc
2026-03-11 13:48:51.000000000 +0100
+++ new/SPIRV-LLVM-Translator-22.1.2/include/LLVMSPIRVExtensions.inc
2026-04-30 17:43:46.000000000 +0200
@@ -72,6 +72,7 @@
EXT(SPV_INTEL_fpga_latency_control)
EXT(SPV_INTEL_fp_max_error)
EXT(SPV_INTEL_cache_controls)
+EXT(SPV_INTEL_subgroup_buffer_prefetch)
EXT(SPV_INTEL_subgroup_requirements)
EXT(SPV_INTEL_task_sequence)
EXT(SPV_INTEL_maximum_registers)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/SPIRVUtil.cpp
new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/SPIRVUtil.cpp
--- old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/SPIRVUtil.cpp 2026-03-11
13:48:51.000000000 +0100
+++ new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/SPIRVUtil.cpp 2026-04-30
17:43:46.000000000 +0200
@@ -2493,6 +2493,12 @@
setArgAttr(0, SPIR::ATTR_CONST);
addUnsignedArg(0);
break;
+ case OpSubgroupBlockPrefetchINTEL:
+ setArgAttr(0, SPIR::ATTR_CONST);
+ addUnsignedArg(0);
+ addUnsignedArg(1);
+ addUnsignedArg(2); // optional Memory Operands bitmask
+ break;
case OpAtomicUMax:
case OpAtomicUMin:
addUnsignedArg(0);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/SPIRVWriter.cpp
new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/SPIRVWriter.cpp
--- old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/SPIRVWriter.cpp 2026-03-11
13:48:51.000000000 +0100
+++ new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/SPIRVWriter.cpp 2026-04-30
17:43:46.000000000 +0200
@@ -5559,21 +5559,18 @@
unsigned TyWidth = cast<IntegerType>(ScalarTy)->getBitWidth();
unsigned VecSize = 0;
- if (TyWidth == 32) {
- // Int4 or FP4 packed in 32-bit integer, change type and vector size.
- assert((Encoding == FPEncodingWrap::E2M1 ||
- Encoding == FPEncodingWrap::Integer) &&
- "Unknown FP encoding");
+ bool IsPacked =
+ Encoding == FPEncodingWrap::E2M1 || Encoding == FPEncodingWrap::Integer;
+ if (IsPacked &&
+ (TyWidth == 8 || TyWidth == 16 || TyWidth == 32 || TyWidth == 64)) {
+ // Int4 or FP4 packed in an integer: each N-bit integer holds N/4 values.
assert(!isLLVMCooperativeMatrixType(LLVMTy) &&
"FP4 and Int4 matrices must not be packed");
- VecSize = 8;
- TyWidth = 4;
- } else if (TyWidth == 8 && (Encoding == FPEncodingWrap::E2M1 ||
- Encoding == FPEncodingWrap::Integer)) {
- assert(!isLLVMCooperativeMatrixType(LLVMTy) &&
- "FP4 and Int4 matrices must not be packed");
- // Int4 or FP4 packed in 8-bit integer, change type and vector size.
- VecSize = 2;
+ unsigned OuterVecLen =
+ LLVMTy->isVectorTy()
+ ? cast<VectorType>(LLVMTy)->getElementCount().getFixedValue()
+ : 1;
+ VecSize = (TyWidth / 4) * OuterVecLen;
TyWidth = 4;
} else {
if (LLVMTy->isVectorTy())
@@ -5669,14 +5666,16 @@
->getArgs());
SrcOp = BM->addUnaryInst(OpBitcast, SrcTy, SrcOp, BB);
} else if (FPDesc.SrcEncoding != FPEncodingWrap::Integer ||
- (SrcTy->isTypeVector() && !LLVMSrcTy->isVectorTy())) {
- // Create bitcast for FP4, FP8 and packed Int4.
+ SrcVecSize > 0) {
+ // Create bitcast for FP4, FP8 and packed Int4 (including cases where
+ // both the LLVM and SPIR-V types are vectors but with different
+ // sizes, e.g. <2 x i8> repacked as <4 x Int4>).
SrcOp = BM->addUnaryInst(OpBitcast, SrcTy, SrcOp, BB);
}
}
+ unsigned DstVecSize = 0;
if (!DstTy) {
// Dst type is 'mini' float or int4.
- unsigned DstVecSize = 0;
DstTy = processMiniFPOrInt4Type(LLVMDstTy, FPDesc.DstEncoding,
GetScalarTy, BM, DstVecSize);
@@ -5704,10 +5703,9 @@
if (FPDesc.DstEncoding == FPEncodingWrap::IEEE754 ||
FPDesc.DstEncoding == FPEncodingWrap::BF16)
return Conv;
- // Originally not-packed integer.
+ // Originally not-packed integer (no repacking, or cooperative matrix).
if (FPDesc.DstEncoding == FPEncodingWrap::Integer &&
- (DstTy->isTypeVector() == LLVMDstTy->isVectorTy() ||
- isLLVMCooperativeMatrixType(LLVMDstTy)))
+ (DstVecSize == 0 || isLLVMCooperativeMatrixType(LLVMDstTy)))
return Conv;
// Need to adjust types: create bitcast for FP8 and packed Int4.
SPIRVValue *BitCast =
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/libSPIRV/SPIRVInstruction.h
new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/libSPIRV/SPIRVInstruction.h
--- old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/libSPIRV/SPIRVInstruction.h
2026-03-11 13:48:51.000000000 +0100
+++ new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/libSPIRV/SPIRVInstruction.h
2026-04-30 17:43:46.000000000 +0200
@@ -4392,6 +4392,46 @@
std::vector<SPIRVId> CacheTy;
};
+class SPIRVSubgroupBlockPrefetchINTELInst : public SPIRVInstTemplateBase {
+public:
+ std::optional<ExtensionID> getRequiredExtension() const override {
+ return ExtensionID::SPV_INTEL_subgroup_buffer_prefetch;
+ }
+ SPIRVCapVec getRequiredCapability() const override {
+ return getVec(CapabilitySubgroupBufferPrefetchINTEL);
+ }
+ // Operand 2, if present, is the Memory Operands bitmask.
+ bool isOperandLiteral(unsigned I) const override { return I == 2; }
+
+protected:
+ void validate() const override {
+ SPIRVInstruction::validate();
+ if (getValue(Ops[0])->isForward())
+ return;
+ SPIRVErrorLog &SPVErrLog = getModule()->getErrorLog();
+ SPIRVType *PtrType = getValueType(Ops[0]);
+ std::string InstName = "OpSubgroupBlockPrefetchINTEL";
+ SPVErrLog.checkError(
+ PtrType->isTypePointer() || PtrType->isTypeUntypedPointerKHR(),
+ SPIRVEC_InvalidInstruction, InstName + "\nPtr must be a pointer\n");
+ SPVErrLog.checkError(
+ PtrType->getPointerStorageClass() == StorageClassCrossWorkgroup,
+ SPIRVEC_InvalidInstruction,
+ InstName + "\nPtr must be in CrossWorkgroup storage class\n");
+ if (!PtrType->isTypeUntypedPointerKHR())
+ SPVErrLog.checkError(PtrType->getPointerElementType()->isTypeInt(),
+ SPIRVEC_InvalidInstruction,
+ InstName +
+ "\nPtr must point to a scalar integer type\n");
+ SPVErrLog.checkError(
+ getValueType(Ops[1])->isTypeInt(32), SPIRVEC_InvalidInstruction,
+ InstName + "\nNumBytes must be a 32-bit integer scalar\n");
+ }
+};
+typedef SPIRVInstTemplate<SPIRVSubgroupBlockPrefetchINTELInst,
+ OpSubgroupBlockPrefetchINTEL, false, 3, true>
+ SPIRVSubgroupBlockPrefetchINTEL;
+
class SPIRVSubgroup2DBlockIOINTELInst : public SPIRVInstTemplateBase {
public:
std::optional<ExtensionID> getRequiredExtension() const override {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
--- old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
2026-03-11 13:48:51.000000000 +0100
+++ new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
2026-04-30 17:43:46.000000000 +0200
@@ -563,6 +563,7 @@
add(CapabilityBindlessTextureNV, "BindlessTextureNV");
add(CapabilitySubgroupShuffleINTEL, "SubgroupShuffleINTEL");
add(CapabilitySubgroupBufferBlockIOINTEL, "SubgroupBufferBlockIOINTEL");
+ add(CapabilitySubgroupBufferPrefetchINTEL, "SubgroupBufferPrefetchINTEL");
add(CapabilitySubgroupImageBlockIOINTEL, "SubgroupImageBlockIOINTEL");
add(CapabilitySubgroupImageMediaBlockIOINTEL,
"SubgroupImageMediaBlockIOINTEL");
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
--- old/SPIRV-LLVM-Translator-22.1.1/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
2026-03-11 13:48:51.000000000 +0100
+++ new/SPIRV-LLVM-Translator-22.1.2/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
2026-04-30 17:43:46.000000000 +0200
@@ -574,6 +574,7 @@
_SPIRV_OP(ControlBarrierArriveINTEL, 6142)
_SPIRV_OP(ControlBarrierWaitINTEL, 6143)
_SPIRV_OP(ArithmeticFenceEXT, 6145)
+_SPIRV_OP(SubgroupBlockPrefetchINTEL, 6221)
_SPIRV_OP(Subgroup2DBlockLoadINTEL, 6231)
_SPIRV_OP(Subgroup2DBlockLoadTransformINTEL, 6232)
_SPIRV_OP(Subgroup2DBlockLoadTransposeINTEL, 6233)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll
2026-03-11 13:48:51.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll
2026-04-30 17:43:46.000000000 +0200
@@ -5,9 +5,15 @@
; 1. from packed FP4 to ... :
; a. packed in 32-bit
; b. packed in 8-bit
+; c. packed in 16-bit
+; d. packed in 64-bit
+; e. packed in vector of 8-bit integers
; 2. to packed FP4 from ... :
; a. packed in 32-bit
; b. packed in 8-bit
+; c. packed in 16-bit
+; d. packed in 64-bit
+; e. packed in vector of 8-bit integers
; RUN: llvm-spirv %s -o %t.spv
--spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16
; RUN: llvm-spirv %t.spv -o %t.spt --to-text
@@ -25,29 +31,50 @@
; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_8:]] "fp4e2m1_hf8_8"
; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_32:]] "hf16_fp4e2m1_32"
; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_8:]] "hf16_fp4e2m1_8"
+; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_16:]] "fp4e2m1_hf8_16"
+; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_64:]] "fp4e2m1_hf8_64"
+; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_vec2xi8:]] "fp4e2m1_hf8_vec2xi8"
+; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_16:]] "hf16_fp4e2m1_16"
+; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_64:]] "hf16_fp4e2m1_64"
+; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_vec2xi8:]] "hf16_fp4e2m1_vec2xi8"
; CHECK-SPIRV-DAG: TypeInt [[#Int32Ty:]] 32 0
; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#Int32Const:]] 1
; CHECK-SPIRV-DAG: TypeInt [[#Int8Ty:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int16Ty:]] 16 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int64Ty:]] 64 0
; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec8Ty:]] [[#Int8Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec2Ty:]] [[#Int8Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec4Ty:]] [[#Int8Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec16Ty:]] [[#Int8Ty]] 16
; CHECK-SPIRV-DAG: Constant [[#Int8Ty]] [[#Int8Const:]] 1
+; CHECK-SPIRV-DAG: Constant [[#Int16Ty]] [[#Int16Const:]] 1
+; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#Int64Const:]] 1
+; CHECK-SPIRV-DAG: ConstantComposite [[#Int8Vec2Ty]] [[#Int8Vec2Const:]]
[[#Int8Const]] [[#Int8Const]]
; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214
; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec8Ty:]] [[#E2M1Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec2Ty:]] [[#E2M1Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec4Ty:]] [[#E2M1Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec16Ty:]] [[#E2M1Ty]] 16
; CHECK-SPIRV-DAG: TypeFloat [[#Float8E4M3Ty:]] 8 4214
; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec8Ty:]] [[#Float8E4M3Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec2Ty:]] [[#Float8E4M3Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec4Ty:]] [[#Float8E4M3Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec16Ty:]] [[#Float8E4M3Ty]] 16
; CHECK-SPIRV-DAG: TypeFloat [[#HFloat16Ty:]] 16 {{$}}
; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec8Ty:]] [[#HFloat16Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec2Ty:]] [[#HFloat16Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec4Ty:]] [[#HFloat16Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec16Ty:]] [[#HFloat16Ty]] 16
; CHECK-SPIRV-DAG: Constant [[#HFloat16Ty]] [[#HFloat16Const:]] 15360
; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec8Ty]]
[[#HFloat16Vec8Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]]
; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec2Ty]]
[[#HFloat16Vec2Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
+; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec4Ty]]
[[#HFloat16Vec4Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]]
+; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec16Ty]]
[[#HFloat16Vec16Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]]
target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir-unknown-unknown"
@@ -129,3 +156,126 @@
}
declare dso_local spir_func i8
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half>)
+
+; Packed in 16-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf8_16]] [[#]]
+; CHECK-SPIRV: Bitcast [[#E2M1Vec4Ty]] [[#Cast1:]] [[#Int16Const]]
+; CHECK-SPIRV: FConvert [[#Float8E4M3Vec4Ty]] [[#Conv:]] [[#Cast1]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec4Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: fp4e2m1_hf8_16
+; CHECK-LLVM: %[[#Cast:]] = bitcast i16 1 to <4 x i4>
+; CHECK-LLVM: %[[#Call:]] = call <4 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]])
+; CHECK-LLVM: ret <4 x i8> %[[#Call]]
+
+define spir_func <4 x i8> @fp4e2m1_hf8_16() {
+entry:
+ %0 = call spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELs(i16 1)
+ ret <4 x i8> %0
+}
+
+declare dso_local spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELs(i16)
+
+; Packed in 64-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf8_64]] [[#]]
+; CHECK-SPIRV: Bitcast [[#E2M1Vec16Ty]] [[#Cast1:]] [[#Int64Const]]
+; CHECK-SPIRV: FConvert [[#Float8E4M3Vec16Ty]] [[#Conv:]] [[#Cast1]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec16Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: fp4e2m1_hf8_64
+; CHECK-LLVM: %[[#Cast:]] = bitcast i64 1 to <16 x i4>
+; CHECK-LLVM: %[[#Call:]] = call <16 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv16_i(<16 x i4> %[[#Cast]])
+; CHECK-LLVM: ret <16 x i8> %[[#Call]]
+
+define spir_func <16 x i8> @fp4e2m1_hf8_64() {
+entry:
+ %0 = call spir_func <16 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELl(i64 1)
+ ret <16 x i8> %0
+}
+
+declare dso_local spir_func <16 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELl(i64)
+
+; Packed in vector of 8-bit integers
+
+; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf8_vec2xi8]] [[#]]
+; CHECK-SPIRV: Bitcast [[#E2M1Vec4Ty]] [[#Cast1:]] [[#Int8Vec2Const]]
+; CHECK-SPIRV: FConvert [[#Float8E4M3Vec4Ty]] [[#Conv:]] [[#Cast1]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec4Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: fp4e2m1_hf8_vec2xi8
+; CHECK-LLVM: %[[#Cast:]] = bitcast <2 x i8> splat (i8 1) to <4 x i4>
+; CHECK-LLVM: %[[#Call:]] = call <4 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]])
+; CHECK-LLVM: ret <4 x i8> %[[#Call]]
+
+define spir_func <4 x i8> @fp4e2m1_hf8_vec2xi8() {
+entry:
+ %0 = call spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<2 x i8> <i8 1, i8 1>)
+ ret <4 x i8> %0
+}
+
+declare dso_local spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<2 x i8>)
+
+; To packed in 16-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_16]] [[#]]
+; CHECK-SPIRV: FConvert [[#E2M1Vec4Ty]] [[#Conv:]] [[#HFloat16Vec4Const]]
+; CHECK-SPIRV: Bitcast [[#Int16Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: hf16_fp4e2m1_16
+; CHECK-LLVM: %[[#Call:]] = call <4 x i4>
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> splat (half
0xH3C00))
+; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to i16
+; CHECK-LLVM: ret i16 %[[#Cast]]
+
+define spir_func i16 @hf16_fp4e2m1_16() {
+entry:
+ %0 = call i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half>
<half 1.0, half 1.0, half 1.0, half 1.0>)
+ ret i16 %0
+}
+
+declare dso_local spir_func i16
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half>)
+
+; To packed in 64-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_64]] [[#]]
+; CHECK-SPIRV: FConvert [[#E2M1Vec16Ty]] [[#Conv:]] [[#HFloat16Vec16Const]]
+; CHECK-SPIRV: Bitcast [[#Int64Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: hf16_fp4e2m1_64
+; CHECK-LLVM: %[[#Call:]] = call <16 x i4>
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half> splat (half
0xH3C00))
+; CHECK-LLVM: %[[#Cast:]] = bitcast <16 x i4> %[[#Call]] to i64
+; CHECK-LLVM: ret i64 %[[#Cast]]
+
+define spir_func i64 @hf16_fp4e2m1_64() {
+entry:
+ %0 = call i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half>
<half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half
1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half
1.0>)
+ ret i64 %0
+}
+
+declare dso_local spir_func i64
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half>)
+
+; To packed in vector of 8-bit integers
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_vec2xi8]] [[#]]
+; CHECK-SPIRV: FConvert [[#E2M1Vec4Ty]] [[#Conv:]] [[#HFloat16Vec4Const]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec2Ty]] [[#Cast:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast]]
+
+; CHECK-LLVM-LABEL: hf16_fp4e2m1_vec2xi8
+; CHECK-LLVM: %[[#Call:]] = call <4 x i4>
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> splat (half
0xH3C00))
+; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to <2 x i8>
+; CHECK-LLVM: ret <2 x i8> %[[#Cast]]
+
+define spir_func <2 x i8> @hf16_fp4e2m1_vec2xi8() {
+entry:
+ %0 = call <2 x i8> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELKDv4_Dh(<4 x
half> <half 1.0, half 1.0, half 1.0, half 1.0>)
+ ret <2 x i8> %0
+}
+
+declare dso_local spir_func <2 x i8>
@_Z38__builtin_spirv_ConvertFP16ToE2M1INTELKDv4_Dh(<4 x half>)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_int4/conversions_packed.ll
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_int4/conversions_packed.ll
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_int4/conversions_packed.ll
2026-03-11 13:48:51.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_int4/conversions_packed.ll
2026-04-30 17:43:46.000000000 +0200
@@ -5,9 +5,15 @@
; 1. from packed Int4 to ... :
; a. packed in 32-bit
; b. packed in 8-bit
+; c. packed in 16-bit
+; d. packed in 64-bit
+; e. packed in vector of 8-bit integers
; 2. to packed Int4 from ... :
; a. packed in 32-bit
; b. packed in 8-bit
+; c. packed in 16-bit
+; d. packed in 64-bit
+; e. packed in vector of 8-bit integers
; RUN: llvm-as %s -o %t.bc
; RUN: llvm-spirv %t.bc -o %t.spv
--spirv-ext=+SPV_EXT_float8,+SPV_INTEL_int4,+SPV_KHR_bfloat16
@@ -28,29 +34,50 @@
; CHECK-SPIRV-DAG: Name [[#int4_e4m3_8:]] "int4_e4m3_8"
; CHECK-SPIRV-DAG: Name [[#hf16_int4_32:]] "hf16_int4_32"
; CHECK-SPIRV-DAG: Name [[#hf16_int4_8:]] "hf16_int4_8"
+; CHECK-SPIRV-DAG: Name [[#int4_e4m3_16:]] "int4_e4m3_16"
+; CHECK-SPIRV-DAG: Name [[#int4_e4m3_64:]] "int4_e4m3_64"
+; CHECK-SPIRV-DAG: Name [[#int4_e4m3_vec2xi8:]] "int4_e4m3_vec2xi8"
+; CHECK-SPIRV-DAG: Name [[#hf16_int4_16:]] "hf16_int4_16"
+; CHECK-SPIRV-DAG: Name [[#hf16_int4_64:]] "hf16_int4_64"
+; CHECK-SPIRV-DAG: Name [[#hf16_int4_vec2xi8:]] "hf16_int4_vec2xi8"
; CHECK-SPIRV-DAG: TypeInt [[#Int32Ty:]] 32 0
; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#Int32Const:]] 1
; CHECK-SPIRV-DAG: TypeInt [[#Int8Ty:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int16Ty:]] 16 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int64Ty:]] 64 0
; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec8Ty:]] [[#Int8Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec2Ty:]] [[#Int8Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec4Ty:]] [[#Int8Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#Int8Vec16Ty:]] [[#Int8Ty]] 16
; CHECK-SPIRV-DAG: Constant [[#Int8Ty]] [[#Int8Const:]] 1
+; CHECK-SPIRV-DAG: Constant [[#Int16Ty]] [[#Int16Const:]] 1
+; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#Int64Const:]] 1
+; CHECK-SPIRV-DAG: ConstantComposite [[#Int8Vec2Ty]] [[#Int8Vec2Const:]]
[[#Int8Const]] [[#Int8Const]]
; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0
; CHECK-SPIRV-DAG: TypeVector [[#Int4Vec8Ty:]] [[#Int4Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#Int4Vec2Ty:]] [[#Int4Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#Int4Vec4Ty:]] [[#Int4Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#Int4Vec16Ty:]] [[#Int4Ty]] 16
; CHECK-SPIRV-DAG: TypeFloat [[#Float8E4M3Ty:]] 8 4214
; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec8Ty:]] [[#Float8E4M3Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec2Ty:]] [[#Float8E4M3Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec4Ty:]] [[#Float8E4M3Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#Float8E4M3Vec16Ty:]] [[#Float8E4M3Ty]] 16
; CHECK-SPIRV-DAG: TypeFloat [[#HFloat16Ty:]] 16 {{$}}
; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec8Ty:]] [[#HFloat16Ty]] 8
; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec2Ty:]] [[#HFloat16Ty]] 2
+; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec4Ty:]] [[#HFloat16Ty]] 4
+; CHECK-SPIRV-DAG: TypeVector [[#HFloat16Vec16Ty:]] [[#HFloat16Ty]] 16
; CHECK-SPIRV-DAG: Constant [[#HFloat16Ty]] [[#HFloat16Const:]] 15360
; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec8Ty]]
[[#HFloat16Vec8Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]]
; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec2Ty]]
[[#HFloat16Vec2Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
+; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec4Ty]]
[[#HFloat16Vec4Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]]
+; CHECK-SPIRV-DAG: ConstantComposite [[#HFloat16Vec16Ty]]
[[#HFloat16Vec16Const:]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]] [[#HFloat16Const]]
[[#HFloat16Const]] [[#HFloat16Const]]
target datalayout =
"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
target triple = "spir-unknown-unknown"
@@ -136,3 +163,126 @@
}
declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToInt4INTELc(<2
x half>)
+
+; Packed in 16-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#int4_e4m3_16]] [[#]]
+; CHECK-SPIRV: Bitcast [[#Int4Vec4Ty]] [[#Cast1:]] [[#Int16Const]]
+; CHECK-SPIRV: ConvertSToF [[#Float8E4M3Vec4Ty]] [[#Conv:]] [[#Cast1]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec4Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: int4_e4m3_16
+; CHECK-LLVM: %[[#Cast:]] = bitcast i16 1 to <4 x i4>
+; CHECK-LLVM: %[[#Call:]] = call <4 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]])
+; CHECK-LLVM: ret <4 x i8> %[[#Call]]
+
+define spir_func <4 x i8> @int4_e4m3_16() {
+entry:
+ %0 = call spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELs(i16 1)
+ ret <4 x i8> %0
+}
+
+declare dso_local spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELs(i16)
+
+; Packed in 64-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#int4_e4m3_64]] [[#]]
+; CHECK-SPIRV: Bitcast [[#Int4Vec16Ty]] [[#Cast1:]] [[#Int64Const]]
+; CHECK-SPIRV: ConvertSToF [[#Float8E4M3Vec16Ty]] [[#Conv:]] [[#Cast1]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec16Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: int4_e4m3_64
+; CHECK-LLVM: %[[#Cast:]] = bitcast i64 1 to <16 x i4>
+; CHECK-LLVM: %[[#Call:]] = call <16 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELDv16_i(<16 x i4> %[[#Cast]])
+; CHECK-LLVM: ret <16 x i8> %[[#Call]]
+
+define spir_func <16 x i8> @int4_e4m3_64() {
+entry:
+ %0 = call spir_func <16 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELl(i64 1)
+ ret <16 x i8> %0
+}
+
+declare dso_local spir_func <16 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELl(i64)
+
+; Packed in vector of 8-bit integers
+
+; CHECK-SPIRV: Function [[#]] [[#int4_e4m3_vec2xi8]] [[#]]
+; CHECK-SPIRV: Bitcast [[#Int4Vec4Ty]] [[#Cast1:]] [[#Int8Vec2Const]]
+; CHECK-SPIRV: ConvertSToF [[#Float8E4M3Vec4Ty]] [[#Conv:]] [[#Cast1]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec4Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: int4_e4m3_vec2xi8
+; CHECK-LLVM: %[[#Cast:]] = bitcast <2 x i8> splat (i8 1) to <4 x i4>
+; CHECK-LLVM: %[[#Call:]] = call <4 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]])
+; CHECK-LLVM: ret <4 x i8> %[[#Call]]
+
+define spir_func <4 x i8> @int4_e4m3_vec2xi8() {
+entry:
+ %0 = call spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELDv4_i(<2 x i8> <i8 1, i8 1>)
+ ret <4 x i8> %0
+}
+
+declare dso_local spir_func <4 x i8>
@_Z38__builtin_spirv_ConvertInt4ToE4M3INTELDv4_i(<2 x i8>)
+
+; To packed in 16-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_int4_16]] [[#]]
+; CHECK-SPIRV: ConvertFToS [[#Int4Vec4Ty]] [[#Conv:]] [[#HFloat16Vec4Const]]
+; CHECK-SPIRV: Bitcast [[#Int16Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: hf16_int4_16
+; CHECK-LLVM: %[[#Call:]] = call <4 x i4>
@_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv4_Dh(<4 x half> splat (half
0xH3C00))
+; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to i16
+; CHECK-LLVM: ret i16 %[[#Cast]]
+
+define spir_func i16 @hf16_int4_16() {
+entry:
+ %0 = call i16 @_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv4_Dh(<4 x half>
<half 1.0, half 1.0, half 1.0, half 1.0>)
+ ret i16 %0
+}
+
+declare dso_local spir_func i16
@_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv4_Dh(<4 x half>)
+
+; To packed in 64-bit integer
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_int4_64]] [[#]]
+; CHECK-SPIRV: ConvertFToS [[#Int4Vec16Ty]] [[#Conv:]] [[#HFloat16Vec16Const]]
+; CHECK-SPIRV: Bitcast [[#Int64Ty]] [[#Cast2:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast2]]
+
+; CHECK-LLVM-LABEL: hf16_int4_64
+; CHECK-LLVM: %[[#Call:]] = call <16 x i4>
@_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv16_Dh(<16 x half> splat (half
0xH3C00))
+; CHECK-LLVM: %[[#Cast:]] = bitcast <16 x i4> %[[#Call]] to i64
+; CHECK-LLVM: ret i64 %[[#Cast]]
+
+define spir_func i64 @hf16_int4_64() {
+entry:
+ %0 = call i64 @_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv16_Dh(<16 x half>
<half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half
1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half
1.0>)
+ ret i64 %0
+}
+
+declare dso_local spir_func i64
@_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv16_Dh(<16 x half>)
+
+; To packed in vector of 8-bit integers
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_int4_vec2xi8]] [[#]]
+; CHECK-SPIRV: ConvertFToS [[#Int4Vec4Ty]] [[#Conv:]] [[#HFloat16Vec4Const]]
+; CHECK-SPIRV: Bitcast [[#Int8Vec2Ty]] [[#Cast:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast]]
+
+; CHECK-LLVM-LABEL: hf16_int4_vec2xi8
+; CHECK-LLVM: %[[#Call:]] = call <4 x i4>
@_Z38__builtin_spirv_ConvertFP16ToInt4INTELDv4_Dh(<4 x half> splat (half
0xH3C00))
+; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to <2 x i8>
+; CHECK-LLVM: ret <2 x i8> %[[#Cast]]
+
+define spir_func <2 x i8> @hf16_int4_vec2xi8() {
+entry:
+ %0 = call <2 x i8> @_Z38__builtin_spirv_ConvertFP16ToInt4INTELKDv4_Dh(<4 x
half> <half 1.0, half 1.0, half 1.0, half 1.0>)
+ ret <2 x i8> %0
+}
+
+declare dso_local spir_func <2 x i8>
@_Z38__builtin_spirv_ConvertFP16ToInt4INTELKDv4_Dh(<4 x half>)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_elem_type.spt
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_elem_type.spt
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_elem_type.spt
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_elem_type.spt
2026-04-30 17:43:46.000000000 +0200
@@ -0,0 +1,30 @@
+; RUN: not llvm-spirv %s -to-binary -o %t.spv 2>&1 | FileCheck %s
+
+; CHECK: InvalidInstruction: Can't translate llvm instruction:
+; CHECK-NEXT: OpSubgroupBlockPrefetchINTEL
+; CHECK-NEXT: Ptr must point to a scalar integer type
+
+119734787 65536 393230 11 0
+2 Capability Addresses
+2 Capability Kernel
+2 Capability SubgroupBufferPrefetchINTEL
+10 Extension "SPV_INTEL_subgroup_buffer_prefetch"
+5 ExtInstImport 1 "OpenCL.std"
+3 MemoryModel 2 2
+5 EntryPoint 6 7 "test"
+3 Source 4 100000
+3 TypeFloat 3 32
+4 TypeInt 5 32 0
+2 TypeVoid 2
+4 TypePointer 4 5 3
+5 TypeFunction 6 2 4 5
+
+5 Function 2 7 0 6
+3 FunctionParameter 4 8
+3 FunctionParameter 5 9
+
+2 Label 10
+3 SubgroupBlockPrefetchINTEL 8 9
+1 Return
+
+1 FunctionEnd
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_numbytes_type.spt
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_numbytes_type.spt
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_numbytes_type.spt
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_numbytes_type.spt
2026-04-30 17:43:46.000000000 +0200
@@ -0,0 +1,32 @@
+; RUN: not llvm-spirv %s -to-binary -o %t.spv 2>&1 | FileCheck %s
+
+; CHECK: InvalidInstruction: Can't translate llvm instruction:
+; CHECK-NEXT: OpSubgroupBlockPrefetchINTEL
+; CHECK-NEXT: NumBytes must be a 32-bit integer scalar
+
+119734787 65536 393230 11 0
+2 Capability Addresses
+2 Capability Kernel
+2 Capability Int8
+2 Capability Int64
+2 Capability SubgroupBufferPrefetchINTEL
+10 Extension "SPV_INTEL_subgroup_buffer_prefetch"
+5 ExtInstImport 1 "OpenCL.std"
+3 MemoryModel 2 2
+5 EntryPoint 6 7 "test"
+3 Source 4 100000
+4 TypeInt 3 8 0
+4 TypeInt 5 64 0
+2 TypeVoid 2
+4 TypePointer 4 5 3
+5 TypeFunction 6 2 4 5
+
+5 Function 2 7 0 6
+3 FunctionParameter 4 8
+3 FunctionParameter 5 9
+
+2 Label 10
+3 SubgroupBlockPrefetchINTEL 8 9
+1 Return
+
+1 FunctionEnd
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_storage_class.spt
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_storage_class.spt
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_storage_class.spt
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/negative_invalid_storage_class.spt
2026-04-30 17:43:46.000000000 +0200
@@ -0,0 +1,31 @@
+; RUN: not llvm-spirv %s -to-binary -o %t.spv 2>&1 | FileCheck %s
+
+; CHECK: InvalidInstruction: Can't translate llvm instruction:
+; CHECK-NEXT: OpSubgroupBlockPrefetchINTEL
+; CHECK-NEXT: Ptr must be in CrossWorkgroup storage class
+
+119734787 65536 393230 11 0
+2 Capability Addresses
+2 Capability Kernel
+2 Capability Int8
+2 Capability SubgroupBufferPrefetchINTEL
+10 Extension "SPV_INTEL_subgroup_buffer_prefetch"
+5 ExtInstImport 1 "OpenCL.std"
+3 MemoryModel 2 2
+5 EntryPoint 6 7 "test"
+3 Source 4 100000
+4 TypeInt 3 8 0
+4 TypeInt 5 32 0
+2 TypeVoid 2
+4 TypePointer 4 7 3
+5 TypeFunction 6 2 4 5
+
+5 Function 2 7 0 6
+3 FunctionParameter 4 8
+3 FunctionParameter 5 9
+
+2 Label 10
+3 SubgroupBlockPrefetchINTEL 8 9
+1 Return
+
+1 FunctionEnd
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch.ll
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch.ll
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch.ll
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch.ll
2026-04-30 17:43:46.000000000 +0200
@@ -0,0 +1,45 @@
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_subgroup_buffer_prefetch
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv %t.spv --to-text -o - | FileCheck %s
--check-prefixes=CHECK-SPIRV,CHECK-SPIRV-TYPED-PTRS
+; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o - | llvm-dis |
FileCheck %s --check-prefix=CHECK-LLVM
+
+; RUN: llvm-spirv %s -o %t.spv
--spirv-ext=+SPV_INTEL_subgroup_buffer_prefetch,+SPV_KHR_untyped_pointers
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv %t.spv --to-text -o -| FileCheck %s
--check-prefixes=CHECK-SPIRV,CHECK-SPIRV-UNTYPED-PTRS
+; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o - | llvm-dis |
FileCheck %s --check-prefix=CHECK-LLVM
+
+; RUN: not llvm-spirv %s -o /dev/null 2>&1 | FileCheck %s
--check-prefix=CHECK-ERROR
+
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V
extension:
+; CHECK-ERROR-NEXT: SPV_INTEL_subgroup_buffer_prefetch
+
+target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+; CHECK-SPIRV-DAG: Capability SubgroupBufferPrefetchINTEL
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_subgroup_buffer_prefetch"
+; CHECK-SPIRV-UNTYPED-PTRS-DAG: Capability UntypedPointersKHR
+; CHECK-SPIRV-UNTYPED-PTRS-DAG: Extension "SPV_KHR_untyped_pointers"
+; CHECK-SPIRV-DAG: TypeInt [[#Int8Ty:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int32Ty:]] 32 0
+; CHECK-SPIRV-TYPED-PTRS-DAG: TypePointer [[#GlbPtrTy:]] 5 [[#Int8Ty]]
+; CHECK-SPIRV-UNTYPED-PTRS-DAG: TypeUntypedPointerKHR [[#GlbPtrTy:]] 5
+
+; CHECK-SPIRV: FunctionParameter [[#GlbPtrTy]] [[#Ptr:]]
+; CHECK-SPIRV: FunctionParameter [[#Int32Ty]] [[#NumBytes:]]
+; CHECK-SPIRV: SubgroupBlockPrefetchINTEL [[#Ptr]] [[#NumBytes]]
+
+; CHECK-LLVM: call spir_func void
@_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khj(ptr addrspace(1) %{{.*}}, i32
%{{.*}})
+
+define spir_kernel void @test(ptr addrspace(1) %ptr, i32 %num_bytes) {
+entry:
+ call spir_func void @_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khj(ptr
addrspace(1) %ptr, i32 %num_bytes)
+ ret void
+}
+
+declare spir_func void @_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khj(ptr
addrspace(1), i32)
+
+!opencl.spir.version = !{!0}
+!spirv.Source = !{!1}
+!0 = !{i32 1, i32 0}
+!1 = !{i32 4, i32 100000}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_mem_operands.ll
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_mem_operands.ll
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_mem_operands.ll
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_mem_operands.ll
2026-04-30 17:43:46.000000000 +0200
@@ -0,0 +1,36 @@
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_subgroup_buffer_prefetch
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv %t.spv --to-text -o - | FileCheck %s
--check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o - | llvm-dis |
FileCheck %s --check-prefix=CHECK-LLVM
+
+; OpSubgroupBlockPrefetchINTEL accepts an optional Memory Operands bitmask
+; as a third operand after the required Ptr and NumBytes.
+; Test Prefetch with Nontemporal memory operand (0x4).
+
+; CHECK-SPIRV-DAG: Capability SubgroupBufferPrefetchINTEL
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_subgroup_buffer_prefetch"
+; CHECK-SPIRV-DAG: TypeInt [[#Int8Ty:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int32Ty:]] 32 0
+; CHECK-SPIRV-DAG: TypePointer [[#GlbPtrTy:]] 5 [[#Int8Ty]]
+
+; CHECK-SPIRV: FunctionParameter [[#GlbPtrTy]] [[#Ptr:]]
+; CHECK-SPIRV: FunctionParameter [[#Int32Ty]] [[#NumBytes:]]
+; CHECK-SPIRV: SubgroupBlockPrefetchINTEL [[#Ptr]] [[#NumBytes]] 4
+
+; CHECK-LLVM: call spir_func void
@_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khjj(ptr addrspace(1) %{{.*}}, i32
%{{.*}}, i32 4)
+
+target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+define spir_kernel void @test_nontemporal(ptr addrspace(1) %ptr, i32
%num_bytes) {
+entry:
+ call spir_func void @_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khjj(ptr
addrspace(1) %ptr, i32 %num_bytes, i32 4)
+ ret void
+}
+
+declare spir_func void @_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khjj(ptr
addrspace(1), i32, i32)
+
+!opencl.spir.version = !{!0}
+!spirv.Source = !{!1}
+!0 = !{i32 1, i32 0}
+!1 = !{i32 4, i32 100000}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_with_cache_controls.ll
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_with_cache_controls.ll
---
old/SPIRV-LLVM-Translator-22.1.1/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_with_cache_controls.ll
1970-01-01 01:00:00.000000000 +0100
+++
new/SPIRV-LLVM-Translator-22.1.2/test/extensions/INTEL/SPV_INTEL_subgroup_buffer_prefetch/subgroup_buffer_prefetch_with_cache_controls.ll
2026-04-30 17:43:46.000000000 +0200
@@ -0,0 +1,48 @@
+; RUN: llvm-spirv %s -o %t.spv
--spirv-ext=+SPV_INTEL_subgroup_buffer_prefetch,+SPV_INTEL_cache_controls
+; RUN: llvm-spirv %t.spv --to-text -o - | FileCheck %s
--check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o - | llvm-dis |
FileCheck %s --check-prefix=CHECK-LLVM
+
+; SPV_INTEL_subgroup_buffer_prefetch interaction with SPV_INTEL_cache_controls:
+; CacheControlLoadINTEL decoration may be used to control which cache levels
+; the data will be prefetched into.
+
+target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
[email protected] = private unnamed_addr addrspace(1) constant [7 x i8] c"file.h\00",
section "llvm.metadata"
+; {6442:"0,1"} = {CacheControlLoadINTEL_Token:"CacheLevel,CacheControl"} = L1
Cached
[email protected] = private unnamed_addr addrspace(1) constant [13 x i8]
c"{6442:\220,1\22}\00", section "llvm.metadata"
+
+; CHECK-SPIRV-DAG: Capability SubgroupBufferPrefetchINTEL
+; CHECK-SPIRV-DAG: Capability CacheControlsINTEL
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_subgroup_buffer_prefetch"
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_cache_controls"
+; CHECK-SPIRV-DAG: TypeInt [[#Int8Ty:]] 8 0
+; CHECK-SPIRV-DAG: TypeInt [[#Int32Ty:]] 32 0
+; CHECK-SPIRV-DAG: TypePointer [[#GlbPtrTy:]] 5 [[#Int8Ty]]
+; CHECK-SPIRV-DAG: Decorate [[#Ptr:]] CacheControlLoadINTEL 0 1
+
+; CHECK-SPIRV: FunctionParameter [[#GlbPtrTy]] [[#Ptr]]
+; CHECK-SPIRV: FunctionParameter [[#Int32Ty]] [[#NumBytes:]]
+; CHECK-SPIRV: SubgroupBlockPrefetchINTEL [[#Ptr]] [[#NumBytes]]
+
+; CHECK-LLVM: spirv.ParameterDecorations ![[#ParamDecs:]]
+; CHECK-LLVM: call spir_func void
@_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khj
+; CHECK-LLVM: ![[#ParamDecs]] = !{![[#FirstParam:]], ![[#]]}
+; CHECK-LLVM: ![[#FirstParam]] = !{![[#DecoNode:]]}
+; CHECK-LLVM: ![[#DecoNode]] = !{i32 6442, i32 0, i32 1}
+
+define spir_kernel void @test(ptr addrspace(1) %ptr, i32 %num_bytes) {
+entry:
+ %annotated = call ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr
addrspace(1) %ptr, ptr addrspace(1) @.str.cc, ptr addrspace(1) @.str.1, i32 0,
ptr addrspace(1) null)
+ call spir_func void @_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khj(ptr
addrspace(1) %annotated, i32 %num_bytes)
+ ret void
+}
+
+declare ptr addrspace(1) @llvm.ptr.annotation.p1.p1(ptr addrspace(1), ptr
addrspace(1), ptr addrspace(1), i32, ptr addrspace(1))
+declare spir_func void @_Z34__spirv_SubgroupBlockPrefetchINTELPU3AS1Khj(ptr
addrspace(1), i32)
+
+!opencl.spir.version = !{!0}
+!spirv.Source = !{!1}
+!0 = !{i32 1, i32 0}
+!1 = !{i32 4, i32 100000}
