Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package rasdaemon for openSUSE:Factory checked in at 2026-07-03 16:10:37 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/rasdaemon (Old) and /work/SRC/openSUSE:Factory/.rasdaemon.new.1982 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "rasdaemon" Fri Jul 3 16:10:37 2026 rev:29 rq:1363634 version:0.8.5+git0.769593b Changes: -------- --- /work/SRC/openSUSE:Factory/rasdaemon/rasdaemon.changes 2026-03-09 16:31:42.367169257 +0100 +++ /work/SRC/openSUSE:Factory/.rasdaemon.new.1982/rasdaemon.changes 2026-07-03 16:11:13.610412534 +0200 @@ -1,0 +2,18 @@ +Fri Jul 03 07:57:12 UTC 2026 - Thomas Renninger <[email protected]> + +- Update to version 0.8.5+git0.769593b: + * rasdaemon: bump to version 0.8.5 + * Add a workflow to drop waiting new version label + * ras-page-isolation.c: cleanup a warning + * ras-non-standard-handler: remove an ugly goto + * ras-mc-ctl: report NVIDIA Vera SQLite events + * rasdaemon: add NVIDIA Vera non-standard CPER decoder + * rasdaemon: guard NULL vendor decoders without sqlite + * rasdaemon: Add Intel Diamond Rapids MCE decoder support + * Fix unsafe strcpy in non-standard-nvidia.c + * labels: Add ASRock WRX80 Creator R2.0 DIMM mapping + * ras-mc-ctl: Fix invalid column in signal events query + * mc_event_trigger: Fix reference to mc_event_trigger.local + * Update README.md ans SECURITY.md + +------------------------------------------------------------------- Old: ---- rasdaemon-0.8.4+git33.4f1f08a.obscpio New: ---- rasdaemon-0.8.5+git0.769593b.obscpio ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ rasdaemon.spec ++++++ --- /var/tmp/diff_new_pack.KAXNul/_old 2026-07-03 16:11:14.998460674 +0200 +++ /var/tmp/diff_new_pack.KAXNul/_new 2026-07-03 16:11:15.002460814 +0200 @@ -17,7 +17,7 @@ Name: rasdaemon -Version: 0.8.4+git33.4f1f08a +Version: 0.8.5+git0.769593b Release: 0 Summary: Utility to receive RAS error tracings License: GPL-2.0-only ++++++ _servicedata ++++++ --- /var/tmp/diff_new_pack.KAXNul/_old 2026-07-03 16:11:15.070463172 +0200 +++ /var/tmp/diff_new_pack.KAXNul/_new 2026-07-03 16:11:15.074463310 +0200 @@ -1,6 +1,6 @@ <servicedata> <service name="tar_scm"> <param name="url">git://git.infradead.org/users/mchehab/rasdaemon.git</param> - <param name="changesrevision">4f1f08a2913a836587eb47ad283dd7246f15b5ab</param></service></servicedata> + <param name="changesrevision">769593be915b4f00a9a7d56569df99bc0cff249a</param></service></servicedata> (No newline at EOF) ++++++ rasdaemon-0.8.4+git33.4f1f08a.obscpio -> rasdaemon-0.8.5+git0.769593b.obscpio ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/.github/workflows/auto-remove-waiting-label.yml new/rasdaemon-0.8.5+git0.769593b/.github/workflows/auto-remove-waiting-label.yml --- old/rasdaemon-0.8.4+git33.4f1f08a/.github/workflows/auto-remove-waiting-label.yml 1970-01-01 01:00:00.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/.github/workflows/auto-remove-waiting-label.yml 2026-06-26 12:00:07.000000000 +0200 @@ -0,0 +1,17 @@ +name: Auto-remove "waiting new revision" label on PR update + +on: + pull_request: + types: [synchronize] + +permissions: + pull-requests: write + +jobs: + remove-label: + runs-on: ubuntu-latest + steps: + - name: Remove label on PR update + uses: actions-ecosystem/action-remove-labels@v1 + with: + labels: 'waiting new revision' diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/ChangeLog new/rasdaemon-0.8.5+git0.769593b/ChangeLog --- old/rasdaemon-0.8.4+git33.4f1f08a/ChangeLog 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/ChangeLog 2026-06-26 12:00:07.000000000 +0200 @@ -1,3 +1,23 @@ +2026-06-26 Mauro Carvalho Chehab <[email protected]> + - Version 0.8.5 + + * rasdaemon: Add NVIDIA non-standard CPER decoder (Vera and Grace) + * rasdaemon: Add Intel Diamond Rapids, Granite Rapids, Sierra Forest, and Clearwater Forest support + * rasdaemon: Add Zhaoxin CPUs support for MCE record events + * rasdaemon: Fix uuid_le() buffer size calculation and SQLite API return code checks + * rasdaemon: Allow built-in or modules EDAC in status checks + * rasdaemon: Add RERI handler implementation + * ras-mc-ctl: Consolidate error counts by DIMM label + * ras-mc-ctl: Fix signal events query column + * ras-mc-ctl: Fix mc_event_trigger.local reference + * ras-mc-ctl: Correct --error-count alignment output + * ras-events: Fix event file endianness handling + * ras-aer-handler: Add support for AER triggers + * tracing: Address deprecated /sys/kernel/debug/tracing path + * ras-page-isolation.c: Clean up compiler warning + * types.c: Add missing newline at end of file + * Documentation: Update README.md and SECURITY.md + 2025-11-20 Mauro Carvalho Chehab <[email protected]> - Version 0.8.4 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/Makefile.am new/rasdaemon-0.8.5+git0.769593b/Makefile.am --- old/rasdaemon-0.8.4+git33.4f1f08a/Makefile.am 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/Makefile.am 2026-06-26 12:00:07.000000000 +0200 @@ -136,6 +136,7 @@ rasdaemon_SOURCES += mce-intel.c rasdaemon_SOURCES += mce-intel-broadwell-de.c rasdaemon_SOURCES += mce-intel-broadwell-epex.c + rasdaemon_SOURCES += mce-intel-diamond.c rasdaemon_SOURCES += mce-intel-dunnington.c rasdaemon_SOURCES += mce-intel-haswell.c rasdaemon_SOURCES += mce-intel-granite.c diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/README.md new/rasdaemon-0.8.5+git0.769593b/README.md --- old/rasdaemon-0.8.4+git33.4f1f08a/README.md 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/README.md 2026-06-26 12:00:07.000000000 +0200 @@ -16,6 +16,16 @@ Tarballs for each release can be found at: - <http://www.infradead.org/~mchehab/rasdaemon/> +Intended Use +============ + +This project provides general-purpose software components intended primarily +for integration, development, research, and infrastructure use by technical +users. + +The project is not offered as a consumer-facing online service or +managed platform. + GOALS ===== diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/SECURITY.md new/rasdaemon-0.8.5+git0.769593b/SECURITY.md --- old/rasdaemon-0.8.4+git33.4f1f08a/SECURITY.md 1970-01-01 01:00:00.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/SECURITY.md 2026-06-26 12:00:07.000000000 +0200 @@ -0,0 +1,72 @@ +Security and Responsible Disclosure +=================================== + +Reporting Security Issues +------------------------- + +Security issues may be reported to: + +mchehab at kernel.org + +Reports should include sufficient technical detail to allow reproduction +and assessment of the issue. + +Please avoid public disclosure of suspected vulnerabilities until the +issue has been reviewed where possible. + +Project Role and Scope +---------------------- + +This project provides upstream source code and software artifacts for +general-purpose use. + +The maintainers distribute the software as development artifacts and +documentation only. The maintainers do not operate production +deployments, hosted services, or downstream distributions of this +software. + +Security Maintenance Model +-------------------------- + +Security review, patch development, and vulnerability remediation are +performed on a best-effort basis and may depend on community +contributions. + +The maintainers do not guarantee response times, security updates, or +continued maintenance of any particular version. + +Responsibilities of Distributors and Operators +---------------------------------------------- + +Entities that package, distribute, integrate, or deploy this software +are responsible for ensuring the security and compliance of their +deployments. + +This includes, but is not limited to: + +- monitoring for security advisories +- applying or backporting security patches +- validating fixes in their environments +- distributing updates to their users +- complying with applicable regulatory or operational requirements + +Distributors and operators should maintain their own security response +processes appropriate to their deployment environments. + +Supported Versions +------------------ + +Security fixes may be applied to actively maintained versions of the +project at the discretion of the maintainers. + +Versions outside active development may not receive updates. + +No Operational Control +---------------------- + +Because this project is distributed as standalone software and source +code, the maintainers do not control how the software is compiled, +packaged, deployed, or operated by third parties. + +Responsibility for the security and maintenance of deployed systems +remains with the parties operating or distributing the software. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/configure.ac new/rasdaemon-0.8.5+git0.769593b/configure.ac --- old/rasdaemon-0.8.4+git33.4f1f08a/configure.ac 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/configure.ac 2026-06-26 12:00:07.000000000 +0200 @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -AC_INIT([RASdaemon],[0.8.4]) +AC_INIT([RASdaemon],[0.8.5]) AM_SILENT_RULES([yes]) AC_CANONICAL_TARGET AC_CONFIG_MACRO_DIR([m4]) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/contrib/mc_event_trigger new/rasdaemon-0.8.5+git0.769593b/contrib/mc_event_trigger --- old/rasdaemon-0.8.4+git33.4f1f08a/contrib/mc_event_trigger 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/contrib/mc_event_trigger 2026-06-26 12:00:07.000000000 +0200 @@ -21,6 +21,7 @@ # DRIVER_DETAIL Other driver-specific detail about the error # -[ -x ./mc_event_trigger.local ] && . ./mc_event_trigger.local +TRIGGER_DIR=$(dirname "$0") +[ -x "$TRIGGER_DIR/mc_event_trigger.local" ] && . "$TRIGGER_DIR/mc_event_trigger.local" exit 0 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/labels/asrock new/rasdaemon-0.8.5+git0.769593b/labels/asrock --- old/rasdaemon-0.8.4+git33.4f1f08a/labels/asrock 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/labels/asrock 2026-06-26 12:00:07.000000000 +0200 @@ -43,6 +43,16 @@ DIMM_E0: 0.0.9, 0.1.9; DIMM_G0: 0.0.6, 0.1.6; + Model: WRX80 Creator R2.0 + DDR4_A1: 0.0.0, 0.1.0, 0.2.0, 0.3.0; + DDR4_B1: 0.0.1, 0.1.1, 0.2.1, 0.3.1; + DDR4_C1: 0.0.3, 0.1.3, 0.2.3, 0.3.3; + DDR4_D1: 0.0.2, 0.1.2, 0.2.2, 0.3.2; + DDR4_E1: 0.0.6, 0.1.6, 0.2.6, 0.3.6; + DDR4_F1: 0.0.7, 0.1.7, 0.2.7, 0.3.7; + DDR4_G1: 0.0.5, 0.1.5, 0.2.5, 0.3.5; + DDR4_H1: 0.0.4, 0.1.4, 0.2.4, 0.3.4; + Vendor: ASRockRack Model: X399D8A-2T DIMM_A1: 0.2.0, 0.3.0; DIMM_A2: 0.0.0, 0.1.0; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/mce-intel-diamond.c new/rasdaemon-0.8.5+git0.769593b/mce-intel-diamond.c --- old/rasdaemon-0.8.4+git33.4f1f08a/mce-intel-diamond.c 1970-01-01 01:00:00.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/mce-intel-diamond.c 2026-06-26 12:00:07.000000000 +0200 @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * The code below came from Qiuxu Zhuo's mcelog code, + * released under GNU Public General License, v2 + * + * Copyright (C) 2025 Intel Corporation + * Decode Intel Diamond Rapids specific machine check errors. + */ + +#include <inttypes.h> +#include <stdio.h> +#include <string.h> + +#include "bitfield.h" +#include "ras-mce-handler.h" + +static char *cbb_punit_0[] = { + [0x01] = "CR4_MCE_CLEAR: MCE when CR4.MCE is clear", + [0x02] = "MCE_MCIP_SET: MCE when MCIP bit is set", + [0x03] = "MCE_UNDER_WFS: MCE under WPS", + [0x04] = "MCE_LT_HANDSHAKE: Unrecoverable error during security flow execution", + [0x05] = "TRIPLE_FAULT: SW triple fault shutdown", + [0x06] = "VMX_ABORT: VMX exit consistency check failures", + [0x07] = "RSM_CONSISTENCY_FAIL: RSM consistency check failures", + [0x08] = "SMM_PROTECTED_ENTRY_FAIL: Invalid conditions on protected mode SMM entry", + [0x09] = "UCODE_PATCH_LOAD_FAIL: Unrecoverable error during security flow execution", +}; + +static char *cbb_punit_8[] = { + [0x16] = "MCA_DVFS_COUNTER_EXPIRED", + [0x23] = "MCA_UNSUPP_RESP", + [0x25] = "MCA_FUSA_MBIST", + [0x26] = "MCA_SA_PLL_LOCKED", + [0x27] = "MCA_XTAL_FREQ_MON_ERROR", + [0x28] = "MCA_PMSB_FUSE_PULLER_ERROR", + [0x29] = "MCA_GPSB_FUSE_PULLER_ERROR", + [0x30] = "MCA_PCODE_WATCHDOG", + [0x31] = "MCA_BGR_FUSA_ERR", + [0x32] = "MCA_CORE_FIVR_ERR", + [0x33] = "MCA_D2D_FIVR_ERR", + [0x34] = "MCA_MLC_FIVR_ERR", + [0x35] = "MCA_RING_FIVR_ERR", + [0x36] = "MCA_D2D_MONF_PLL_FUSA_0", + [0x37] = "MCA_D2D_MONF_PLL_FUSA_1", + [0x38] = "MCA_TOP0_FUSA_PLL_ERR", + [0x39] = "MCA_BASE_FUSA_PLL_ERR", + [0x40] = "MCA_UCIE_RESET_BUS_STOP_ON_ERROR", + [0x41] = "MCA_RSRC_ADAPT_0_ERR", + [0x42] = "MCA_RSC_ADAPT_1_ERR", + [0x45] = "MCA_TOP1_FUSA_PLL_ERR", + [0x46] = "MCA_TOP2_FUSA_PLL_ERR", + [0x47] = "MCA_TOP3_FUSA_PLL_ERR", + [0x48] = "UC_PATCH_LOAD_ACK_ERROR", +}; + +static char *cbb_punit_12[] = { + [0x01] = "MCA_UC_IRAM_DOUBLE_ERROR", + [0x02] = "MCA_UC_DOUBLE_EXCEPTION_ERROR", + [0x03] = "MCA_UC_TELEM_SRAM_ERROR", + [0x04] = "MCA_UC_DRAM_DOUBLE_ERROR", + [0x05] = "MCA_UC_TPMI_SRAM_ERROR", +}; + +static char *cbb_punit_20[] = { + [0x01] = "MCA_FIVR_HI_YELLOW", + [0x02] = "MCA_FIVR_HI_RED", +}; + +static struct field cbb_punit0[] = { + FIELD(0, cbb_punit_0), + {} +}; + +static struct field cbb_punit8[] = { + FIELD(0, cbb_punit_8), + {} +}; + +static struct field cbb_punit12[] = { + FIELD(0, cbb_punit_12), + {} +}; + +static struct field cbb_punit20[] = { + FIELD(0, cbb_punit_20), + {} +}; + +static char *imh_punit_0[] = { + [0x02 ... 0x03] = "Power Management Unit microcontroller double-bit ECC error", + [0x08 ... 0x09] = "Power Management Unit microcontroller error", + [0x0a] = "Power Management Unit microcontroller Patch Load error", + [0x0b] = "Power Management Unit microcontroller POReqValid error", + [0x0c] = "Power Management Unit microcontroller RAM address error", + [0x0d] = "Power Management Unit microcontroller RAM access error", + [0x10] = "If MCI_MISC.MODEL_SPECIFIC_INFORMATION is set to 1, " + "indicates Pcode Watchdog Timer expired. " + "If MCI_MISC.MODEL_SPECIFIC_INFORMATION is set to 3, " + "indicates Power Management Unit TeleSRAM double-bit ECC error detected.", + [0x20] = "Power Management Agent signaled Error", + [0x30] = "Power Management Unit Microcontroller Error", + [0xa0] = "Power Management Unit HPMSRAM double-bit ECC error detected", + [0xb0] = "Power Management Unit TPMISRAM double-bit ECC error detected", +}; + +static char *imh_punit_1[] = { + [0x09] = "MCA_TSC_DOWNLOAD_TIMEOUT", + [0x0a] = "MCA_INVALID_XTALFREQ_RANGE", + [0x0b] = "MCA_GPSB_TIMEOUT", + [0x0c] = "MCA_PMSB_TIMEOUT", + [0x0d] = "MCA_CFG_ACK_TIMEOUT", + [0x23] = "MCA_PCU_SVID_ERROR", + [0x35] = "MCA_SVID_LOADLINE_INVALID", + [0x36] = "MCA_SVID_ICCMAX_INVALID", + [0x4a] = "MCA_FIVR_PD_HARDERR", + [0x4c] = "MCA_HPM_DOUBLE_BIT_ERROR_DETECTED", + [0x58] = "MCA_INVALID_MEMORY_FREQUENCY", + [0x63] = "MCA_SVID_VCCIN_PROTOCOL_ERROR", + [0x6a] = "MCA_SPPR_TIMEOUT", + [0x6f] = "MCA_INVALID_SID_ERROR", + [0x70] = "MCA_INVALID_REMOTE_LEGACY_AGENT_ERROR", + [0x71] = "MCA_INVALID_REMOTE_LT_AGENT_ERROR", + [0x7b] = "MCA_THERMAL_SENSOR_INVALID", + [0x7c] = "MCA_CXL_DEVICE_NO_CREDIT", + [0x7e] = "MCA_RECOVERABLE_DIE_THERMAL_TOO_HOT", + [0x83] = "MCA_PKGS_RECOVERABLE_RESET_PREP_ACK_TIMEOUT", +}; + +static struct field imh_punit0[] = { + FIELD(0, imh_punit_0), + {} +}; + +static struct field imh_punit1[] = { + FIELD(0, imh_punit_1), + {} +}; + +static char *upi_0[] = { + [0x00 ... 0x02] = "Internal Parity Error", + [0x05] = "Internal Parity Error", + [0x08] = "Internal Queue Overflow Error", + [0x09] = "UPI link layer buffer overflow", + [0x0a] = "Internal Queue Underflow Error", + [0x0b] = "UPI link layer buffer underflow", + [0x0c] = "Link layer or internal credit overflow", + [0x11 ... 0x12] = "Internal Queue Overflow Error", + [0x13 ... 0x14] = "Internal Queue Underflow Error", + [0x21] = "Internal Interface Error", + [0x23] = "Invalid Message", + [0x24] = "UPI Protocol Error", + [0x25] = "UPI Interleave Error", + [0x28] = "Internal Interface Error", + [0x29] = "Link integrity or initialization error", + [0x2a ... 0x2d] = "Power Management Transition Error - Timeout", + [0x30] = "Received poison when poison is disabled", + [0x31] = "Internal Interface Error", +}; + +static char *upi_2[] = { + [0x00] = "Link integrity or initialization error", + [0x03] = "Link degraded", + [0x04 ... 0x07] = "Power Management Transition Error - Timeout", +}; + +static struct field upi0[] = { + FIELD(0, upi_0), + {} +}; + +static struct field upi2[] = { + FIELD(0, upi_2), + {} +}; + +static char *mcchan_0[] = { + [0x01] = "CMI Request Address Parity Error (APPP)", + [0x02] = "CMI Wr data parity error", + [0x04] = "CMI Wr BE parity error", + [0x08] = "Transient or Correctable Error for Patrol Reads", + [0x10] = "UnCorr Patrol Scrub Error", + [0x20] = "Nontransient or Transient ectable Error for Spare Reads", + [0x40] = "UnCorr Spare Error", + [0x80] = "Transient or Correctable Error for Demand or Underfill Reads", + [0xa0] = "Uncorrectable Error for Demand or Underfill Reads", + [0xb0] = "Poisoned Read Data when Poison Disabled", + [0xc0] = "Read 2LM MetaData Error for Demand, Underfill, or Patrol/Spare", +}; + +static char *mcchan_1[] = { + [0x02] = "WDB Read ECC Error", + [0x04] = "WDB BE Read Parity Error", + [0x06] = "WDB Read Persistent ECC Error", + [0x08] = "DDR Link Fail", + [0x09] = "Illegal incoming opcode", +}; + +static char *mcchan_2[] = { + [0x00] = "DDR CAParity or WrCRC Error", + [0x40] = "Decoder structure error", +}; + +static char *mcchan_4[] = { + [0x00] = "MC internal address parity error", +}; + +static char *mcchan_8[] = { + [0x13] = "CMI Credit Oversubscription Error", + [0x14] = "CMI Total Credit Count Error", + [0x15] = "CMI Reserved Credit Pool Error", + [0x32] = "MC Internal Errors", + [0x34] = "MC Tracker RDCMP RF parity error", + [0x36] = "MC Tracker WRCMP RF parity error", +}; + +static struct field mcchan0[] = { + FIELD(0, mcchan_0), + {} +}; + +static struct field mcchan1[] = { + FIELD(0, mcchan_1), + {} +}; + +static struct field mcchan2[] = { + FIELD(0, mcchan_2), + {} +}; + +static struct field mcchan4[] = { + FIELD(0, mcchan_4), + {} +}; + +static struct field mcchan8[] = { + FIELD(0, mcchan_8), + {} +}; + +static int diamond_imh(struct mce_event *e) +{ + return (e->apicid >> 2) & 1; +} + +static void diamond_imc_misc(struct mce_event *e) +{ + uint64_t mscod = EXTRACT(e->status, 16, 31); + uint32_t column = EXTRACT(e->misc, 9, 18) << 2; + uint32_t row = EXTRACT(e->misc, 19, 36); + uint32_t bank = EXTRACT(e->misc, 37, 38); + uint32_t bankgroup = EXTRACT(e->misc, 39, 41); + uint32_t fdevice_v = EXTRACT(e->misc, 42, 42); + uint32_t fdevice = EXTRACT(e->misc, 44, 48); + uint32_t subchan = EXTRACT(e->misc, 49, 49); + uint32_t subrank = EXTRACT(e->misc, 51, 54); + uint32_t chipselect = EXTRACT(e->misc, 55, 56); + uint32_t eccmode = EXTRACT(e->misc, 58, 61); + uint32_t transient = EXTRACT(e->misc, 63, 63); + + /* For MSCOD 0800h or above, MCi_MISC[31:9] holds proprietary error information. */ + if (mscod >= 0x800) + return; + + mce_snprintf(e->error_msg, "bank: 0x%x bankgroup: 0x%x row: 0x%x column: 0x%x\n", bank, bankgroup, row, column); + mce_snprintf(e->error_msg, "chipselect: 0x%x subrank: 0x%x subchan: 0x%x\n", chipselect, subrank, subchan); + + if (transient) { + mce_snprintf(e->error_msg, "transient\n"); + return; + } + + if (fdevice_v) + mce_snprintf(e->error_msg, "failed device: 0x%x\n", fdevice); + + mce_snprintf(e->error_msg, "ecc mode: "); + switch (eccmode) { + case 1: + mce_snprintf(e->error_msg, "SDDC 128b 1LM\n"); + break; + case 2: + mce_snprintf(e->error_msg, "SDDC 125b 1LM\n"); + break; + case 3: + mce_snprintf(e->error_msg, "SDDC 125b 2LM\n"); + break; + case 4: + mce_snprintf(e->error_msg, "ADDDC 80b 1LM\n"); + break; + case 5: + mce_snprintf(e->error_msg, "ADDDC 80b 2LM\n"); + break; + case 9: + mce_snprintf(e->error_msg, "5x8 128b 1LM\n"); + break; + case 10: + mce_snprintf(e->error_msg, "5x8 125b 1LM\n"); + break; + case 11: + mce_snprintf(e->error_msg, "5x8 125b 2LM\n"); + break; + default: + mce_snprintf(e->error_msg, "Invalid/unknown ECC mode\n"); + } +} + +static void diamond_memerr_misc(struct mce_event *e, int *channel, int *dimm) +{ + /* Check this is a memory error */ + if (!test_prefix(7, e->status & 0xefff)) + return; + + if (e->bank < 19 || e->bank > 26) + return; + + channel[0] = e->bank - 19 + 8 * diamond_imh(e); +} + +void diamond_decode_model(enum cputype cputype, struct ras_events *ras, struct mce_event *e) +{ + uint64_t f, status = e->status; + int channel = -1, dimm = -1; + int imh = diamond_imh(e); + + switch (e->bank) { + case 4: + mce_snprintf(e->error_msg, "CBB Punit: "); + + if (EXTRACT(status, 0, 15) == 0x040b) { + mce_snprintf(e->error_msg, "Scan-at-Field Error\n"); + break; + } + + f = EXTRACT(status, 16, 23); + switch (EXTRACT(status, 24, 31)) { + case 0x00: + decode_bitfield(e, f, cbb_punit0); + break; + case 0x08: + decode_bitfield(e, f, cbb_punit8); + break; + case 0x0c: + decode_bitfield(e, f, cbb_punit12); + break; + case 0x14: + decode_bitfield(e, f, cbb_punit20); + break; + } + break; + case 11: + mce_snprintf(e->error_msg, "IMH%d Punit: ", imh); + + f = EXTRACT(status, 24, 31); + if (f) + decode_bitfield(e, f, imh_punit1); + else + decode_bitfield(e, EXTRACT(status, 16, 23), imh_punit0); + break; + case 18: + mce_snprintf(e->error_msg, "UPI: "); + + f = EXTRACT(status, 16, 23); + switch (EXTRACT(status, 24, 31)) { + case 0x00: + decode_bitfield(e, f, upi0); + break; + case 0x02: + decode_bitfield(e, f, upi2); + break; + } + break; + case 19 ... 26: + mce_snprintf(e->error_msg, "IMH%d MCCHAN: ", imh); + + f = EXTRACT(status, 16, 23); + switch (EXTRACT(status, 24, 31)) { + case 0x00: + decode_bitfield(e, f, mcchan0); + break; + case 0x01: + decode_bitfield(e, f, mcchan1); + break; + case 0x02: + decode_bitfield(e, f, mcchan2); + break; + case 0x04: + decode_bitfield(e, f, mcchan4); + break; + case 0x08: + decode_bitfield(e, f, mcchan8); + break; + } + + /* Decode MISC register if MISCV and OTHER_INFO[1] are both set. */ + if (EXTRACT(status, 59, 59) && EXTRACT(status, 33, 33)) + diamond_imc_misc(e); + break; + } + + /* Parse the reported channel and DIMM. */ + diamond_memerr_misc(e, &channel, &dimm); + if (channel != -1) + mce_snprintf(e->error_msg, "channel: %d", channel); + if (dimm != -1) + mce_snprintf(e->error_msg, "dimm: %d", dimm); +} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/mce-intel.c new/rasdaemon-0.8.5+git0.769593b/mce-intel.c --- old/rasdaemon-0.8.4+git33.4f1f08a/mce-intel.c 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/mce-intel.c 2026-06-26 12:00:07.000000000 +0200 @@ -421,6 +421,9 @@ case CPU_CLEARWATERFOREST: granite_decode_model(mce->cputype, ras, e); break; + case CPU_DIAMONDRAPIDS: + diamond_decode_model(mce->cputype, ras, e); + break; default: break; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/non-standard-nvidia.c new/rasdaemon-0.8.5+git0.769593b/non-standard-nvidia.c --- old/rasdaemon-0.8.4+git33.4f1f08a/non-standard-nvidia.c 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/non-standard-nvidia.c 2026-06-26 12:00:07.000000000 +0200 @@ -4,15 +4,72 @@ * Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ -#include <ctype.h> +#include <errno.h> +#include <limits.h> #include <stdio.h> #include <string.h> +#include <stdint.h> #include <time.h> #include "non-standard-nvidia.h" #include "ras-logger.h" #include "ras-non-standard-handler.h" +static void nvidia_format_timestamp(char *timestamp, size_t len) +{ + time_t now; + struct tm *tm; + + if (!timestamp || !len) + return; + + now = time(NULL); + tm = localtime(&now); + if (tm) + strftime(timestamp, len, "%Y-%m-%d %H:%M:%S %z", tm); + else + snprintf(timestamp, len, "unknown"); +} + +#ifdef HAVE_SQLITE3 + +#include <sqlite3.h> + +static int nvidia_add_vendor_table(struct ras_events *ras, + struct ras_ns_ev_decoder *ev_decoder, + const struct db_table_descriptor *table, + const char *label) +{ + int rc; + + rc = ras_mc_add_vendor_table(ras, &ev_decoder->stmt_dec_record, table); + if (rc != SQLITE_OK) + log(TERM, LOG_ERR, "Failed to create/prepare %s table: %d\n", + label, rc); + + return rc; +} + +static void nvidia_store_vendor_record(struct ras_ns_ev_decoder *ev_decoder, + const char *label) +{ + int rc; + + rc = sqlite3_step(ev_decoder->stmt_dec_record); + if (rc != SQLITE_DONE) + log(TERM, LOG_ERR, + "Failed to store %s event in database: error = %d\n", + label, rc); + + rc = sqlite3_reset(ev_decoder->stmt_dec_record); + if (rc != SQLITE_OK) + log(TERM, LOG_ERR, + "Failed to reset %s statement: error = %d\n", + label, rc); +} + +#endif /* HAVE_SQLITE3 */ + static const char * const nvidia_reg_names[] = { [NVIDIA_FIELD_SIGNATURE] = "Signature:", [NVIDIA_FIELD_ERROR_TYPE] = "Error Type:", @@ -81,9 +138,394 @@ } } -#ifdef HAVE_SQLITE3 +#define NVIDIA_VERA_MAX_CONTEXTS 16 +#define NVIDIA_VERA_VERSION 1 -#include <sqlite3.h> +static uint16_t nvidia_vera_le16(const void *p) +{ + uint16_t v; + + memcpy(&v, p, sizeof(v)); +#if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + v = __builtin_bswap16(v); +#endif + return v; +} + +static uint32_t nvidia_vera_le32(const void *p) +{ + uint32_t v; + + memcpy(&v, p, sizeof(v)); +#if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + v = __builtin_bswap32(v); +#endif + return v; +} + +static uint64_t nvidia_vera_le64(const void *p) +{ + uint64_t v; + + memcpy(&v, p, sizeof(v)); +#if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + v = __builtin_bswap64(v); +#endif + return v; +} + +struct nvidia_vera_event_sec { + uint8_t version; + uint8_t event_context_count; + uint8_t source_device_type; + uint8_t reserved; + uint16_t event_type; + uint16_t event_sub_type; + uint64_t event_link_id; + char source_module_signature[16]; +} __attribute__((packed)); + +struct nvidia_vera_cpu_info { + uint16_t info_version; + uint8_t info_size; + uint8_t socket_number; + uint32_t architecture; + uint8_t chip_serial_number[16]; + uint64_t instance_base; +} __attribute__((packed)); + +struct nvidia_vera_context_sec { + uint32_t context_size; + uint16_t context_version; + uint16_t reserved; + uint16_t data_format_type; + uint16_t data_format_version; + uint32_t data_size; +} __attribute__((packed)); + +struct nvidia_vera_context { + uint32_t context_size; + uint16_t context_version; + uint16_t data_format_type; + uint16_t data_format_version; + uint32_t data_size; + const uint8_t *data; +}; + +struct nvidia_vera_decoded { + char signature[17]; + uint8_t version; + uint8_t event_context_count; + uint8_t source_device_type; + uint16_t event_type; + uint16_t event_sub_type; + uint64_t event_link_id; + uint8_t socket; + uint32_t architecture; + uint8_t chip_serial_number[16]; + uint64_t instance_base; + struct nvidia_vera_context contexts[NVIDIA_VERA_MAX_CONTEXTS]; +}; + +static void nvidia_trace_hex_bytes(struct trace_seq *s, const uint8_t *buf, size_t len) +{ + size_t i; + + for (i = 0; i < len; i++) + trace_seq_printf(s, "%02x", buf[i]); +} + +static int nvidia_vera_context_entry_count(const struct nvidia_vera_context *ctx) +{ + if (!ctx) + return -EINVAL; + if (ctx->data_size > INT_MAX) + return -EOVERFLOW; + + switch (ctx->data_format_type) { + case 0: + return 0; + case 1: + return ctx->data_size / 16; + case 2: + case 3: + return ctx->data_size / 8; + case 4: + return ctx->data_size / 4; + default: + return -EINVAL; + } +} + +static int nvidia_vera_context_u64_pair(const struct nvidia_vera_context *ctx, + unsigned int index, uint64_t *addr, uint64_t *val) +{ + int count; + + if (!ctx || !addr || !val || ctx->data_format_type != 1) + return -EINVAL; + + count = nvidia_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >= (unsigned int)count) + return -ERANGE; + + *addr = nvidia_vera_le64(ctx->data + index * 16); + *val = nvidia_vera_le64(ctx->data + index * 16 + 8); + + return 0; +} + +static int nvidia_vera_context_u32_pair(const struct nvidia_vera_context *ctx, + unsigned int index, uint32_t *addr, uint32_t *val) +{ + int count; + + if (!ctx || !addr || !val || ctx->data_format_type != 2) + return -EINVAL; + + count = nvidia_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >= (unsigned int)count) + return -ERANGE; + + *addr = nvidia_vera_le32(ctx->data + index * 8); + *val = nvidia_vera_le32(ctx->data + index * 8 + 4); + + return 0; +} + +static int nvidia_vera_context_u64_value(const struct nvidia_vera_context *ctx, + unsigned int index, uint64_t *val) +{ + int count; + + if (!ctx || !val || ctx->data_format_type != 3) + return -EINVAL; + + count = nvidia_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >= (unsigned int)count) + return -ERANGE; + + *val = nvidia_vera_le64(ctx->data + index * 8); + + return 0; +} + +static int nvidia_vera_context_u32_value(const struct nvidia_vera_context *ctx, + unsigned int index, uint32_t *val) +{ + int count; + + if (!ctx || !val || ctx->data_format_type != 4) + return -EINVAL; + + count = nvidia_vera_context_entry_count(ctx); + if (count < 0) + return count; + if (index >= (unsigned int)count) + return -ERANGE; + + *val = nvidia_vera_le32(ctx->data + index * 4); + + return 0; +} + +static int nvidia_vera_validate_context_data(uint16_t data_format_type, + uint32_t data_size) +{ + switch (data_format_type) { + case 0: + return 0; + case 1: + return data_size % 16 ? -EINVAL : 0; + case 2: + case 3: + return data_size % 8 ? -EINVAL : 0; + case 4: + return data_size % 4 ? -EINVAL : 0; + default: + return -EOPNOTSUPP; + } +} + +static void nvidia_vera_print_context(struct trace_seq *s, + const struct nvidia_vera_context *ctx, + unsigned int index) +{ + int entries; + unsigned int i; + uint64_t addr64, val64; + uint32_t addr32, val32; + int rc; + + trace_seq_printf(s, + "context[%u]: version=%u format=%u format_version=%u context_size=%u data_size=%u\n", + index, ctx->context_version, ctx->data_format_type, + ctx->data_format_version, ctx->context_size, + ctx->data_size); + + if (ctx->data_format_type == 0 && ctx->data_size > 0) { + unsigned int prefix_len = ctx->data_size > 16 ? 16 : ctx->data_size; + + trace_seq_printf(s, "context[%u]_opaque_prefix: ", index); + nvidia_trace_hex_bytes(s, ctx->data, prefix_len); + trace_seq_printf(s, "\n"); + return; + } + + entries = nvidia_vera_context_entry_count(ctx); + if (entries < 0) { + trace_seq_printf(s, " WARNING: invalid context data (%d)\n", entries); + return; + } + + trace_seq_printf(s, "context[%u]_entries: %d\n", index, entries); + + for (i = 0; i < (unsigned int)entries; i++) { + switch (ctx->data_format_type) { + case 1: + rc = nvidia_vera_context_u64_pair(ctx, i, &addr64, &val64); + if (!rc) + trace_seq_printf(s, " context[%u].reg[%u]: addr=0x%016llx val=0x%016llx\n", + index, i, + (unsigned long long)addr64, + (unsigned long long)val64); + break; + case 2: + rc = nvidia_vera_context_u32_pair(ctx, i, &addr32, &val32); + if (!rc) + trace_seq_printf(s, " context[%u].reg[%u]: addr=0x%08x val=0x%08x\n", + index, i, addr32, val32); + break; + case 3: + rc = nvidia_vera_context_u64_value(ctx, i, &val64); + if (!rc) + trace_seq_printf(s, " context[%u].value[%u]: 0x%016llx\n", + index, i, (unsigned long long)val64); + break; + case 4: + rc = nvidia_vera_context_u32_value(ctx, i, &val32); + if (!rc) + trace_seq_printf(s, " context[%u].value[%u]: 0x%08x\n", + index, i, val32); + break; + default: + break; + } + } +} + +static int nvidia_decode_vera_cper_sec(const void *buf, size_t len, + struct nvidia_vera_decoded *decoded) +{ + const struct nvidia_vera_event_sec *event = buf; + const struct nvidia_vera_cpu_info *cpu_info; + const struct nvidia_vera_context_sec *context; + const uint8_t *bytes = buf; + size_t data_end_advance; + size_t advance; + size_t offset; + int i; + int ret; + + if (!buf || !decoded) + return -EINVAL; + if (len < sizeof(*event)) + return -ENODATA; + if (event->version != NVIDIA_VERA_VERSION) + return -EOPNOTSUPP; + if (event->source_device_type != 0) + return -EOPNOTSUPP; + + offset = sizeof(*event); + if (len - offset < sizeof(*cpu_info)) + return -ENODATA; + + cpu_info = (const void *)(bytes + offset); + if (cpu_info->info_size < sizeof(*cpu_info)) + return -EINVAL; + if (len - offset < cpu_info->info_size) + return -ENODATA; + + offset += cpu_info->info_size; + if (event->event_context_count > NVIDIA_VERA_MAX_CONTEXTS) + return -E2BIG; + + memset(decoded, 0, sizeof(*decoded)); + memcpy(decoded->signature, event->source_module_signature, + sizeof(event->source_module_signature)); + decoded->signature[sizeof(event->source_module_signature)] = '\0'; + decoded->version = event->version; + decoded->event_context_count = event->event_context_count; + decoded->source_device_type = event->source_device_type; + decoded->event_type = nvidia_vera_le16(&event->event_type); + decoded->event_sub_type = nvidia_vera_le16(&event->event_sub_type); + decoded->event_link_id = nvidia_vera_le64(&event->event_link_id); + decoded->socket = cpu_info->socket_number; + decoded->architecture = nvidia_vera_le32(&cpu_info->architecture); + memcpy(decoded->chip_serial_number, cpu_info->chip_serial_number, + sizeof(cpu_info->chip_serial_number)); + decoded->instance_base = nvidia_vera_le64(&cpu_info->instance_base); + + for (i = 0; i < event->event_context_count; i++) { + struct nvidia_vera_context *decoded_context = &decoded->contexts[i]; + uint32_t context_size; + uint32_t data_size; + uint16_t data_format_type; + + if (len - offset < sizeof(*context)) + return -ENODATA; + + context = (const void *)(bytes + offset); + context_size = nvidia_vera_le32(&context->context_size); + data_format_type = nvidia_vera_le16(&context->data_format_type); + data_size = nvidia_vera_le32(&context->data_size); + + if (context_size < sizeof(*context)) + return -EINVAL; + if (data_format_type > 4) + return -EOPNOTSUPP; + if (data_size > SIZE_MAX - sizeof(*context)) + return -EOVERFLOW; + + data_end_advance = sizeof(*context) + data_size; + if (data_end_advance > len - offset) + return -ENODATA; + + if (context_size == sizeof(*context)) + advance = data_end_advance; + else if (data_size <= context_size - sizeof(*context)) + advance = context_size; + else + return -EINVAL; + + if (advance > len - offset) + return -ENODATA; + + ret = nvidia_vera_validate_context_data(data_format_type, data_size); + if (ret) + return ret; + + decoded_context->context_size = context_size; + decoded_context->context_version = + nvidia_vera_le16(&context->context_version); + decoded_context->data_format_type = data_format_type; + decoded_context->data_format_version = + nvidia_vera_le16(&context->data_format_version); + decoded_context->data_size = data_size; + decoded_context->data = bytes + offset + sizeof(*context); + offset += advance; + } + + return 0; +} + +#ifdef HAVE_SQLITE3 static const struct db_fields nvidia_ns_fields[] = { { .name = "id", .type = "INTEGER PRIMARY KEY" }, @@ -108,14 +550,8 @@ static int nvidia_ns_add_table(struct ras_events *ras, struct ras_ns_ev_decoder *ev_decoder) { - int rc; - - rc = ras_mc_add_vendor_table(ras, &ev_decoder->stmt_dec_record, - &nvidia_ns_table); - if (rc != SQLITE_OK) - log(TERM, LOG_ERR, "Failed to create/prepare NVIDIA table: %d\n", rc); - - return rc; + return nvidia_add_vendor_table(ras, ev_decoder, &nvidia_ns_table, + "NVIDIA"); } static int nvidia_ns_decode(struct ras_events *ras, @@ -126,9 +562,6 @@ const struct nvidia_cper_sec *err; char timestamp[64]; uint32_t reg_data_len; - time_t now; - struct tm *tm; - int rc; if (event->length < sizeof(struct nvidia_cper_sec)) { trace_seq_printf(s, "NVIDIA CPER section too small: %u bytes\n", @@ -138,19 +571,10 @@ err = (const struct nvidia_cper_sec *)event->error; - /* Format timestamp */ - now = time(NULL); - tm = localtime(&now); - if (tm) - strftime(timestamp, sizeof(timestamp), - "%Y-%m-%d %H:%M:%S %z", tm); - else - strcpy(timestamp, "unknown"); + nvidia_format_timestamp(timestamp, sizeof(timestamp)); - /* Decode the CPER section for display */ decode_nvidia_cper_sec(ev_decoder, s, err, event->length); - /* Store in database */ if (ev_decoder->stmt_dec_record) { reg_data_len = event->length - sizeof(struct nvidia_cper_sec); @@ -163,7 +587,6 @@ sqlite3_bind_int(ev_decoder->stmt_dec_record, 7, err->number_regs); sqlite3_bind_int64(ev_decoder->stmt_dec_record, 8, err->instance_base); - /* Bind register data (parsed from structure) */ if (reg_data_len > 0) { const uint8_t *reg_data = (const uint8_t *)err + sizeof(struct nvidia_cper_sec); @@ -173,19 +596,111 @@ sqlite3_bind_null(ev_decoder->stmt_dec_record, 9); } - /* Bind complete raw binary data from the event */ sqlite3_bind_blob(ev_decoder->stmt_dec_record, 10, event->error, event->length, SQLITE_TRANSIENT); - rc = sqlite3_step(ev_decoder->stmt_dec_record); - if (rc != SQLITE_DONE) - log(TERM, LOG_ERR, - "Failed to store NVIDIA event in database: error = %d\n", rc); - - rc = sqlite3_reset(ev_decoder->stmt_dec_record); - if (rc != SQLITE_OK) - log(TERM, LOG_ERR, - "Failed to reset NVIDIA statement: error = %d\n", rc); + nvidia_store_vendor_record(ev_decoder, "NVIDIA"); + } + + return 0; +} + +static const struct db_fields nvidia_vera_ns_fields[] = { + { .name = "id", .type = "INTEGER PRIMARY KEY" }, + { .name = "timestamp", .type = "TEXT" }, + { .name = "signature", .type = "TEXT" }, + { .name = "event_type", .type = "INTEGER" }, + { .name = "event_sub_type", .type = "INTEGER" }, + { .name = "event_link_id", .type = "INTEGER" }, + { .name = "source_device_type", .type = "INTEGER" }, + { .name = "event_context_count", .type = "INTEGER" }, + { .name = "socket", .type = "INTEGER" }, + { .name = "architecture", .type = "INTEGER" }, + { .name = "chip_serial_number", .type = "BLOB" }, + { .name = "instance_base", .type = "INTEGER" }, + { .name = "raw_data", .type = "BLOB" }, +}; + +static const struct db_table_descriptor nvidia_vera_ns_table = { + .name = "nvidia_vera_ns_event", + .fields = nvidia_vera_ns_fields, + .num_fields = ARRAY_SIZE(nvidia_vera_ns_fields), +}; + +static int nvidia_vera_ns_add_table(struct ras_events *ras, + struct ras_ns_ev_decoder *ev_decoder) +{ + return nvidia_add_vendor_table(ras, ev_decoder, &nvidia_vera_ns_table, + "NVIDIA Vera"); +} + +static int nvidia_vera_ns_decode(struct ras_events *ras, + struct ras_ns_ev_decoder *ev_decoder, + struct trace_seq *s, + struct ras_non_standard_event *event) +{ + struct nvidia_vera_decoded decoded; + char timestamp[64]; + int rc; + unsigned int i; + + if (event->length < sizeof(struct nvidia_vera_event_sec) + + sizeof(struct nvidia_vera_cpu_info)) { + trace_seq_printf(s, "NVIDIA Vera CPER section too small: %u bytes\n", + event->length); + return -1; + } + + rc = nvidia_decode_vera_cper_sec(event->error, event->length, &decoded); + if (rc) { + trace_seq_printf(s, "Malformed NVIDIA Vera CPER section, error_data_length: %u, ret: %d\n", + event->length, rc); + return -1; + } + + nvidia_format_timestamp(timestamp, sizeof(timestamp)); + + trace_seq_printf(s, "NVIDIA Vera CPER section, error_data_length: %u\n", + event->length); + trace_seq_printf(s, "version: %u\n", decoded.version); + trace_seq_printf(s, "signature: %s\n", decoded.signature); + trace_seq_printf(s, "event_type: %u\n", decoded.event_type); + trace_seq_printf(s, "event_sub_type: %u\n", decoded.event_sub_type); + trace_seq_printf(s, "event_link_id: 0x%016llx\n", + (unsigned long long)decoded.event_link_id); + trace_seq_printf(s, "source_device_type: %u\n", decoded.source_device_type); + trace_seq_printf(s, "socket: %u\n", decoded.socket); + trace_seq_printf(s, "architecture: 0x%x\n", decoded.architecture); + trace_seq_printf(s, "chip_serial_number: "); + nvidia_trace_hex_bytes(s, decoded.chip_serial_number, + sizeof(decoded.chip_serial_number)); + trace_seq_printf(s, "\n"); + trace_seq_printf(s, "instance_base: 0x%016llx\n", + (unsigned long long)decoded.instance_base); + trace_seq_printf(s, "event_context_count: %u\n", decoded.event_context_count); + + for (i = 0; i < decoded.event_context_count; i++) + nvidia_vera_print_context(s, &decoded.contexts[i], i); + + if (ev_decoder->stmt_dec_record) { + sqlite3_bind_text(ev_decoder->stmt_dec_record, 1, timestamp, -1, SQLITE_TRANSIENT); + sqlite3_bind_text(ev_decoder->stmt_dec_record, 2, decoded.signature, + sizeof(decoded.signature) - 1, SQLITE_TRANSIENT); + sqlite3_bind_int(ev_decoder->stmt_dec_record, 3, decoded.event_type); + sqlite3_bind_int(ev_decoder->stmt_dec_record, 4, decoded.event_sub_type); + sqlite3_bind_int64(ev_decoder->stmt_dec_record, 5, decoded.event_link_id); + sqlite3_bind_int(ev_decoder->stmt_dec_record, 6, decoded.source_device_type); + sqlite3_bind_int(ev_decoder->stmt_dec_record, 7, decoded.event_context_count); + sqlite3_bind_int(ev_decoder->stmt_dec_record, 8, decoded.socket); + sqlite3_bind_int64(ev_decoder->stmt_dec_record, 9, decoded.architecture); + sqlite3_bind_blob(ev_decoder->stmt_dec_record, 10, + decoded.chip_serial_number, + sizeof(decoded.chip_serial_number), SQLITE_TRANSIENT); + sqlite3_bind_int64(ev_decoder->stmt_dec_record, 11, decoded.instance_base); + sqlite3_bind_blob(ev_decoder->stmt_dec_record, 12, + event->error, event->length, SQLITE_TRANSIENT); + + nvidia_store_vendor_record(ev_decoder, "NVIDIA Vera"); } return 0; @@ -193,16 +708,24 @@ #endif /* HAVE_SQLITE3 */ -/* NVIDIA CPER decoder registration */ struct ras_ns_ev_decoder nvidia_ns_ev_decoder = { - .sec_type = NVIDIA_SEC_TYPE_UUID, + .sec_type = NVIDIA_GRACE_SEC_TYPE_UUID, #ifdef HAVE_SQLITE3 .add_table = nvidia_ns_add_table, .decode = nvidia_ns_decode, #endif }; +static struct ras_ns_ev_decoder nvidia_vera_ns_ev_decoder = { + .sec_type = NVIDIA_VERA_SEC_TYPE_UUID, +#ifdef HAVE_SQLITE3 + .add_table = nvidia_vera_ns_add_table, + .decode = nvidia_vera_ns_decode, +#endif +}; + static void __attribute__((constructor)) nvidia_init(void) { register_ns_ev_decoder(&nvidia_ns_ev_decoder); + register_ns_ev_decoder(&nvidia_vera_ns_ev_decoder); } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/non-standard-nvidia.h new/rasdaemon-0.8.5+git0.769593b/non-standard-nvidia.h --- old/rasdaemon-0.8.4+git33.4f1f08a/non-standard-nvidia.h 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/non-standard-nvidia.h 2026-06-26 12:00:07.000000000 +0200 @@ -13,7 +13,8 @@ struct ras_ns_ev_decoder; -#define NVIDIA_SEC_TYPE_UUID "6d5244f2-2712-11ec-bea7-cb3fdb95c786" +#define NVIDIA_GRACE_SEC_TYPE_UUID "6d5244f2-2712-11ec-bea7-cb3fdb95c786" +#define NVIDIA_VERA_SEC_TYPE_UUID "9068e568-6ca0-11f0-aeaf-159343591eac" /* NVIDIA CPER Error Section Structure */ struct nvidia_cper_sec { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/ras-mce-handler.c new/rasdaemon-0.8.5+git0.769593b/ras-mce-handler.c --- old/rasdaemon-0.8.4+git33.4f1f08a/ras-mce-handler.c 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/ras-mce-handler.c 2026-06-26 12:00:07.000000000 +0200 @@ -56,6 +56,7 @@ [CPU_GRANITERAPIDS_D] = "Graniterapids server D Family", [CPU_SIERRAFOREST] = "Sierraforest server", [CPU_CLEARWATERFOREST] = "Clearwaterforest server", + [CPU_DIAMONDRAPIDS] = "Diamondrapids server", [CPU_ZHAOXIN] = "Zhaoxin generic CPU", [CPU_ZHAOXIN_KH50000] = "Zhaoxin KH-50000 server", }; @@ -132,7 +133,12 @@ mce->model); return CPU_INTEL; } + } else if (mce->family == 19) { + mce->mc_error_support = 1; + if (mce->model == 0x01) + return CPU_DIAMONDRAPIDS; } + if (mce->family > 6) { log(ALL, LOG_INFO, "Family %u Model %x CPU: only decoding architectural errors\n", diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/ras-mce-handler.h new/rasdaemon-0.8.5+git0.769593b/ras-mce-handler.h --- old/rasdaemon-0.8.4+git33.4f1f08a/ras-mce-handler.h 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/ras-mce-handler.h 2026-06-26 12:00:07.000000000 +0200 @@ -48,6 +48,7 @@ CPU_GRANITERAPIDS_D, CPU_SIERRAFOREST, CPU_CLEARWATERFOREST, + CPU_DIAMONDRAPIDS, }; struct mce_event { @@ -141,6 +142,7 @@ void skylake_s_decode_model(struct ras_events *ras, struct mce_event *e); void i10nm_decode_model(enum cputype cputype, struct ras_events *ras, struct mce_event *e); void granite_decode_model(enum cputype cputype, struct ras_events *ras, struct mce_event *e); +void diamond_decode_model(enum cputype cputype, struct ras_events *ras, struct mce_event *e); /* AMD error code decode function */ void decode_amd_errcode(struct mce_event *e); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/ras-non-standard-handler.c new/rasdaemon-0.8.5+git0.769593b/ras-non-standard-handler.c --- old/rasdaemon-0.8.4+git33.4f1f08a/ras-non-standard-handler.c 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/ras-non-standard-handler.c 2026-06-26 12:00:07.000000000 +0200 @@ -162,7 +162,7 @@ struct tep_record *record, struct tep_event *event, void *context) { - int len, i, line_count; + int len, i, line_count, decoded = 0; unsigned long long val; struct ras_events *ras = context; time_t now; @@ -236,8 +236,13 @@ return -1; if (!find_ns_ev_decoder(ev.sec_type, &ns_ev_decoder)) { - ns_ev_decoder->decode(ras, ns_ev_decoder, s, &ev); - } else { + if (ns_ev_decoder->decode) { + ns_ev_decoder->decode(ras, ns_ev_decoder, s, &ev); + decoded = 1; + } + } + + if (!decoded) { len = ev.length; i = 0; line_count = 0; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/ras-page-isolation.c new/rasdaemon-0.8.5+git0.769593b/ras-page-isolation.c --- old/rasdaemon-0.8.4+git33.4f1f08a/ras-page-isolation.c 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/ras-page-isolation.c 2026-06-26 12:00:07.000000000 +0200 @@ -603,7 +603,7 @@ if (!str || !anchor_str || !value) return 1; - char *pos = strstr(str, anchor_str); + char *pos = (void *)strstr(str, anchor_str); if (!pos) return 1; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/rasdaemon-0.8.4+git33.4f1f08a/util/ras-mc-ctl.in new/rasdaemon-0.8.5+git0.769593b/util/ras-mc-ctl.in --- old/rasdaemon-0.8.4+git33.4f1f08a/util/ras-mc-ctl.in 2026-02-27 10:17:14.000000000 +0100 +++ new/rasdaemon-0.8.5+git0.769593b/util/ras-mc-ctl.in 2026-06-26 12:00:07.000000000 +0200 @@ -234,6 +234,23 @@ return ($?>>8); } +sub sqlite_table_exists +{ + my ($dbh, $table) = @_; + my $query = "select 1 from sqlite_master where type='table' and name=?"; + my $query_handle = $dbh->prepare($query); + my $exists = 0; + + return 0 if (!$query_handle); + + $query_handle->execute($table); + $query_handle->bind_columns(\my $one); + $exists = 1 if ($query_handle->fetch()); + $query_handle->finish; + + return $exists; +} + sub print_status { @@ -1596,8 +1613,10 @@ my ($etype, $severity, $etype_string, $severity_string); my ($dev_name, $dev); my ($mpidr, $memdev); + my $has_nvidia_vera_ns = 0; my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); + $has_nvidia_vera_ns = sqlite_table_exists($dbh, "nvidia_vera_ns_event"); # Memory controller mc_event errors $query = "select err_type, label, mc, top_layer,middle_layer,lower_layer, count(*) from mc_event$conf{opt}{since} group by err_type, label, mc, top_layer, middle_layer, lower_layer"; @@ -1670,6 +1689,24 @@ $query_handle->finish; } + if ($has_nvidia_vera_ns == 1) { + $query = "select signature, socket, count(*) from nvidia_vera_ns_event$conf{opt}{since} group by signature, socket"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + my ($signature, $socket); + $query_handle->bind_columns(\($signature, $socket, $count)); + $out = ""; + while($query_handle->fetch()) { + $out .= sprintf "\tNVIDIA Vera device (signature=%s, socket=%d) has %d errors\n", $signature, $socket, $count; + } + if ($out ne "") { + print "NVIDIA Vera events summary:\n$out\n"; + } else { + print "No NVIDIA Vera errors.\n\n"; + } + $query_handle->finish; + } + # CXL errors if ($has_cxl == 1) { # CXL AER uncorrectable errors @@ -1933,8 +1970,10 @@ my ($event_type, $event_sub_type, $health_status, $media_status, $life_used, $dirty_shutdown_cnt, $cor_vol_err_cnt, $cor_per_err_cnt, $device_temp, $add_status); my ($sub_type, $sub_channel, $cme_threshold_ev_flags, $cme_count, $cvme_count); my ($signal, $errorno, $code, $comm, $pid, $grp, $res); + my $has_nvidia_vera_ns = 0; my $dbh = DBI->connect("dbi:SQLite:dbname=$dbname", "", "", {}); + $has_nvidia_vera_ns = sqlite_table_exists($dbh, "nvidia_vera_ns_event"); # Memory controller mc_event errors $query = "select id, timestamp, err_count, err_type, err_msg, label, mc, top_layer,middle_layer,lower_layer, address, grain, syndrome, driver_detail from mc_event$conf{opt}{since} order by id"; @@ -2032,6 +2071,37 @@ $query_handle->finish; } + if ($has_nvidia_vera_ns == 1) { + $query = "select id, timestamp, signature, event_type, event_sub_type, event_link_id, source_device_type, event_context_count, socket, architecture, chip_serial_number, instance_base from nvidia_vera_ns_event$conf{opt}{since} order by id"; + $query_handle = $dbh->prepare($query); + $query_handle->execute(); + my ($signature, $event_type, $event_sub_type, $event_link_id, $source_device_type, $event_context_count, $socket, $architecture, $chip_serial_number, $instance_base); + $query_handle->bind_columns(\($id, $timestamp, $signature, $event_type, $event_sub_type, $event_link_id, $source_device_type, $event_context_count, $socket, $architecture, $chip_serial_number, $instance_base)); + $out = ""; + while($query_handle->fetch()) { + $out .= "$id $timestamp error: "; + $out .= "signature=$signature, "; + $out .= "event_type=$event_type, "; + $out .= "event_sub_type=$event_sub_type, "; + $out .= sprintf "event_link_id=0x%llx, ", $event_link_id; + $out .= "source_device_type=$source_device_type, "; + $out .= "event_context_count=$event_context_count, "; + $out .= "socket=$socket, "; + $out .= sprintf "architecture=0x%x, ", $architecture; + if (defined $chip_serial_number && length $chip_serial_number) { + $out .= sprintf "chip_serial_number=%s, ", unpack("H*", $chip_serial_number); + } + $out .= sprintf "instance_base=0x%llx", $instance_base; + $out .= "\n"; + } + if ($out ne "") { + print "NVIDIA Vera events:\n$out\n"; + } else { + print "No NVIDIA Vera errors.\n\n"; + } + $query_handle->finish; + } + # CXL errors if ($has_cxl == 1) { # CXL AER uncorrectable errors @@ -2497,7 +2567,7 @@ # SIGNAL event if ($has_signal == 1) { - $query = "select id, timestamp, signal, errorno, code, comm, pid, grp, res from signal_event$conf{opt}{since} order by id"; + $query = "select id, timestamp, sig, errorno, code, comm, pid, grp, res from signal_event$conf{opt}{since} order by id"; $query_handle = $dbh->prepare($query); $query_handle->execute(); $query_handle->bind_columns(\($id, $timestamp, $signal, $errorno, $code, $comm, $pid, $grp, $res)); ++++++ rasdaemon.obsinfo ++++++ --- /var/tmp/diff_new_pack.KAXNul/_old 2026-07-03 16:11:15.486477599 +0200 +++ /var/tmp/diff_new_pack.KAXNul/_new 2026-07-03 16:11:15.502478154 +0200 @@ -1,5 +1,5 @@ name: rasdaemon -version: 0.8.4+git33.4f1f08a -mtime: 1772183834 -commit: 4f1f08a2913a836587eb47ad283dd7246f15b5ab +version: 0.8.5+git0.769593b +mtime: 1782468007 +commit: 769593be915b4f00a9a7d56569df99bc0cff249a
