Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package libdrm for openSUSE:Factory checked
in at 2021-06-04 00:33:10
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/libdrm (Old)
and /work/SRC/openSUSE:Factory/.libdrm.new.1898 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "libdrm"
Fri Jun 4 00:33:10 2021 rev:154 rq:894907 version:2.4.106
Changes:
--------
--- /work/SRC/openSUSE:Factory/libdrm/libdrm.changes 2021-04-10
15:26:31.890318758 +0200
+++ /work/SRC/openSUSE:Factory/.libdrm.new.1898/libdrm.changes 2021-06-04
00:33:13.372875219 +0200
@@ -1,0 +2,7 @@
+Wed May 19 08:13:47 UTC 2021 - Paolo Stivanin <i...@paolostivanin.com>
+
+- Update to 2.4.106:
+ * various nouveau fixes
+ * improve tests
+
+-------------------------------------------------------------------
Old:
----
libdrm-2.4.105.tar.xz
New:
----
libdrm-2.4.106.tar.xz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ libdrm.spec ++++++
--- /var/tmp/diff_new_pack.HZW1Rd/_old 2021-06-04 00:33:13.956875672 +0200
+++ /var/tmp/diff_new_pack.HZW1Rd/_new 2021-06-04 00:33:13.960875674 +0200
@@ -17,7 +17,7 @@
Name: libdrm
-Version: 2.4.105
+Version: 2.4.106
Release: 0
Summary: Userspace Interface for Kernel DRM Services
License: MIT
++++++ libdrm-2.4.105.tar.xz -> libdrm-2.4.106.tar.xz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/meson.build
new/libdrm-2.4.106/meson.build
--- old/libdrm-2.4.105/meson.build 2021-04-07 16:09:24.175843200 +0200
+++ new/libdrm-2.4.106/meson.build 2021-05-18 05:42:27.000000000 +0200
@@ -21,7 +21,7 @@
project(
'libdrm',
['c'],
- version : '2.4.105',
+ version : '2.4.106',
license : 'MIT',
meson_version : '>= 0.43',
default_options : ['buildtype=debugoptimized', 'c_std=gnu99'],
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/nouveau/nouveau.c
new/libdrm-2.4.106/nouveau/nouveau.c
--- old/libdrm-2.4.105/nouveau/nouveau.c 2021-04-07 16:09:24.175843200
+0200
+++ new/libdrm-2.4.106/nouveau/nouveau.c 2021-05-18 05:42:27.000000000
+0200
@@ -46,19 +46,35 @@
#include "nvif/ioctl.h"
#include "nvif/unpack.h"
-#ifdef DEBUG
+drm_private FILE *nouveau_out = NULL;
drm_private uint32_t nouveau_debug = 0;
static void
-debug_init(char *args)
+debug_init(void)
{
- if (args) {
- int n = strtol(args, NULL, 0);
+ static bool once = false;
+ char *debug, *out;
+
+ if (once)
+ return;
+ once = true;
+
+ debug = getenv("NOUVEAU_LIBDRM_DEBUG");
+ if (debug) {
+ int n = strtol(debug, NULL, 0);
if (n >= 0)
nouveau_debug = n;
+
+ }
+
+ nouveau_out = stderr;
+ out = getenv("NOUVEAU_LIBDRM_OUT");
+ if (out) {
+ FILE *fout = fopen(out, "w");
+ if (fout)
+ nouveau_out = fout;
}
}
-#endif
static int
nouveau_object_ioctl(struct nouveau_object *obj, void *data, uint32_t size)
@@ -327,9 +343,7 @@
struct nouveau_drm *drm;
drmVersionPtr ver;
-#ifdef DEBUG
- debug_init(getenv("NOUVEAU_LIBDRM_DEBUG"));
-#endif
+ debug_init();
if (!(drm = calloc(1, sizeof(*drm))))
return -ENOMEM;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/nouveau/private.h
new/libdrm-2.4.106/nouveau/private.h
--- old/libdrm-2.4.105/nouveau/private.h 2021-04-07 16:09:24.175843200
+0200
+++ new/libdrm-2.4.106/nouveau/private.h 2021-05-18 05:42:27.000000000
+0200
@@ -1,6 +1,8 @@
#ifndef __NOUVEAU_LIBDRM_PRIVATE_H__
#define __NOUVEAU_LIBDRM_PRIVATE_H__
+#include <stdio.h>
+
#include <libdrm_macros.h>
#include <xf86drm.h>
#include <xf86atomic.h>
@@ -9,18 +11,19 @@
#include "nouveau.h"
-#ifdef DEBUG
+/*
+ * 0x00000001 dump all pushbuffers
+ * 0x00000002 submit pushbuffers synchronously
+ * 0x80000000 if compiled with SIMULATE return -EINVAL for all pb submissions
+ */
drm_private extern uint32_t nouveau_debug;
+drm_private extern FILE *nouveau_out;
#define dbg_on(lvl) (nouveau_debug & (1 << lvl))
#define dbg(lvl, fmt, args...) do {
\
if (dbg_on((lvl))) \
- fprintf(stderr, "nouveau: "fmt, ##args); \
+ fprintf(nouveau_out, "nouveau: "fmt, ##args);
\
} while(0)
-#else
-#define dbg_on(lvl) (0)
-#define dbg(lvl, fmt, args...)
-#endif
-#define err(fmt, args...) fprintf(stderr, "nouveau: "fmt, ##args)
+#define err(fmt, args...) fprintf(nouveau_out, "nouveau: "fmt, ##args)
struct nouveau_client_kref {
struct drm_nouveau_gem_pushbuf_bo *kref;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/nouveau/pushbuf.c
new/libdrm-2.4.106/nouveau/pushbuf.c
--- old/libdrm-2.4.105/nouveau/pushbuf.c 2021-04-07 16:09:24.175843200
+0200
+++ new/libdrm-2.4.106/nouveau/pushbuf.c 2021-05-18 05:42:27.000000000
+0200
@@ -292,11 +292,14 @@
kref = krec->buffer + kpsh->bo_index;
bo = (void *)(unsigned long)kref->user_priv;
bgn = (uint32_t *)((char *)bo->map + kpsh->offset);
- end = bgn + (kpsh->length /4);
+ end = bgn + ((kpsh->length & 0x7fffff) /4);
- err("ch%d: psh %08x %010llx %010llx\n", chid, kpsh->bo_index,
+ err("ch%d: psh %s%08x %010llx %010llx\n", chid,
+ bo->map ? "" : "(unmapped) ", kpsh->bo_index,
(unsigned long long)kpsh->offset,
(unsigned long long)(kpsh->offset + kpsh->length));
+ if (!bo->map)
+ continue;
while (bgn < end)
err("\t0x%08x\n", *bgn++);
}
@@ -336,6 +339,8 @@
req.suffix0 = nvpb->suffix0;
req.suffix1 = nvpb->suffix1;
req.vram_available = 0; /* for valgrind */
+ if (dbg_on(1))
+ req.vram_available |= NOUVEAU_GEM_PUSHBUF_SYNC;
req.gart_available = 0;
if (dbg_on(0))
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/amdgpu_test.h
new/libdrm-2.4.106/tests/amdgpu/amdgpu_test.h
--- old/libdrm-2.4.105/tests/amdgpu/amdgpu_test.h 2021-04-07
16:09:24.175843200 +0200
+++ new/libdrm-2.4.106/tests/amdgpu/amdgpu_test.h 2021-05-18
05:42:27.000000000 +0200
@@ -449,13 +449,18 @@
return r;
}
-static inline bool asic_is_arcturus(uint32_t asic_id)
+
+static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t
chip_id, uint32_t chip_rev)
{
- switch(asic_id) {
- /* Arcturus asic DID */
- case 0x738C:
- case 0x7388:
- case 0x738E:
+
+ if (family_id != AMDGPU_FAMILY_AI)
+ return false;
+
+ switch (chip_id - chip_rev) {
+ /* Arcturus */
+ case 0x32:
+ /* Aldebaran */
+ case 0x3c:
return true;
default:
return false;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/basic_tests.c
new/libdrm-2.4.106/tests/amdgpu/basic_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/basic_tests.c 2021-04-07
16:09:24.175843200 +0200
+++ new/libdrm-2.4.106/tests/amdgpu/basic_tests.c 2021-05-18
05:42:27.000000000 +0200
@@ -46,6 +46,8 @@
static uint32_t major_version;
static uint32_t minor_version;
static uint32_t family_id;
+static uint32_t chip_id;
+static uint32_t chip_rev;
static void amdgpu_query_info_test(void);
static void amdgpu_command_submission_gfx(void);
@@ -341,9 +343,10 @@
};
static const uint32_t bufferclear_cs_shader_gfx9[] = {
- 0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205,
- 0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100,
- 0xBF810000
+ 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
+ 0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206,
+ 0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000,
+ 0xbf810000
};
static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
@@ -357,8 +360,9 @@
static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
static const uint32_t buffercopy_cs_shader_gfx9[] = {
- 0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100,
- 0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000
+ 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
+ 0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70,
+ 0xe01c2000, 0x80010200, 0xbf810000
};
static const uint32_t preamblecache_gfx9[] = {
@@ -617,19 +621,20 @@
CU_BOOL suite_basic_tests_enable(void)
{
- uint32_t asic_id;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
- asic_id = device_handle->info.asic_id;
-
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
- /* disable gfx engine basic test cases for Arturus due to no CPG */
- if (asic_is_arcturus(asic_id)) {
+ family_id = device_handle->info.family_id;
+ chip_id = device_handle->info.chip_external_rev;
+ chip_rev = device_handle->info.chip_rev;
+
+ /* disable gfx engine basic test cases for some asics have no CPG */
+ if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
if (amdgpu_set_test_active("Basic Tests",
"Command submission Test (GFX)",
CU_FALSE))
@@ -1071,6 +1076,14 @@
amdgpu_bo_list_handle bo_list[2];
amdgpu_va_handle va_handle[2];
int r, i;
+ struct amdgpu_gpu_info gpu_info = {0};
+ unsigned gc_ip_type;
+
+ r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
+ AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
if (family_id == AMDGPU_FAMILY_SI) {
sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0);
@@ -1113,14 +1126,14 @@
r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0,
0, sem);
CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0,
sem);
+ r = amdgpu_cs_wait_semaphore(context_handle[0], gc_ip_type, 0, 0, sem);
CU_ASSERT_EQUAL(r, 0);
ptr = ib_result_cpu[1];
ptr[0] = gfx_nop;
ib_info[1].ib_mc_address = ib_result_mc_address[1];
ib_info[1].size = 1;
- ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request[1].ip_type = gc_ip_type;
ibs_request[1].number_of_ibs = 1;
ibs_request[1].ibs = &ib_info[1];
ibs_request[1].resources = bo_list[1];
@@ -1130,7 +1143,7 @@
CU_ASSERT_EQUAL(r, 0);
fence_status.context = context_handle[0];
- fence_status.ip_type = AMDGPU_HW_IP_GFX;
+ fence_status.ip_type = gc_ip_type;
fence_status.ip_instance = 0;
fence_status.fence = ibs_request[1].seq_no;
r = amdgpu_cs_query_fence_status(&fence_status,
@@ -1144,24 +1157,24 @@
ib_info[0].ib_mc_address = ib_result_mc_address[0];
ib_info[0].size = 1;
- ibs_request[0].ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request[0].ip_type = gc_ip_type;
ibs_request[0].number_of_ibs = 1;
ibs_request[0].ibs = &ib_info[0];
ibs_request[0].resources = bo_list[0];
ibs_request[0].fence_info.handle = NULL;
r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0,
0, sem);
+ r = amdgpu_cs_signal_semaphore(context_handle[0], gc_ip_type, 0, 0,
sem);
CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0,
sem);
+ r = amdgpu_cs_wait_semaphore(context_handle[1], gc_ip_type, 0, 0, sem);
CU_ASSERT_EQUAL(r, 0);
ptr = ib_result_cpu[1];
ptr[0] = gfx_nop;
ib_info[1].ib_mc_address = ib_result_mc_address[1];
ib_info[1].size = 1;
- ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
+ ibs_request[1].ip_type = gc_ip_type;
ibs_request[1].number_of_ibs = 1;
ibs_request[1].ibs = &ib_info[1];
ibs_request[1].resources = bo_list[1];
@@ -1171,7 +1184,7 @@
CU_ASSERT_EQUAL(r, 0);
fence_status.context = context_handle[1];
- fence_status.ip_type = AMDGPU_HW_IP_GFX;
+ fence_status.ip_type = gc_ip_type;
fence_status.ip_instance = 0;
fence_status.fence = ibs_request[1].seq_no;
r = amdgpu_cs_query_fence_status(&fence_status,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/cs_tests.c
new/libdrm-2.4.106/tests/amdgpu/cs_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/cs_tests.c 2021-04-07 16:09:24.179843000
+0200
+++ new/libdrm-2.4.106/tests/amdgpu/cs_tests.c 2021-05-18 05:42:27.000000000
+0200
@@ -64,21 +64,20 @@
CU_BOOL suite_cs_tests_enable(void)
{
- uint32_t asic_id;
-
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
- asic_id = device_handle->info.asic_id;
+ chip_id = device_handle->info.chip_external_rev;
+ chip_rev = device_handle->info.chip_rev;
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
- asic_is_arcturus(asic_id)) {
+ asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
return CU_FALSE;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/deadlock_tests.c
new/libdrm-2.4.106/tests/amdgpu/deadlock_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/deadlock_tests.c 2021-04-07
16:09:24.179843000 +0200
+++ new/libdrm-2.4.106/tests/amdgpu/deadlock_tests.c 2021-05-18
05:42:27.000000000 +0200
@@ -106,6 +106,10 @@
static pthread_t stress_thread;
static uint32_t *ptr;
+static uint32_t family_id;
+static uint32_t chip_rev;
+static uint32_t chip_id;
+
int use_uc_mtype = 0;
static void amdgpu_deadlock_helper(unsigned ip_type);
@@ -124,25 +128,27 @@
CU_BOOL suite_deadlock_tests_enable(void)
{
CU_BOOL enable = CU_TRUE;
- uint32_t asic_id;
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
+ family_id = device_handle->info.family_id;
+ chip_id = device_handle->info.chip_external_rev;
+ chip_rev = device_handle->info.chip_rev;
+
/*
* Only enable for ASICs supporting GPU reset and for which it's enabled
* by default (currently GFX8/9 dGPUS)
*/
- if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
- device_handle->info.family_id != AMDGPU_FAMILY_AI &&
- device_handle->info.family_id != AMDGPU_FAMILY_CI) {
+ if (family_id != AMDGPU_FAMILY_VI &&
+ family_id != AMDGPU_FAMILY_AI &&
+ family_id != AMDGPU_FAMILY_CI) {
printf("\n\nGPU reset is not enabled for the ASIC, deadlock
suite disabled\n");
enable = CU_FALSE;
}
- asic_id = device_handle->info.asic_id;
- if (asic_is_arcturus(asic_id)) {
+ if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
if (amdgpu_set_test_active("Deadlock Tests",
"gfx ring block test (set
amdgpu.lockup_timeout=50)",
CU_FALSE))
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/security_tests.c
new/libdrm-2.4.106/tests/amdgpu/security_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/security_tests.c 2021-04-07
16:09:24.179843000 +0200
+++ new/libdrm-2.4.106/tests/amdgpu/security_tests.c 2021-05-18
05:42:27.000000000 +0200
@@ -432,7 +432,8 @@
&minor_version, &device_handle))
return CU_FALSE;
- if (device_handle->info.family_id != AMDGPU_FAMILY_RV) {
+
+ if (!(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_TMZ)) {
printf("\n\nDon't support TMZ (trust memory zone), security
suite disabled\n");
enable = CU_FALSE;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/syncobj_tests.c
new/libdrm-2.4.106/tests/amdgpu/syncobj_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/syncobj_tests.c 2021-04-07
16:09:24.179843000 +0200
+++ new/libdrm-2.4.106/tests/amdgpu/syncobj_tests.c 2021-05-18
05:42:27.000000000 +0200
@@ -33,6 +33,10 @@
static uint32_t major_version;
static uint32_t minor_version;
+static uint32_t family_id;
+static uint32_t chip_id;
+static uint32_t chip_rev;
+
static void amdgpu_syncobj_timeline_test(void);
CU_BOOL suite_syncobj_timeline_tests_enable(void)
@@ -99,7 +103,19 @@
uint32_t expired;
int i, r;
uint64_t seq_no;
- uint32_t *ptr;
+ static uint32_t *ptr;
+ struct amdgpu_gpu_info gpu_info = {0};
+ unsigned gc_ip_type;
+
+ r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+ CU_ASSERT_EQUAL(r, 0);
+
+ family_id = device_handle->info.family_id;
+ chip_id = device_handle->info.chip_external_rev;
+ chip_rev = device_handle->info.chip_rev;
+
+ gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
+ AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
CU_ASSERT_EQUAL(r, 0);
@@ -125,11 +141,11 @@
chunk_data.ib_data._pad = 0;
chunk_data.ib_data.va_start = ib_result_mc_address;
chunk_data.ib_data.ib_bytes = 16 * 4;
- chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+ chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type :
AMDGPU_HW_IP_DMA;
chunk_data.ib_data.ip_instance = 0;
chunk_data.ib_data.ring = 0;
- chunk_data.ib_data.flags = 0;
+ chunk_data.ib_data.flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
chunks[1].chunk_id = wait_or_signal ?
AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
@@ -151,7 +167,7 @@
memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
fence_status.context = context_handle;
- fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+ fence_status.ip_type = wait_or_signal ? gc_ip_type :
AMDGPU_HW_IP_DMA;
fence_status.ip_instance = 0;
fence_status.ring = 0;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/vce_tests.c
new/libdrm-2.4.106/tests/amdgpu/vce_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/vce_tests.c 2021-04-07 16:09:24.179843000
+0200
+++ new/libdrm-2.4.106/tests/amdgpu/vce_tests.c 2021-05-18 05:42:27.000000000
+0200
@@ -116,7 +116,7 @@
return CU_FALSE;
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
- asic_is_arcturus(asic_id)) {
+ asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
return CU_FALSE;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/vcn_tests.c
new/libdrm-2.4.106/tests/amdgpu/vcn_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/vcn_tests.c 2021-04-07 16:09:24.179843000
+0200
+++ new/libdrm-2.4.106/tests/amdgpu/vcn_tests.c 2021-05-18 05:42:27.000000000
+0200
@@ -114,7 +114,7 @@
if (r != 0 || !info.available_rings ||
(family_id < AMDGPU_FAMILY_RV &&
(family_id == AMDGPU_FAMILY_AI &&
- chip_id != (chip_rev + 0x32)))) { /* Arcturus */
+ (chip_id - chip_rev) < 0x32))) { /* Arcturus */
printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
return CU_FALSE;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/tests/amdgpu/vm_tests.c
new/libdrm-2.4.106/tests/amdgpu/vm_tests.c
--- old/libdrm-2.4.105/tests/amdgpu/vm_tests.c 2021-04-07 16:09:24.179843000
+0200
+++ new/libdrm-2.4.106/tests/amdgpu/vm_tests.c 2021-05-18 05:42:27.000000000
+0200
@@ -30,6 +30,9 @@
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
+static uint32_t family_id;
+static uint32_t chip_id;
+static uint32_t chip_rev;
static void amdgpu_vmid_reserve_test(void);
static void amdgpu_vm_unaligned_map(void);
@@ -110,7 +113,11 @@
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
CU_ASSERT_EQUAL(r, 0);
- gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ?
+ family_id = device_handle->info.family_id;
+ chip_id = device_handle->info.chip_external_rev;
+ chip_rev = device_handle->info.chip_rev;
+
+ gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/libdrm-2.4.105/xf86drmMode.c
new/libdrm-2.4.106/xf86drmMode.c
--- old/libdrm-2.4.105/xf86drmMode.c 2021-04-07 16:09:24.183843000 +0200
+++ new/libdrm-2.4.106/xf86drmMode.c 2021-05-18 05:42:27.000000000 +0200
@@ -289,10 +289,8 @@
memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0]));
memcpy(f.pitches, pitches, 4 * sizeof(pitches[0]));
memcpy(f.offsets, offsets, 4 * sizeof(offsets[0]));
- if (modifier) {
- f.flags |= DRM_MODE_FB_MODIFIERS;
+ if (modifier)
memcpy(f.modifier, modifier, 4 * sizeof(modifier[0]));
- }
if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f)))
return ret;
