Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package gmmlib for openSUSE:Factory checked
in at 2021-11-30 23:15:57
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/gmmlib (Old)
and /work/SRC/openSUSE:Factory/.gmmlib.new.31177 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "gmmlib"
Tue Nov 30 23:15:57 2021 rev:16 rq:934606 version:21.3.3
Changes:
--------
--- /work/SRC/openSUSE:Factory/gmmlib/gmmlib.changes 2021-10-28
18:31:45.328426426 +0200
+++ /work/SRC/openSUSE:Factory/.gmmlib.new.31177/gmmlib.changes 2021-12-02
02:13:25.898996199 +0100
@@ -1,0 +2,6 @@
+Mon Nov 29 15:45:21 UTC 2021 - Bj??rn Lie <bjorn....@gmail.com>
+
+- Update to version 21.3.3:
+ * No upstream changelog available.
+
+-------------------------------------------------------------------
Old:
----
intel-gmmlib-21.2.2.tar.gz
New:
----
intel-gmmlib-21.3.3.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ gmmlib.spec ++++++
--- /var/tmp/diff_new_pack.3pqiYx/_old 2021-12-02 02:13:26.386994711 +0100
+++ /var/tmp/diff_new_pack.3pqiYx/_new 2021-12-02 02:13:26.390994698 +0100
@@ -19,13 +19,13 @@
%global somajor 11
%global libname libigdgmm%{somajor}
Name: gmmlib
-Version: 21.2.2
+Version: 21.3.3
Release: 0
Summary: Intel Graphics Memory Management Library Package
License: MIT
Group: Development/Libraries/C and C++
URL: https://github.com/intel/gmmlib
-Source0:
https://github.com/intel/gmmlib/archive/intel-gmmlib-%{version}.tar.gz
+Source0: %{url}/archive/intel-gmmlib-%{version}.tar.gz
Source1: baselibs.conf
BuildRequires: cmake
BuildRequires: gcc-c++
++++++ intel-gmmlib-21.2.2.tar.gz -> intel-gmmlib-21.3.3.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
---
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
2021-08-24 11:31:41.000000000 +0200
+++
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/CachePolicy/GmmGen12dGPUCachePolicy.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -134,6 +134,7 @@
{
case IGFX_DG1:
case IGFX_XE_HP_SDV:
+ case IGFX_PVC:
StartMocsIdx = 1; // Index 0 is reserved for Error
break;
default:
@@ -147,7 +148,7 @@
CPTblIdx = IsSpecialMOCSUsage((GMM_RESOURCE_USAGE_TYPE)Usage,
SpecialMOCS);
}
- // Applicable upto only
+ // Applicable upto Xe_HP only
if(pCachePolicy[Usage].HDCL1 &&
(GFX_GET_CURRENT_PRODUCT(pGmmGlobalContext->GetPlatformInfo().Platform) <=
IGFX_XE_HP_SDV))
{
@@ -166,12 +167,18 @@
UsageEle.L3.SCC = (uint16_t)pCachePolicy[Usage].L3_SCC;
}
+
if(GFX_GET_CURRENT_PRODUCT(pGmmGlobalContext->GetPlatformInfo().Platform) ==
IGFX_PVC)
+ {
+ pCachePolicy[Usage].GlbGo = 0;
+ pCachePolicy[Usage].UcLookup = 0;
+ }
// Go/Lookup
// N/A for SpecialMOCS
- // N/A for DG1, RKL
+ // N/A for DG1, RKL, PVC
// Applicable for IGFX_XE_HP_SDV only
if(!SpecialMOCS &&
- (FROMPRODUCT(XE_HP_SDV)))
+ (FROMPRODUCT(XE_HP_SDV)) &&
+
(GFX_GET_CURRENT_PRODUCT(pGmmGlobalContext->GetPlatformInfo().Platform) !=
IGFX_PVC))
{
if(pCachePolicy[Usage].L3 == 0)
{
@@ -369,7 +376,20 @@
CurrentMaxSpecialMocsIndex = 63;
}
+ else if
(GFX_GET_CURRENT_PRODUCT(pGmmGlobalContext->GetPlatformInfo().Platform) ==
IGFX_PVC)
+ {
+ //Default MOCS Table
+ for(int index = 0; index < GMM_MAX_NUMBER_MOCS_INDEXES; index++)
+ { // Index ESC SCC L3CC Go
LookUp HDCL1
+ GMM_DEFINE_MOCS( index , 0 , 0 , 3 , 0 , 0
, 0 )
+ }
+ // Fixed MOCS Table
+ // Index ESC SCC L3CC Go LookUp
HDCL1
+ GMM_DEFINE_MOCS( 1 , 0 , 0 , 1 , 0 , 0 , 0 )
+ GMM_DEFINE_MOCS( 2 , 0 , 0 , 3 , 0 , 0 , 0 )
+ CurrentMaxMocsIndex = 2;
+ }
// clang-format on
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/GlobalInfo/GmmInfo.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/GlobalInfo/GmmInfo.cpp
--- old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/GlobalInfo/GmmInfo.cpp
2021-08-24 11:31:41.000000000 +0200
+++ new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/GlobalInfo/GmmInfo.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -501,6 +501,11 @@
{
SkuTable.FtrTileY = true;
}
+
+ if(GFX_GET_CURRENT_PRODUCT(this->GetPlatformInfo().Platform) == IGFX_PVC)
+ {
+ SkuTable.Ftr57bGPUAddressing = true;
+ }
}
#ifdef __GMM_KMD__ /*LINK CONTEXT TO GLOBAL*/
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Platform/GmmGen12Platform.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Platform/GmmGen12Platform.cpp
--- old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Platform/GmmGen12Platform.cpp
2021-08-24 11:31:41.000000000 +0200
+++ new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Platform/GmmGen12Platform.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -313,6 +313,11 @@
Data.NoOfBitsSupported = 46;
Data.HighestAcceptablePhysicalAddress = GFX_MASK_LARGE(0, 45);
}
+ else if(GFX_GET_CURRENT_PRODUCT(Data.Platform) == IGFX_PVC)
+ {
+ Data.NoOfBitsSupported = 52;
+ Data.HighestAcceptablePhysicalAddress = GFX_MASK_LARGE(0, 51);
+ }
}
void GmmLib::PlatformInfoGen12::ApplyExtendedTexAlign(uint32_t CCSMode,
ALIGNMENT &UnitAlign)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Resource/GmmResourceInfoCommonEx.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Resource/GmmResourceInfoCommonEx.cpp
---
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Resource/GmmResourceInfoCommonEx.cpp
2021-08-24 11:31:41.000000000 +0200
+++
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Resource/GmmResourceInfoCommonEx.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -75,8 +75,9 @@
CreateParams.Flags.Info.TiledX = true;
}
}
- else
- {
+ //Auto-tiling selection if not Linear already
+ else if(CreateParams.Flags.Info.Linear == 0)
+ {
// Xe_HP onwards.
if((CreateParams.Flags.Info.TiledYs +
CreateParams.Flags.Info.TiledYf +
@@ -119,8 +120,9 @@
}
}
}
- else
- {
+ //Convert non linear & non-tiledX tiling selection by client to proper
tiling.
+ else if(CreateParams.Flags.Info.Linear +
CreateParams.Flags.Info.TiledX == 0)
+ {
if(!pGmmGlobalContext->GetSkuTable().FtrTileY)
{
__GMM_ASSERT(!(CreateParams.Flags.Info.TiledYs ||
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Texture/GmmGen9Texture.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Texture/GmmGen9Texture.cpp
--- old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Texture/GmmGen9Texture.cpp
2021-08-24 11:31:41.000000000 +0200
+++ new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Texture/GmmGen9Texture.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -592,7 +592,7 @@
// Color Surf with MSAA Enabled Mutiply 4
if(GMM_IS_64KB_TILE(pTexInfo->Flags) &&
(!pGmmGlobalContext->GetSkuTable().FtrTileY) &&
- ((pTexInfo->MSAA.NumSamples == 8) && (pTexInfo->MSAA.NumSamples ==
16)) &&
+ ((pTexInfo->MSAA.NumSamples == 8) || (pTexInfo->MSAA.NumSamples ==
16)) &&
((pTexInfo->Flags.Gpu.Depth == 0) &&
(pTexInfo->Flags.Gpu.SeparateStencil == 0)))
{
ArrayQPitch *= 4; /* Aligned height of 4 samples */
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.cpp
---
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.cpp
2021-08-24 11:31:41.000000000 +0200
+++
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -176,3 +176,36 @@
}
}
}
+
+void CTestXe_HP_CachePolicy::SetUpPlatformVariant(PRODUCT_FAMILY platform)
+{
+ printf("%s\n", __FUNCTION__);
+ CTestGen12dGPUCachePolicy::SetUpGen12dGPUVariant(platform);
+}
+
+void CTestXe_HP_CachePolicy::TearDownPlatformVariant()
+{
+ printf("%s\n", __FUNCTION__);
+ CTestGen12dGPUCachePolicy::TearDownGen12dGPUVariant();
+}
+
+void CTestXe_HP_CachePolicy::CheckL3CachePolicy()
+{
+ printf("%s\n", __FUNCTION__);
+ CTestGen12dGPUCachePolicy::CheckL3Gen12dGPUCachePolicy();
+}
+
+void CTestXe_HP_CachePolicy::SetUpTestCase()
+{
+}
+
+void CTestXe_HP_CachePolicy::TearDownTestCase()
+{
+}
+
+TEST_F(CTestXe_HP_CachePolicy, Test_PVC_CachePolicy)
+{
+ SetUpPlatformVariant(IGFX_PVC);
+ CheckL3CachePolicy();
+ TearDownPlatformVariant();
+}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.h
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.h
---
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.h
2021-08-24 11:31:41.000000000 +0200
+++
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/ULT/GmmGen12dGPUCachePolicyULT.h
2021-11-12 09:18:31.000000000 +0100
@@ -42,4 +42,16 @@
static void SetUpTestCase();
static void TearDownTestCase();
};
+
+class CTestXe_HP_CachePolicy : public CTestGen12dGPUCachePolicy
+{
+protected:
+ virtual void SetUpPlatformVariant(PRODUCT_FAMILY);
+ virtual void TearDownPlatformVariant();
+ virtual void CheckL3CachePolicy();
+
+public:
+ static void SetUpTestCase();
+ static void TearDownTestCase();
+};
#pragma once
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Utility/GmmLibObject.cpp
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Utility/GmmLibObject.cpp
--- old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/Utility/GmmLibObject.cpp
2021-08-24 11:31:41.000000000 +0200
+++ new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/Utility/GmmLibObject.cpp
2021-11-12 09:18:31.000000000 +0100
@@ -69,6 +69,8 @@
case IGFX_GEN12LP_CORE:
case IGFX_GEN12_CORE:
case IGFX_XE_HP_CORE:
+ case IGFX_XE_HPG_CORE:
+ case IGFX_XE_HPC_CORE:
return new GmmLib::PlatformInfoGen12(Platform);
break;
case IGFX_GEN11_CORE:
@@ -109,6 +111,8 @@
case IGFX_GEN12LP_CORE:
case IGFX_GEN12_CORE:
case IGFX_XE_HP_CORE:
+ case IGFX_XE_HPG_CORE:
+ case IGFX_XE_HPC_CORE:
if(pGmmGlobalContext->GetSkuTable().FtrLocalMemory)
{
pGmmCachePolicy = new
GmmLib::GmmGen12dGPUCachePolicy(CachePolicy);
@@ -180,6 +184,8 @@
case IGFX_GEN12LP_CORE:
case IGFX_GEN12_CORE:
case IGFX_XE_HP_CORE:
+ case IGFX_XE_HPG_CORE:
+ case IGFX_XE_HPC_CORE:
default:
return new GmmGen12TextureCalc();
break;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/inc/External/Common/GmmCommonExt.h
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/inc/External/Common/GmmCommonExt.h
---
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/inc/External/Common/GmmCommonExt.h
2021-08-24 11:31:41.000000000 +0200
+++
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/inc/External/Common/GmmCommonExt.h
2021-11-12 09:18:31.000000000 +0100
@@ -117,6 +117,9 @@
#define GMM_GFX_ADDRESS_CANONIZE(a) (((int64_t)(a) << (64 - 48)) >> (64 -
48)) // TODO(Minor): When GMM adds platform-dependent VA size caps, change from
48.
#define GMM_GFX_ADDRESS_DECANONIZE(a) ((uint64_t)(a) & (((uint64_t) 1 << 48)
- 1)) // "
+#define GMM_GFX_PLATFORM_VA_SIZE(pClientContext)
(((pClientContext)->GetLibContext()->GetSkuTable().Ftr57bGPUAddressing) ? 57 :
48)
+#define VASize(pCC)
GMM_GFX_PLATFORM_VA_SIZE(pCC)
+
#define GMM_BIT_RANGE(endbit, startbit) ((endbit)-(startbit)+1)
#define GMM_BIT(bit) (1)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/inc/External/Common/GmmLibDll.h
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/inc/External/Common/GmmLibDll.h
---
old/gmmlib-intel-gmmlib-21.2.2/Source/GmmLib/inc/External/Common/GmmLibDll.h
2021-08-24 11:31:41.000000000 +0200
+++
new/gmmlib-intel-gmmlib-21.3.3/Source/GmmLib/inc/External/Common/GmmLibDll.h
2021-11-12 09:18:31.000000000 +0100
@@ -76,6 +76,6 @@
}
#endif
-#ifdef _WIN32
-typedef GMM_STATUS (APIENTRY *pfnGmmEntry)(GmmExportEntries *);
-#endif
+typedef GMM_STATUS (GMM_STDCALL *pfnGmmEntry)(GmmExportEntries *);
+typedef GMM_STATUS (GMM_STDCALL *pfnGmmInit)(GMM_INIT_IN_ARGS *,
GMM_INIT_OUT_ARGS *);
+typedef void (GMM_STDCALL *pfnGmmDestroy)(GMM_INIT_OUT_ARGS *);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/inc/common/igfxfmid.h
new/gmmlib-intel-gmmlib-21.3.3/Source/inc/common/igfxfmid.h
--- old/gmmlib-intel-gmmlib-21.2.2/Source/inc/common/igfxfmid.h 2021-08-24
11:31:41.000000000 +0200
+++ new/gmmlib-intel-gmmlib-21.3.3/Source/inc/common/igfxfmid.h 2021-11-12
09:18:31.000000000 +0100
@@ -73,6 +73,8 @@
IGFX_DG1 = 1210,
IGFX_XE_HP_SDV = 1250,
+ IGFX_DG2 = 1270,
+ IGFX_PVC = 1271,
IGFX_MAX_PRODUCT,
IGFX_GENNEXT = 0x7ffffffe,
@@ -126,9 +128,11 @@
IGFX_GEN11LP_CORE = 16, //Gen11 LP Family
IGFX_GEN12_CORE = 17, //Gen12 Family
IGFX_GEN12LP_CORE = 18, //Gen12 LP Family
- IGFX_XE_HP_CORE =0x0c05, //XE_HP family
-
- //Please add new GENs BEFORE THIS !
+ IGFX_XE_HP_CORE = 0x0c05, //XE_HP family
+ IGFX_XE_HPG_CORE = 0x0c07, // XE_HPG Family
+ IGFX_XE_HPC_CORE = 0x0c08, // XE_HPC Family
+
+ //Please add new GENs BEFORE THIS !
IGFX_MAX_CORE,
IGFX_GENNEXT_CORE = 0x7ffffffe, //GenNext
@@ -284,7 +288,8 @@
// This macro returns true if the product family is discrete
#define GFX_IS_DISCRETE_FAMILY(p) ( ( GFX_GET_CURRENT_PRODUCT(p) ==
IGFX_DG1 ) || \
- ( GFX_GET_CURRENT_PRODUCT(p) ==
IGFX_XE_HP_SDV ))
+ ( GFX_GET_CURRENT_PRODUCT(p) ==
IGFX_XE_HP_SDV ) || \
+ ( GFX_GET_CURRENT_PRODUCT(p) ==
IGFX_DG2 ) )
// These macros return true/false depending on the current render family.
#define GFX_IS_NAPA_RENDER_FAMILY(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN3_CORE ) || \
@@ -303,6 +308,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_5_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN5_CORE ) || \
@@ -316,6 +324,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_5_75_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN5_75_CORE ) || \
@@ -327,6 +338,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_6_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN6_CORE ) || \
@@ -336,6 +350,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN9_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_7_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN7_CORE ) || \
@@ -345,6 +362,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_7_5_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN7_5_CORE ) || \
@@ -353,6 +373,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_8_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN8_CORE ) || \
@@ -360,6 +383,9 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_8_CHV_OR_LATER(p) ( ( GFX_GET_CURRENT_PRODUCT(p) ==
IGFX_CHERRYVIEW ) || \
@@ -367,21 +393,33 @@
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_9_OR_LATER(p) ( ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN9_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
-#define GFX_IS_GEN_10_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
- ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
- ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+#define GFX_IS_GEN_10_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN10_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
-#define GFX_IS_GEN_11_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
+#define GFX_IS_GEN_11_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN11_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GEN12_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HP_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPG_CORE ) || \
+ ( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_XE_HPC_CORE ) || \
( GFX_GET_CURRENT_RENDERCORE(p) ==
IGFX_GENNEXT_CORE ) )
#define GFX_IS_GEN_12_OR_LATER(p) (( GFX_GET_CURRENT_RENDERCORE(p) >=
IGFX_GEN12_CORE ))
#define GFX_IS_ATOM_PRODUCT_FAMILY(p) ( GFX_IS_PRODUCT(p, IGFX_VALLEYVIEW)
|| \
@@ -1603,6 +1641,35 @@
#define PCH_DEV_ID_519E 0x519E
#define PCH_DEV_ID_519F 0x519F
+//PVC Device ID
+#define DEV_ID_0BD0 0x0BD0
+#define DEV_ID_0BD5 0x0BD5
+
+// Macro to identify PVC device ID
+#define GFX_IS_XT_CONFIG(d) (d == DEV_ID_0BD5)
+
+//DG2 Device IDs
+#define DEV_ID_4F80 0x4F80
+#define DEV_ID_4F81 0x4F81
+#define DEV_ID_4F82 0x4F82
+#define DEV_ID_4F83 0x4F83
+#define DEV_ID_4F84 0x4F84
+#define DEV_ID_4F87 0x4F87
+#define DEV_ID_4F88 0x4F88
+#define DEV_ID_5690 0x5690
+#define DEV_ID_5691 0x5691
+#define DEV_ID_5692 0x5692
+#define DEV_ID_5693 0x5693
+#define DEV_ID_5694 0x5694
+#define DEV_ID_5695 0x5695
+#define DEV_ID_56A0 0x56A0
+#define DEV_ID_56A1 0x56A1
+#define DEV_ID_56A2 0x56A2
+#define DEV_ID_56A5 0x56A5
+#define DEV_ID_56A6 0x56A6
+#define DEV_ID_56B0 0x56B0
+#define DEV_ID_56B1 0x56B1
+
#define MGM_HAS 0
//#define SDG_HAS 1 //Reserve place for Springdale-G HAS
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/gmmlib-intel-gmmlib-21.2.2/Source/inc/common/sku_wa.h
new/gmmlib-intel-gmmlib-21.3.3/Source/inc/common/sku_wa.h
--- old/gmmlib-intel-gmmlib-21.2.2/Source/inc/common/sku_wa.h 2021-08-24
11:31:41.000000000 +0200
+++ new/gmmlib-intel-gmmlib-21.3.3/Source/inc/common/sku_wa.h 2021-11-12
09:18:31.000000000 +0100
@@ -105,7 +105,8 @@
unsigned int FtrDisplayXTiling : 1; // Fallback to
Legacy TileX Display, used for Pre-SI platforms.
unsigned int FtrMultiTileArch : 1;
unsigned int FtrDisplayPageTables : 1; // Display Page
Tables: 2-Level Page walk for Displayable Frame buffers in GGTT.
- };
+ unsigned int Ftr57bGPUAddressing : 1; // 57b GPUVA
support eg: PVC
+ };
struct //_sku_3d
