Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package dynamips for openSUSE:Factory checked in at 2022-05-24 21:53:41 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/dynamips (Old) and /work/SRC/openSUSE:Factory/.dynamips.new.2254 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "dynamips" Tue May 24 21:53:41 2022 rev:25 rq:979038 version:0.2.22 Changes: -------- --- /work/SRC/openSUSE:Factory/dynamips/dynamips.changes 2020-01-06 15:21:29.216459106 +0100 +++ /work/SRC/openSUSE:Factory/.dynamips.new.2254/dynamips.changes 2022-05-24 21:53:42.473720541 +0200 @@ -1,0 +2,6 @@ +Tue May 24 16:15:37 UTC 2022 - Martin Hauke <[email protected]> + +- Update to version 0.2.22 + * Fix stack alignment for JIT function call targets. + +------------------------------------------------------------------- Old: ---- dynamips-0.2.21.tar.gz New: ---- dynamips-0.2.22.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ dynamips.spec ++++++ --- /var/tmp/diff_new_pack.P9WdfT/_old 2022-05-24 21:53:43.177720969 +0200 +++ /var/tmp/diff_new_pack.P9WdfT/_new 2022-05-24 21:53:43.181720972 +0200 @@ -1,7 +1,7 @@ # # spec file for package dynamips # -# Copyright (c) 2019 SUSE LINUX GmbH, Nuernberg, Germany. +# Copyright (c) 2022 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: dynamips -Version: 0.2.21 +Version: 0.2.22 Release: 0 Summary: Cisco router Emulator License: GPL-2.0-or-later ++++++ define-s390x-arch.patch ++++++ --- /var/tmp/diff_new_pack.P9WdfT/_old 2022-05-24 21:53:43.201720984 +0200 +++ /var/tmp/diff_new_pack.P9WdfT/_new 2022-05-24 21:53:43.205720987 +0200 @@ -1,8 +1,10 @@ ---- dynamips-0.2.16/common/dynamips_common.h 2016-03-16 05:05:47.000000000 -0400 -+++ dynamips-0.2.16/common/dynamips_common.h 2017-02-28 10:47:30.000000000 -0500 -@@ -65,6 +65,8 @@ - #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN - #elif defined(__arm__) || defined (__aarch64__) +diff --git a/common/dynamips_common.h b/common/dynamips_common.h +index 0f72f53..ca3a184 100644 +--- a/common/dynamips_common.h ++++ b/common/dynamips_common.h +@@ -71,6 +71,8 @@ + #define ARCH_BYTE_ORDER ARCH_BIG_ENDIAN + #elif defined(__riscv) || defined(__riscv__) #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN +#elif defined(__s390x__) +#define ARCH_BYTE_ORDER ARCH_BIG_ENDIAN ++++++ dynamips-0.2.21.tar.gz -> dynamips-0.2.22.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/.circleci/config.yml new/dynamips-0.2.22/.circleci/config.yml --- old/dynamips-0.2.21/.circleci/config.yml 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/.circleci/config.yml 2022-05-24 05:56:03.000000000 +0200 @@ -1,9 +1,9 @@ -# iOS CircleCI 2.0 configuration file -version: 2 +# iOS CircleCI 2.1 configuration file +version: 2.1 jobs: build: macos: - xcode: "9.4.0" + xcode: "11.7.0" steps: - checkout @@ -13,15 +13,18 @@ command: | sudo systemsetup -settimezone Europe/Warsaw echo "Today is $(date +"%Y-%m-%d %T")" + echo 'export HOMEBREW_NO_AUTO_UPDATE=1' >> ~/.envs - run: name: Install libelf command: | + source ~/.envs brew install libelf - run: name: Install cmake command: | + source ~/.envs brew install cmake - run: diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/CMakeLists.txt new/dynamips-0.2.22/CMakeLists.txt --- old/dynamips-0.2.21/CMakeLists.txt 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/CMakeLists.txt 2022-05-24 05:56:03.000000000 +0200 @@ -25,7 +25,7 @@ message ( STATUS "CMAKE_MODULE_PATH=${CMAKE_MODULE_PATH}" ) project ( dynamips C ) -set ( DYNAMIPS_VERSION_TRAIN 0.2.21 ) +set ( DYNAMIPS_VERSION_TRAIN 0.2.22 ) set ( DYNAMIPS_VERSION_SUB ) include ( utils ) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/ChangeLog new/dynamips-0.2.22/ChangeLog --- old/dynamips-0.2.21/ChangeLog 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/ChangeLog 2022-05-24 05:56:03.000000000 +0200 @@ -3019,3 +3019,12 @@ ---------- * Fix SEGV during snprintf and localtime_r. Fixes #91 + ++--------------------+ +| Release: v0.2.22 | ++--------------------+ + +24-05-2022 +---------- + +* Fix stack alignment for JIT function call targets. Fixes #128 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/README.md new/dynamips-0.2.22/README.md --- old/dynamips-0.2.21/README.md 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/README.md 2022-05-24 05:56:03.000000000 +0200 @@ -148,14 +148,9 @@ * git tag the release ### Useful Information -Website: http://www.gns3.net/dynamips/ -Forum: http://forum.gns3.net/ +Forum: https://gns3.com/community Repository: https://github.com/GNS3/dynamips Bugtracker: https://github.com/GNS3/dynamips/issues - -### Original websites -http://www.ipflow.utc.fr/index.php/Cisco_7200_Simulator -http://www.ipflow.utc.fr/blog/ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/RELEASE-NOTES new/dynamips-0.2.22/RELEASE-NOTES --- old/dynamips-0.2.21/RELEASE-NOTES 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/RELEASE-NOTES 2022-05-24 05:56:03.000000000 +0200 @@ -1,19 +1,19 @@ Release Notes for Cisco router simulator (Dynamips) =================================================== -Version: v0.2.21 +Version: v0.2.22 -Release date: Friday, July 12th, 2019 (2019-07-12) +Release date: Tuesday, May 24th, 2022 (2022-05-24) -Source code: https://github.com/GNS3/dynamips/tree/v0.2.21 +Source code: https://github.com/GNS3/dynamips/tree/v0.2.22 License: GNU GPLv2 -What's New since v0.2.20 +What's New since v0.2.21 ======================== -* Fix SEGV during snprintf and localtime_r. Fixes #91 +* Fix stack alignment for JIT function call targets. Fixes #128 Known Issues diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/appveyor.yml new/dynamips-0.2.22/appveyor.yml --- old/dynamips-0.2.21/appveyor.yml 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/appveyor.yml 2022-05-24 05:56:03.000000000 +0200 @@ -13,7 +13,7 @@ install: - 'appveyor DownloadFile http://cygwin.com/setup-%CYG_ARCH%.exe -FileName setup.exe' - 'setup.exe -qnNdO -R "%CYG_ROOT%" -s "%CYG_MIRROR%" -l "%CYG_CACHE%" -P make -P gcc-core -P cmake >NUL' - - 'appveyor DownloadFile http://www.mr511.de/software/libelf-0.8.13.tar.gz' + - 'appveyor DownloadFile http://ftp.slackware.com/pub/gsb/gsb64-2.30_slackware64-13.1/source/l/libelf/libelf-0.8.13.tar.gz' - 'mkdir libelf && tar xvzf libelf-0.8.13.tar.gz -C libelf' - '%CYG_ROOT%/bin/bash -lc "cd $APPVEYOR_BUILD_FOLDER/libelf/libelf-0.8.13 && ./configure && make && make install' - 'cinst 7zip.commandline' diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/common/cisco_card.c new/dynamips-0.2.22/common/cisco_card.c --- old/dynamips-0.2.21/common/cisco_card.c 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/common/cisco_card.c 2022-05-24 05:56:03.000000000 +0200 @@ -201,7 +201,7 @@ struct cisco_nio_binding *nb; if (card != NULL) { - fprintf(fd,"vm add_slot_binding %s %u %u %s\n", + fprintf(fd,"vm slot_add_binding %s %u %u %s\n", vm->name,card->slot_id,card->subslot_id,card->dev_type); for(nb=card->nio_list;nb;nb=nb->next) { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/common/dynamips.c new/dynamips-0.2.22/common/dynamips.c --- old/dynamips-0.2.21/common/dynamips.c 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/common/dynamips.c 2022-05-24 05:56:03.000000000 +0200 @@ -73,7 +73,7 @@ const char *sw_version = DYNAMIPS_VERSION"-"JIT_ARCH; /* Software version tag */ -const char *sw_version_tag = "2019071212"; +const char *sw_version_tag = "2022052400"; /* Hypervisor */ int hypervisor_mode = 0; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/common/dynamips_common.h new/dynamips-0.2.22/common/dynamips_common.h --- old/dynamips-0.2.21/common/dynamips_common.h 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/common/dynamips_common.h 2022-05-24 05:56:03.000000000 +0200 @@ -65,6 +65,12 @@ #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN #elif defined(__arm__) || defined (__aarch64__) #define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN +#elif defined(__ppc64__) +#define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN +#elif defined(__s390x__) +#define ARCH_BYTE_ORDER ARCH_BIG_ENDIAN +#elif defined(__riscv) || defined(__riscv__) +#define ARCH_BYTE_ORDER ARCH_LITTLE_ENDIAN #endif #ifndef ARCH_BYTE_ORDER diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/snapcraft.yaml new/dynamips-0.2.22/snapcraft.yaml --- old/dynamips-0.2.21/snapcraft.yaml 1970-01-01 01:00:00.000000000 +0100 +++ new/dynamips-0.2.22/snapcraft.yaml 2022-05-24 05:56:03.000000000 +0200 @@ -0,0 +1,27 @@ +name: dynamips +version: git +summary: Dynamips +description: | + Dynamips is an emulator designed to run Cisco IOS images. +base: core18 +confinement: strict + +parts: + dynamips: + plugin: cmake + source: . + build-packages: + - gcc + - cmake + - libelf-dev + - libpcap-dev + stage-packages: + - libelf1 + - libpcap0.8 + +apps: + dynamips: + command: dynamips + plugs: + - network + - network-bind diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/stable/mips_mts.c new/dynamips-0.2.22/stable/mips_mts.c --- old/dynamips-0.2.21/stable/mips_mts.c 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/stable/mips_mts.c 2022-05-24 05:56:03.000000000 +0200 @@ -142,6 +142,7 @@ /* === MIPS Memory Operations ============================================= */ /* LB: Load Byte */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -153,6 +154,7 @@ } /* LBU: Load Byte Unsigned */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lbu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -164,6 +166,7 @@ } /* LH: Load Half-Word */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -175,6 +178,7 @@ } /* LHU: Load Half-Word Unsigned */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lhu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -186,6 +190,7 @@ } /* LW: Load Word */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -197,6 +202,7 @@ } /* LWU: Load Word Unsigned */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lwu)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -208,6 +214,7 @@ } /* LD: Load Double-Word */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(ld)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -219,6 +226,7 @@ } /* SB: Store Byte */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sb)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -230,6 +238,7 @@ } /* SH: Store Half-Word */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sh)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -241,6 +250,7 @@ } /* SW: Store Word */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sw)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -252,6 +262,7 @@ } /* SD: Store Double-Word */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sd)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -263,6 +274,7 @@ } /* LDC1: Load Double-Word To Coprocessor 1 */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(ldc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -274,6 +286,7 @@ } /* LWL: Load Word Left */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lwl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t r_mask,naddr; @@ -297,6 +310,7 @@ } /* LWR: Load Word Right */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(lwr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t r_mask,naddr; @@ -321,6 +335,7 @@ } /* LDL: Load Double-Word Left */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(ldl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t r_mask,naddr; @@ -343,6 +358,7 @@ } /* LDR: Load Double-Word Right */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(ldr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t r_mask,naddr; @@ -365,6 +381,7 @@ } /* SWL: Store Word Left */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(swl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t d_mask,naddr; @@ -389,6 +406,7 @@ } /* SWR: Store Word Right */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(swr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t d_mask,naddr; @@ -413,6 +431,7 @@ } /* SDL: Store Double-Word Left */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sdl)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t d_mask,naddr; @@ -437,6 +456,7 @@ } /* SDR: Store Double-Word Right */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sdr)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t d_mask,naddr; @@ -461,6 +481,7 @@ } /* LL: Load Linked */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(ll)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -474,6 +495,7 @@ } /* SC: Store Conditional */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sc)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -489,6 +511,7 @@ } /* SDC1: Store Double-Word from Coprocessor 1 */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(sdc1)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int reg) { m_uint64_t data; @@ -500,6 +523,7 @@ } /* CACHE: Cache operation */ +__attribute__((force_align_arg_pointer)) fastcall void MTS_PROTO(cache)(cpu_mips_t *cpu,m_uint64_t vaddr,u_int op) { mips64_jit_tcb_t *block; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/dynamips-0.2.21/stable/ppc32_mem.c new/dynamips-0.2.22/stable/ppc32_mem.c --- old/dynamips-0.2.21/stable/ppc32_mem.c 2019-07-12 11:41:16.000000000 +0200 +++ new/dynamips-0.2.22/stable/ppc32_mem.c 2022-05-24 05:56:03.000000000 +0200 @@ -722,6 +722,7 @@ /* === PPC Memory Operations ============================================= */ /* LBZ: Load Byte Zero */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lbz(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -733,6 +734,7 @@ } /* LHZ: Load Half-Word Zero */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lhz(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -744,6 +746,7 @@ } /* LWZ: Load Word Zero */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lwz(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -755,6 +758,7 @@ } /* LWBR: Load Word Byte Reverse */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lwbr(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -766,6 +770,7 @@ } /* LHA: Load Half-Word Algebraic */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lha(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -777,6 +782,7 @@ } /* STB: Store Byte */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_stb(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -788,6 +794,7 @@ } /* STH: Store Half-Word */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_sth(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -799,6 +806,7 @@ } /* STW: Store Word */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_stw(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -810,6 +818,7 @@ } /* STWBR: Store Word Byte Reversed */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_stwbr(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -821,6 +830,7 @@ } /* LSW: Load String Word */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lsw(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -832,6 +842,7 @@ } /* STW: Store String Word */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_stsw(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -843,6 +854,7 @@ } /* LFD: Load Floating-Point Double */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_lfd(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -854,6 +866,7 @@ } /* STFD: Store Floating-Point Double */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_stfd(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int reg) { m_uint64_t data; @@ -865,6 +878,7 @@ } /* ICBI: Instruction Cache Block Invalidate */ +__attribute__((force_align_arg_pointer)) fastcall void ppc32_icbi(cpu_ppc_t *cpu,m_uint32_t vaddr,u_int op) { ppc32_jit_tcb_t *block;
