Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package ovmf for openSUSE:Factory checked in at 2022-08-25 15:33:00 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/ovmf (Old) and /work/SRC/openSUSE:Factory/.ovmf.new.2083 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "ovmf" Thu Aug 25 15:33:00 2022 rev:78 rq:998943 version:202205 Changes: -------- --- /work/SRC/openSUSE:Factory/ovmf/ovmf.changes 2022-07-18 18:33:04.329683647 +0200 +++ /work/SRC/openSUSE:Factory/.ovmf.new.2083/ovmf.changes 2022-08-25 15:33:03.283918945 +0200 @@ -1,0 +2,366 @@ +Tue Aug 23 13:00:42 UTC 2022 - Joey Lee <[email protected]> + +- Removed patches in ovmf-bsc1196879-sev-fix.patch which are merged to + edk2-stable202205: + - OvmfPkg/AmdSev: reserve snp pages + - de463163d9 edk2-stable202205-rc1~292 + - OvmfPkg/ResetVector: cache the SEV status MSR value + - 63c50d3ff2 edk2-stable202205-rc1~291 + - OvmfPkg/BaseMemEncryptLib: use the SEV_STATUS MSR + - f1d1c337e7 edk2-stable202205-rc1~290 + +------------------------------------------------------------------- +Tue Aug 16 05:20:44 UTC 2022 - Joey Lee <[email protected]> + +- Update to edk2-stable202205 + - Features (https://github.com/tianocore/edk2/releases): + Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg + IntelFsp2Pkg: BaseFspCommonLib Support for X64 Build + Add PrmPkg + BaseTools Enhance GenFw to support PRM GCC build + Enable Intel TDX in OvmfPkg + Generate CloudHv target as PVH ELF binary + Add parallel hash feature into BaseCryptLib + Configure/Enable elliptic curve ciphers in OpenSSL + Add FMMT tool into edk2 BaseTools + Dynamic variable flash information cannot be passed in Standalone MM + - Patches (git log --oneline --reverse edk2-stable202202~..edk2-stable202205): + b24306f15d NetworkPkg: Fix incorrect unicode string of the AKM/Cipher Suite + 2dbed52506 ArmVirtPkg/ArmVirtMemoryInitPeiLib: avoid redundant cache invalidation + 54cddc3ad4 ArmVirtPkg/ArmVirtKvmTool: wire up configurable timeout + de463163d9 OvmfPkg/AmdSev: reserve snp pages + 63c50d3ff2 OvmfPkg/ResetVector: cache the SEV status MSR value in workarea + f1d1c337e7 OvmfPkg/BaseMemEncryptLib: use the SEV_STATUS MSR value from workarea + b1b89f9009 MdeModulePkg: Correct high-memory use in NvmExpressDxe + 84338c0d49 MdeModulePkg: Replace Opcode with the corresponding instructions. + d3febfd9ad MdePkg: Replace Opcode with the corresponding instructions. + 7bc8b1d9f4 SourceLevelDebugPkg: Replace Opcode with the corresponding instructions. + 2aa107c0aa UefiCpuPkg: Replace Opcode with the corresponding instructions. + bbaa00dd01 MdePkg: Remove the macro definitions regarding Opcode. + 6a890db161 BaseTools: Upgrade the version of NASM tool + 497ac7b6d7 UefiPayloadPkg/PayloadLoaderPeim: Use INT64 as input parameter + dc39554d58 edk2/MdeModulePkg/Debuglib: Add Standalone MM support + 906242343f MdeModulePkg/GraphicsConsoleDxe: Check status to make sure no error + b422b0fcf9 EmulatorPkg/EmuGopDxe: Set ModeInfo after Open successfully + 589d51df26 MdeModulePkg/Usb/Keyboard.c: Don't request protocol before setting + b909b4ad09 OvmfPkg: Make the Xen ELF header generator more flexible + 0a707eb258 OvmfPkg: Xen: Use a new fdf include for the PVH ELF header + 0015a4e0a8 OvmfPkg: Xen: Generate fdf include file from ELF header generator + 9ac8c85d50 OvmfPkg: CloudHv: Remove VARS and CODE sections + e1c7f9b4e5 OvmfPkg: Generate CloudHv as a PVH ELF binary + d50d9e5549 OvmfPkg: CloudHv: Retrieve RSDP address from PVH + 82bfd2e86d OvmfPkg: CloudHv: Rely on PVH memmap instead of CMOS + b83d0a6438 OvmfPkg: CloudHv: Add README + 4a68176cb5 UefiCpuPkg: Extend SMM CPU Service with rendezvous support. + 949b8a3d97 Maintainers.txt: Add new reviewer for UefiPayloadPkg + 091b6a1197 UefiPayloadPkg: Add build option for Above 4G Memory + 4adc364c75 UefiPayloadPkg: Fix case of protocol + 79f2734e5a MdeModulePkg: Add a check for metadata size in NvmExpress Driver + af74efe494 UefiPayloadPkg: Make Boot Manager Key configurable + 62fa37fe7b BlSupportSmm: fix definition of SetSmrr() + 56530dec11 .pytool/Plugin/UncrustifyCheck: Output file diffs by default + 2aac8bb7ef .pytool: Update to newest pytools + c63ef58698 .azurepipelines: Updated python version + f06941cc46 MdeModulePkg: Add bRefClkFreq card attribute programming support + 2b175eeb6a RedfishPkg: fix memory leak issue + 10b4c8f3b7 Maintainers: Update Maintainers.txt for edk2 Redfish modules + 0fdd466c75 UefiCpuPkg/MpInitLib:remove optional in declaration + 52e09dcd7a UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm + a13dfc769b MdeModulePkg/DxeIpl: Create 5-level page table for long mode + c8ea48bdf9 DynamicTablesPkg: Fix serial port namespace path in DBG2 + 414cd2a4d5 BaseTools/GenFw: Enhance GenFw to support PRM GCC build + 33438f7354 EmulatorPkg/RedfishPlatformCredentialLib: Check EFI_SECURE_BOOT_MODE_NAME + 5b56c52b5c EmulatorPkg/RedfishPlatformCredentialLib: Don't stop Redfish service + 0531f61376 IntelFsp2Pkg: BaseFspDebugLibSerialPort Support for X64 + 411b3ff6dd IntelFsp2Pkg: BaseFspSwitchStackLib Support for X64 + b429959bb6 MdeModulePkg/SdMmcPciHcDxe: Make timeout for SD card configurable + 79a705fbaf UefiPayloadPkg: Hookup SD/MMC timeout + 28eeb08d86 MdePkg/Include: Smbios Specification 3.5.0 changes + c1e662101a CryptoPkg: Add new hash algorithm ParallelHash256HashAll in BaseCryptLib. + 267a92fef3 MdePkg/AcpiXX.h: Update Error Severity type for Generic Error Status Block + ec0b54849b IntelFsp2Pkg: BaseFspCommonLib Support for X64 + 5d8d8b5148 MdeModulePkg/NvmExpressDxe: fix check for Cap.Css + 69218d5d28 MdeModulePkg/NvmExpressPei: fix check for NVM command set + bf9230a9f3 BaseTools: Add the FeatureFlagExpression usage to the Source Section + 3115377bf0 BaseTools: Remove the redundant __FLEXIBLE_SIZE from PcdValueInit.c + 4a2e1000a1 CryptoPkg: update openssl submodule to 1.1.1n + 355515a06a CryptoPkg? Redefinition bug in CrtLibSupport.h. + 7b005f344e BaseTools: fix gcc12 warning + 85021f8cf2 BaseTools: fix gcc12 warning + 22130dcd98 Basetools: turn off gcc12 warning + ec30a4a0c3 BaseTools:Support decimal version number in ECC check + 3ef2071927 UefiCpuPkg: Update BFV searching algorithm in VTF0 + 691b178667 ShellPkg/AcpiView: Adds ACPI_PARSER bitfield parser + 40004ff9d5 ShellPkg/AcpiView: PrintFormatter for FADT Flags field + 7456990e8e MdeModulePkg/Ufs: bRefClkFreq attribute be programmed after fDeviceInit + 237c966396 UefiPayloadPkg/UefiPayloadPkg.ci.yaml: Remove duplicated entry + 76191052fd UefiPayloadPkg: Fix build error + 449eb01a8d UefiPayloadPkg: Fix architecture in the build instruction + c248802e40 UefiPayloadPkg: Fix PciHostBridgeLib + 2b4b8013fe UefiPayloadPkg/Library/PlatformBootManagerLib: Remove broken VGA detection + 55637a2894 UefiPayloadPkg: Make Boot Timeout configurable + 2268920afc .azurepipelines: Use Python 3.8 + c3ca70669e .azurepipelines: Use windows-2019 VM image + 3b0de44759 EmulatorPkg: Use windows-2019 VM image + 75628d27c0 OvmfPkg: Use windows-2019 VM image + b328bb54c6 BaseTools/Bin: Update GCC ARM compiler version + 3f0c788a5f MdePkg: Add Tdx.h + 77228269e7 MdePkg: Update Cpuid.h for Tdx + 818bc9596d MdePkg: Introduce basic Tdx functions in BaseLib + c3001cb744 MdePkg: Add TdxLib to wrap Tdx operations + eddcba40b5 UefiCpuPkg: Extend VmgExitLibNull to handle #VE exception + daf8f642f3 OvmfPkg: Extend VmgExitLib to handle #VE exception + de327f7d8a UefiCpuPkg/CpuExceptionHandler: Add base support for the #VE exception + ab9d790901 MdePkg: Add helper functions for Tdx guest in BaseIoLibIntrinsic + b6b2de8848 MdePkg: Support mmio for Tdx guest in BaseIoLibIntrinsic + d74e932681 MdePkg: Support IoFifo for Tdx guest in BaseIoLibIntrinsic + 3571fc906f MdePkg: Support IoRead/IoWrite for Tdx guest in BaseIoLibIntrinsic + 7bed7ae6c5 UefiCpuPkg: Support TDX in BaseXApicX2ApicLib + d983b102b3 MdePkg: Add macro to check SEV / TDX guest + 88da06ca76 UefiCpuPkg: Enable Tdx support in MpInitLib + 352eabdcd5 OvmfPkg: Add IntelTdx.h in OvmfPkg/Include/IndustryStandard + 6a608255bb OvmfPkg: Add TdxMailboxLib + 57bcfc3b06 OvmfPkg: Create initial version of PlatformInitLib + 102cafedad OvmfPkg/PlatformInitLib: Add hob functions + 9a9b33b3d6 OvmfPkg/PlatformPei: Move global variables to PlatformInfoHob + 5a2574a82e OvmfPkg/PlatformPei: Refactor MiscInitialization + 6d2ce5fd5c OvmfPkg/PlatformPei: Refactor MiscInitialization for CloudHV + 3dd47f9544 OvmfPkg/PlatformPei: Refactor AddressWidthInitialization + 432e4acd87 OvmfPkg/PlatformPei: Refactor MaxCpuCountInitialization + f3801cf26c OvmfPkg/PlatformPei: Refactor QemuUc32BaseInitialization + e510326245 OvmfPkg/PlatformPei: Refactor InitializeRamRegions + 12e860a1e8 OvmfPkg/PlatformPei: Refactor MemMapInitialization + cec82a64cf OvmfPkg/PlatformPei: Refactor NoexecDxeInitialization + f53f449f15 OvmfPkg/PlatformPei: Refactor MiscInitialization + 10460942ff OvmfPkg/PlatformInitLib: Create MemDetect.c + 96047b6663 OvmfPkg/PlatformInitLib: Move functions to Platform.c + b22ac35b75 OvmfPkg: Update PlatformInitLib to process Tdx hoblist + ccca1c2d5d OvmfPkg/Sec: Declare local variable as volatile in SecCoreStartupWithStack + 2b80269d98 OvmfPkg: Update Sec to support Tdx + 6b27c11690 OvmfPkg: Check Tdx in QemuFwCfgPei to avoid DMA operation + bec9104201 MdeModulePkg: Skip setting IA32_ERER.NXE if it has already been set + fd306d1dbc MdeModulePkg: Add PcdTdxSharedBitMask + cc3620f304 UefiCpuPkg: Update AddressEncMask in CpuPageTable + e23f8f52fd OvmfPkg: Update PlatformInitLib for Tdx guest + cf17156d7d OvmfPkg: Update PlatformPei to support Tdx guest + 9fdc70af6b OvmfPkg: Update AcpiPlatformDxe to alter MADT table + 5aa8018639 OvmfPkg/BaseMemEncryptTdxLib: Add TDX helper library + fae5c1464d OvmfPkg: Add TdxDxe driver + 07c721fea7 OvmfPkg/QemuFwCfgLib: Support Tdx in QemuFwCfgDxe + 2520182122 OvmfPkg: Update IoMmuDxe to support TDX + c2e7be4055 OvmfPkg: Rename XenTimerDxe to LocalApicTimerDxe + 299c44cd4f UefiCpuPkg: Setting initial-count register as the last step + c37cbc030d OvmfPkg: Switch timer in build time for OvmfPkg + 580a6b616b OvmfPkg: Add TdxWorkArea definition + 75942a52ae OvmfPkg: Add PrePiHobListPointerLibTdx + 4fe2678411 OvmfPkg: Add PeilessStartupLib + 1f29de4d20 OvmfPkg/IntelTdx: Add Sec to bring up both Legacy and Tdx guest + 55fda68a80 OvmfPkg: Update TdxDxe to set TDX PCDs + f674fa9cde OvmfPkg: Update DxeAcpiTimerLib to read HostBridgeDevId in PlatformInfoHob + 149ed8e421 OvmfPkg/IncompatiblePciDeviceSupportDxe: Refine the configuration + c477b2783f OvmfPkg/IncompatiblePciDeviceSupportDxe: Ignore OptionRom in Td guest + cb8349f01a MdeModulePkg: Update PciEnumeratorSupport to ignore OptionRom if needed + 44a53a3bdd OvmfPkg: Introduce IntelTdxX64 for TDVF Config-B + 7fda517c3d OvmfPkg: Add dependency of VariableSmm driver to make it work normally. + b953265a27 UefiPayloadPkg: Add a new DebugPrintErrorLevelLib instance + 0023e35cf4 UefiPayloadPkg: Change some configuration of the payload + 3e130e40fc UefiPayloadPkg: Consume the new added DebugPrintErrorLevelLib instance + f16b05a13b .pytool/Plugin/UncrustifyCheck: Update func to return absolute paths + dbfbaedb21 .pytool/Plugin/UncrustifyCheck: Add ignore file support + d932199d39 OvmfPkg: Revert Uncrustify formatting in VbeShim.h files + ad6816c319 OvmfPkg: Do not check VbeShim.h formatting with Uncrustify + d2998af211 PrmPkg: Add package and include headers + 5f76c3e471 PrmPkg: Add PrmConfig protocol interface + e189e01af2 PrmPkg/PrmContextBufferLib: Add initial library instance + 3f7af17c6b PrmPkg/PrmConfigDxe: Add initial driver + 9276e0d2b9 PrmPkg: Add initial PrmSamplePrintModule + c63905aba7 PrmPkg: Add initial PrmSampleMemoryAllocationModule + 27b1a840e4 PrmPkg: Add initial PrmSampleHardwareAccessModule + 7c41ec47ca PrmPkg: Add initial PrmSampleContextBufferModule + 97ab54c1b1 PrmPkg: Add initial package DSC file + d2cb6e67a4 Readme.md: Add initial content + e846797662 PrmPkg: Add ALLOCATE_CONTEXT_BUFFER_IN_FW build option + a6f8946bc9 PrmPkg: Enable variable growth for the PRM_MODULE_EXPORT macro + ef05955996 PrmPkg: Publish PRM operation region to support PRM ACPI _DSM invocation + f96517f4d0 PrmPkg: Export major/minor version in PRM module PE COFF header + 50e1432a40 PrmPkg: Add initial PrmSsdtInstallDxe module + a409f4b67d PrmPkg: Remove PRM Module Update Lock + 0797989c5d PrmPkg: Remove ALLOCATE_CONTEXT_BUFFER_IN_FW build flag + 0b469caff6 PrmPkg/PrmContextBuffer.h: Add ACPI parameter support structures + be2c927d7c PrmPkg/PrmLoaderDxe: Add ACPI parameter buffer support + c1a7a50f67 PrmPkg/PrmSampleContextBufferModule: Remove OS debug print requirement + 4c8486fd72 PrmPkg/PrmSampleHardwareAccessModule: Add non-print PRM handlers + 7217263514 PrmPkg/SampleAcpiParameterBufferModule: Add initial module + fec018624c PrmPkg/HardwareAccessModuleConfigLib: Add initial library + d10b8dc5d8 PrmPkg/Samples/Readme.md: Add initial file + 6b7dde7cdd PrmPkg: Refactor some PrmLoaderDxe functionality into libraries + 4348c72ad0 PrmPkg/Application/PrmInfo: Add initial application ++++ 169 more lines (skipped) ++++ between /work/SRC/openSUSE:Factory/ovmf/ovmf.changes ++++ and /work/SRC/openSUSE:Factory/.ovmf.new.2083/ovmf.changes Old: ---- edk2-edk2-stable202202.tar.gz openssl-1.1.1j.tar.gz openssl-1.1.1j.tar.gz.asc ovmf-bsc1196879-sev-fix.patch New: ---- edk2-edk2-stable202205.tar.gz openssl-1.1.1n.tar.gz openssl-1.1.1n.tar.gz.asc ovmf-Revert-MdeModulePkg-Replace-Opcode-with-the-correspo.patch ovmf-Revert-MdePkg-Remove-the-macro-definitions-regarding.patch ovmf-Revert-MdePkg-Replace-Opcode-with-the-corresponding-.patch ovmf-Revert-SourceLevelDebugPkg-Replace-Opcode-with-the-c.patch ovmf-Revert-UefiCpuPkg-Replace-Opcode-with-the-correspond.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ ovmf.spec ++++++ --- /var/tmp/diff_new_pack.8TFaoo/_old 2022-08-25 15:33:04.251921058 +0200 +++ /var/tmp/diff_new_pack.8TFaoo/_new 2022-08-25 15:33:04.259921076 +0200 @@ -18,11 +18,11 @@ %undefine _build_create_debug -%global openssl_version 1.1.1j +%global openssl_version 1.1.1n %global softfloat_version b64af41c3276f Name: ovmf -Version: 202202 +Version: 202205 Release: 0 Summary: Open Virtual Machine Firmware License: BSD-2-Clause-Patent @@ -51,9 +51,14 @@ Patch4: %{name}-disable-ia32-firmware-piepic.patch Patch5: %{name}-set-fixed-enroll-time.patch Patch6: %{name}-disable-brotli.patch -Patch7: %{name}-bsc1196879-sev-fix.patch -Patch8: %{name}-ignore-spurious-GCC-12-warning.patch -Patch9: %{name}-tools_def-add-fno-omit-frame-pointer-to-GCC48_-IA32-.patch +Patch7: %{name}-ignore-spurious-GCC-12-warning.patch +Patch8: %{name}-tools_def-add-fno-omit-frame-pointer-to-GCC48_-IA32-.patch +# PED-1359, because nasm-2.14 doesn't support corresponding instructions. +Patch9: %{name}-Revert-MdePkg-Remove-the-macro-definitions-regarding.patch +Patch10: %{name}-Revert-UefiCpuPkg-Replace-Opcode-with-the-correspond.patch +Patch11: %{name}-Revert-SourceLevelDebugPkg-Replace-Opcode-with-the-c.patch +Patch12: %{name}-Revert-MdePkg-Replace-Opcode-with-the-corresponding-.patch +Patch13: %{name}-Revert-MdeModulePkg-Replace-Opcode-with-the-correspo.patch BuildRequires: bc BuildRequires: cross-arm-binutils BuildRequires: cross-arm-gcc%{gcc_version} @@ -172,6 +177,10 @@ %patch7 -p1 %patch8 -p1 %patch9 -p1 +%patch10 -p1 +%patch11 -p1 +%patch12 -p1 +%patch13 -p1 # add openssl pushd CryptoPkg/Library/OpensslLib/openssl @@ -307,7 +316,7 @@ declare -A EXTRA_FLAGS_X64 EXTRA_FLAGS_X64=( - [ovmf-x86_64]="-p OvmfPkg/OvmfPkgX64.dsc -D FD_SIZE_2MB" + [ovmf-x86_64]="-p OvmfPkg/OvmfPkgX64.dsc -D FD_SIZE_4MB" [ovmf-x86_64-4m]="-p OvmfPkg/OvmfPkgX64.dsc -D FD_SIZE_4MB -D NETWORK_TLS_ENABLE" [ovmf-x86_64-smm]="-a IA32 -p OvmfPkg/OvmfPkgIa32X64.dsc -D FD_SIZE_4MB -D NETWORK_TLS_ENABLE -D SMM_REQUIRE -D EXCLUDE_SHELL" ) ++++++ edk2-edk2-stable202202.tar.gz -> edk2-edk2-stable202205.tar.gz ++++++ /work/SRC/openSUSE:Factory/ovmf/edk2-edk2-stable202202.tar.gz /work/SRC/openSUSE:Factory/.ovmf.new.2083/edk2-edk2-stable202205.tar.gz differ: char 14, line 1 ++++++ ovmf-Revert-MdeModulePkg-Replace-Opcode-with-the-correspo.patch ++++++ >From 8133c7453f729c7db7ee8850c491683f33e2c3d2 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" <[email protected]> Date: Tue, 23 Aug 2022 16:57:41 +0800 Subject: [PATCH 5/5] Revert "MdeModulePkg: Replace Opcode with the corresponding instructions." This reverts commit 84338c0d498555f860a480693ee8647a1795fba3. Signed-off-by: Lee, Chun-Yi <[email protected]> --- .../DebugSupportDxe/Ia32/AsmFuncs.nasm | 20 +++++++++++++++--- .../DebugSupportDxe/X64/AsmFuncs.nasm | 21 ++++++++++++++++--- 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm index 07fc912fe8..cfb418748f 100644 --- a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm +++ b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm @@ -1,7 +1,7 @@ ;/** @file ; Low leve IA32 specific debug support functions. ; -; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;**/ @@ -26,6 +26,20 @@ %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags +;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87, +;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver +;; MUST check the CPUID feature flags to see that these instructions are available +;; and fail to init if they are not. + +;; fxstor [edi] +%macro FXSTOR_EDI 0 + db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [edi] +%endmacro + +;; fxrstor [esi] +%macro FXRSTOR_ESI 0 + db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [esi] +%endmacro SECTION .data global ASM_PFX(OrigVector) @@ -334,7 +348,7 @@ ExtraPushDone: ; IMPORTANT!! The debug stack has been carefully constructed to ; insure that esp and edi are 16 byte aligned when we get here. ; They MUST be. If they are not, a GP fault will occur. - fxsave [edi] + FXSTOR_EDI ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear cld @@ -358,7 +372,7 @@ ExtraPushDone: ;; FX_SAVE_STATE_IA32 FxSaveState; mov esi, esp - fxrstor [esi] + FXRSTOR_ESI add esp, 512 ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm index c6c5e49189..9cc38a3128 100644 --- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm +++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm @@ -1,7 +1,7 @@ ;/** @file ; Low level x64 routines used by the debug support driver. ; -; Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;**/ @@ -26,6 +26,21 @@ %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags +;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87, +;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver +;; MUST check the CPUID feature flags to see that these instructions are available +;; and fail to init if they are not. + +;; fxstor [rdi] +%macro FXSTOR_RDI 0 + db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [rdi] +%endmacro + +;; fxrstor [rsi] +%macro FXRSTOR_RSI 0 + db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [rsi] +%endmacro + SECTION .data global ASM_PFX(OrigVector) @@ -366,7 +381,7 @@ ExtraPushDone: ; IMPORTANT!! The debug stack has been carefully constructed to ; insure that rsp and rdi are 16 byte aligned when we get here. ; They MUST be. If they are not, a GP fault will occur. - fxsave [rdi] + FXSTOR_RDI ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -389,7 +404,7 @@ ExtraPushDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - fxrstor [rsi] + FXRSTOR_RSI add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; -- 2.26.2 ++++++ ovmf-Revert-MdePkg-Remove-the-macro-definitions-regarding.patch ++++++ >From 083d51817e057037da5568fcc68f5d6bf449b169 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" <[email protected]> Date: Tue, 23 Aug 2022 16:56:21 +0800 Subject: [PATCH 1/5] Revert "MdePkg: Remove the macro definitions regarding Opcode." This reverts commit bbaa00dd01ed0df30e43a5a89fd2b0433d858b73. Signed-off-by: Lee, Chun-Yi <[email protected]> --- MdePkg/Include/Ia32/Nasm.inc | 26 +++++++++++++++++++++++++- MdePkg/Include/X64/Nasm.inc | 26 +++++++++++++++++++++++++- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc index e92c032bd8..c794d9ece3 100644 --- a/MdePkg/Include/Ia32/Nasm.inc +++ b/MdePkg/Include/Ia32/Nasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -9,6 +9,30 @@ ; ;------------------------------------------------------------------------------ +%macro SAVEPREVSSP 0 + DB 0xF3, 0x0F, 0x01, 0xEA +%endmacro + +%macro CLRSSBSY_EAX 0 + DB 0x67, 0xF3, 0x0F, 0xAE, 0x30 +%endmacro + +%macro RSTORSSP_EAX 0 + DB 0x67, 0xF3, 0x0F, 0x01, 0x28 +%endmacro + +%macro SETSSBSY 0 + DB 0xF3, 0x0F, 0x01, 0xE8 +%endmacro + +%macro READSSP_EAX 0 + DB 0xF3, 0x0F, 0x1E, 0xC8 +%endmacro + +%macro INCSSP_EAX 0 + DB 0xF3, 0x0F, 0xAE, 0xE8 +%endmacro + ; NASM provides built-in macros STRUC and ENDSTRUC for structure definition. ; For example, to define a structure called mytype containing a longword, ; a word, a byte and a string of bytes, you might code diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc index bb77ca6c32..cfb14edc94 100644 --- a/MdePkg/Include/X64/Nasm.inc +++ b/MdePkg/Include/X64/Nasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -9,6 +9,30 @@ ; ;------------------------------------------------------------------------------ +%macro SAVEPREVSSP 0 + DB 0xF3, 0x0F, 0x01, 0xEA +%endmacro + +%macro CLRSSBSY_RAX 0 + DB 0xF3, 0x0F, 0xAE, 0x30 +%endmacro + +%macro RSTORSSP_RAX 0 + DB 0xF3, 0x0F, 0x01, 0x28 +%endmacro + +%macro SETSSBSY 0 + DB 0xF3, 0x0F, 0x01, 0xE8 +%endmacro + +%macro READSSP_RAX 0 + DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8 +%endmacro + +%macro INCSSP_RAX 0 + DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8 +%endmacro + ; ; Macro for the PVALIDATE instruction, defined in AMD APM volume 3. ; NASM feature request URL: https://bugzilla.nasm.us/show_bug.cgi?id=3392753 -- 2.26.2 ++++++ ovmf-Revert-MdePkg-Replace-Opcode-with-the-corresponding-.patch ++++++ ++++ 1121 lines (skipped) ++++++ ovmf-Revert-SourceLevelDebugPkg-Replace-Opcode-with-the-c.patch ++++++ >From 44c1b4c12c3e1f4d751036c81e6eab1abf91bfe6 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" <[email protected]> Date: Tue, 23 Aug 2022 16:56:37 +0800 Subject: [PATCH 3/5] Revert "SourceLevelDebugPkg: Replace Opcode with the corresponding instructions." This reverts commit 7bc8b1d9f412507d579f21ea9af56fced81e7827. Signed-off-by: Lee, Chun-Yi <[email protected]> --- .../Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm | 6 +++--- .../Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm index b5e5a96e34..912256ba45 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Ia32/AsmFuncs.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -321,7 +321,7 @@ NoExtrPush: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. ; edx still contains result from CPUID above jz .2 - fxsave [edi] + db 0xf, 0xae, 00000111y ;fxsave [edi] .2: ;; save the exception data @@ -342,7 +342,7 @@ NoExtrPush: cpuid ; use CPUID to determine if FXSAVE/FXRESTOR are supported test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .3 - fxrstor [esi] + db 0xf, 0xae, 00001110y ; fxrstor [esi] .3: add esp, 512 diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm index b1019e017b..ccee120ca1 100644 --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/X64/AsmFuncs.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -293,7 +293,7 @@ NoExtrPush: rep stosq pop rcx mov rdi, rsp - fxsave [rdi] + db 0xf, 0xae, 00000111y ;fxsave [rdi] ;; save the exception data push qword [rbp + 16] @@ -314,7 +314,7 @@ NoExtrPush: add rsp, 8 mov rsi, rsp - fxrstor [rsi] + db 0xf, 0xae, 00001110y ; fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; -- 2.26.2 ++++++ ovmf-Revert-UefiCpuPkg-Replace-Opcode-with-the-correspond.patch ++++++ >From e8146da22109982083c12966ead99eb019a02601 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" <[email protected]> Date: Tue, 23 Aug 2022 16:56:29 +0800 Subject: [PATCH 2/5] Revert "UefiCpuPkg: Replace Opcode with the corresponding instructions." This reverts commit 2aa107c0aa2e1375651867c8df1b81ff64b67fce. Signed-off-by: Lee, Chun-Yi <[email protected]> --- UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm | 4 +-- .../Ia32/ExceptionHandlerAsm.nasm | 11 ++++---- .../Ia32/ExceptionTssEntryAsm.nasm | 9 ++++--- .../X64/ExceptionHandlerAsm.nasm | 14 +++++----- .../X64/Xcode5ExceptionHandlerAsm.nasm | 26 +++++++++---------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 6 ++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm | 4 +-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +-- 10 files changed, 43 insertions(+), 43 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm index a894ff53ad..66f8857fc0 100644 --- a/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm +++ b/UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------ ;* -;* Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> +;* Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> ;* SPDX-License-Identifier: BSD-2-Clause-Patent ;* ;* CpuAsm.nasm @@ -23,7 +23,7 @@ ASM_PFX(SetCodeSelector): push rcx lea rax, [setCodeSelectorLongJump] push rax - retfq + o64 retf setCodeSelectorLongJump: ret diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm index 3fe9aed1e8..58d5312899 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,13 +32,12 @@ ALIGN 8 ; exception handler stub table ; AsmIdtVectorBegin: -%assign Vector 0 %rep 32 - push byte %[Vector]; + db 0x6a ; push #VectorNum + db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum push eax mov eax, ASM_PFX(CommonInterruptEntry) jmp eax -%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -288,7 +287,7 @@ ErrorCodeAndVectorOnStack: test edx, BIT24 ; Test for FXSAVE/FXRESTOR support. ; edx still contains result from CPUID above jz .3 - fxsave [edi] + db 0xf, 0xae, 0x7 ;fxsave [edi] .3: ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear @@ -321,7 +320,7 @@ ErrorCodeAndVectorOnStack: ; are supported test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 - fxrstor [esi] + db 0xf, 0xae, 0xe ; fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm index b63cfeac6d..dd3f74d2aa 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionTssEntryAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -79,7 +79,8 @@ AsmExceptionEntryBegin: DoIret%[Vector]: iretd ASM_PFX(ExceptionTaskSwtichEntry%[Vector]): - push byte %[Vector] + db 0x6a ; push #VectorNum + db %[Vector] mov eax, ASM_PFX(CommonTaskSwtichEntryPoint) call eax mov esp, eax ; Restore stack top @@ -243,7 +244,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): clts sub esp, 512 mov edi, esp - fxsave [edi] + db 0xf, 0xae, 0x7 ;fxsave [edi] .3: ;; UINT32 ExceptionData; @@ -276,7 +277,7 @@ ASM_PFX(CommonTaskSwtichEntryPoint): test edx, BIT24 ; Test for FXSAVE/FXRESTOR support jz .4 mov esi, esp - fxrstor [esi] + db 0xf, 0xae, 0xe ; fxrstor [esi] .4: add esp, 512 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 9a806d1f86..2a5545ecfd 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -32,13 +32,12 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin: -%assign Vector 0 %rep 32 - push byte %[Vector] + db 0x6a ; push #VectorNum + db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum push rax mov rax, ASM_PFX(CommonInterruptEntry) jmp rax -%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -258,7 +257,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp - fxsave [rdi] + db 0xf, 0xae, 0x7 ;fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -285,7 +284,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - fxrstor [rsi] + db 0xf, 0xae, 0xE ; fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -372,7 +371,8 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - retfq + DB 0x48 ; prefix to composite "retq" with next "retf" + retf ; far return DoIret: iretq diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm index 9c72fa5815..84a12ddb88 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -54,13 +54,12 @@ SECTION .text ALIGN 8 AsmIdtVectorBegin: -%assign Vector 0 %rep 32 - push byte %[Vector] + db 0x6a ; push #VectorNum + db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum push rax mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry) jmp rax -%assign Vector Vector+1 %endrep AsmIdtVectorEnd: @@ -281,7 +280,7 @@ DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp - fxsave [rdi] + db 0xf, 0xae, 0x7 ;fxsave [rdi] ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -336,15 +335,15 @@ DrFinish: jz CetDone ; SSP should be 0xFC0 at this point mov rax, 0x04 ; advance past cs:lip:prevssp;supervisor shadow stack token - incsspq rax ; After this SSP should be 0xFE0 - saveprevssp ; now the shadow stack restore token will be created at 0xFB8 - rdsspq rax ; Read new SSP, SSP should be 0xFE8 + INCSSP_RAX ; After this SSP should be 0xFE0 + SAVEPREVSSP ; now the shadow stack restore token will be created at 0xFB8 + READSSP_RAX ; Read new SSP, SSP should be 0xFE8 sub rax, 0x10 - clrssbsy [rax] ; Clear token at 0xFD8, SSP should be 0 after this + CLRSSBSY_RAX ; Clear token at 0xFD8, SSP should be 0 after this sub rax, 0x20 - rstorssp [rax] ; Restore to token at 0xFB8, new SSP will be 0xFB8 + RSTORSSP_RAX ; Restore to token at 0xFB8, new SSP will be 0xFB8 mov rax, 0x01 ; Pop off the new save token created - incsspq rax ; SSP should be 0xFC0 now + INCSSP_RAX ; SSP should be 0xFC0 now CetDone: cli @@ -354,7 +353,7 @@ CetDone: ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - fxrstor [rsi] + db 0xf, 0xae, 0xE ; fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -441,7 +440,8 @@ DoReturn: push qword [rax + 0x18] ; save EFLAGS in new location mov rax, [rax] ; restore rax popfq ; restore EFLAGS - retfq + DB 0x48 ; prefix to composite "retq" with next "retf" + retf ; far return DoIret: iretq diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm index f1422fd30a..f7f2937faf 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -345,7 +345,7 @@ BITS 64 ; ; Far return into 32-bit mode ; - retfq +o64 retf BITS 32 CompatMode: @@ -507,7 +507,7 @@ NoSevEs: ; ; Far return into 32-bit mode ; - retfq +o64 retf BITS 32 PmEntry: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm index 9d66b9c5da..0919d6d05f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------- @@ -13,7 +13,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov eax, 1 - incsspd eax + INCSSP_EAX mov eax, cr4 btr eax, 23 ; clear CET diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 19de5f614e..167f5e14db 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -252,7 +252,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, eax - setssbsy + SETSSBSY CetDone: diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm index 8bbdbb31cc..3240f9d974 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Cet.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------- @@ -14,7 +14,7 @@ ASM_PFX(DisableCet): ; Skip the pushed data for call mov rax, 1 - incsspq rax + INCSSP_RAX mov rax, cr4 btr eax, 23 ; clear CET diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index d302ca8d01..0e154e5db9 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ; -; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2020, AMD Incorporated. All rights reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; @@ -279,7 +279,7 @@ CetInterruptDone: mov eax, 0x668 | CR4_CET mov cr4, rax - setssbsy + SETSSBSY CetDone: -- 2.26.2
