Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package CoreFreq for openSUSE:Factory checked in at 2022-11-04 17:38:06 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old) and /work/SRC/openSUSE:Factory/.CoreFreq.new.2275 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq" Fri Nov 4 17:38:06 2022 rev:16 rq:1033550 version:1.92.3 Changes: -------- --- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2022-08-23 14:29:48.771633432 +0200 +++ /work/SRC/openSUSE:Factory/.CoreFreq.new.2275/CoreFreq.changes 2022-11-04 17:41:57.919004635 +0100 @@ -1,0 +2,64 @@ +Fri Nov 4 14:32:03 UTC 2022 - Jan Engelhardt <jeng...@inai.de> + +- Repair deficient description grammar. + +------------------------------------------------------------------- +Fri Nov 4 13:35:40 UTC 2022 - Michael Pujos <pujos.mich...@gmail.com> + +- update to version 1.92.3 + - Export CPUID bits Intel Sierra Forest, Grand Ridge, Granite Rapids + and completes AMD64 Fn0000_0007_ECX_x0 + - [Features] WBNOINVD and CLZERO instructions + - Adding various Mitigation Mechanism aggregations: + IPRED_DIS_U, IPRED_DIS_S, RRSBA_DIS_U, RRSBA_DIS_S, BHI_DIS_S, MCDT_NO + - RDPID and UMIP capability fixed. + - [AMD] Perf. Mon. version based on CPUID_0x80000022.EAX.PerfMonV2 + - [AMD][Zen3+][Rembrandt] Trigger UMC and IOMMU decoders + - [AMD][Ryzen 5 6600H] Found voltage VID @ SMU 0x6f010 and 0x6f014 + - Introducing AMD Security Feature capabilities: + SKINIT, SEV, GMET, SEV-ES, SEV-SNP + - [AMD64] Non-architectural MSR: SPECULATIVE STORE BYPASS DISABLE + - [Intel][2nd & 3rd gen] Misc IMC optimizations + - [AMD][Rembrandt] Provides Vcore from a new formula. + - Dumping CPUID leaves from AMD64 Architecture Programmer???s Manual + - [Intel][HSW & BDW] Compute the DIMM banks + - [UI] Re-assigned keys to move or resize windows. + - [AMD][Zen] Uncore frequency: Improving the Memory Clock divisor + - [Intel][HSW & BDW][SKL] Make use of same function DimmWidthToRows + - [AMD][Zen3+][Rembrandt] Provides the thermal sensor. + - [AMD/Zen2 & Zen3] Removed the HSMP capability. + - [Intel][CML][RKL][TGL] Compute the DIMM Rows from CH_WIDTH + - [AMD/EPYC] Adding the CPUID of Zen4 Genoa architecture + - [AMD/Zen2] Introducing Mendocino architecture + - Changed MeteorLake/N to CPUID 06_B5 + - [Intel] Computes BIOS DRAM frequency based on PLL_REF100 + - [Intel][SNB/IVB/HSW/BDW] Improved BIOS DRAM frequency + - [Intel][SNB/IVB] DRAM frequency based on RAM_Select and FSB_Select + - [Intel][IVB] IMC specifications and optimizations. + - [Intel][SNB,IVB] Computes the DIMM A from DAS bit in MAD register + - [Intel][SNB,IVB,HSW,BDW] Rolling back changes to the DIMM topology + - [Intel][BDW][HSW] Query the IMC Power Down Mode + - [Intel][IVB][SNB] Attempt to decode the IMC third timings + - [AMD][Ryzen] Added AMD Ryzen 7 PRO 6860Z + - [AMD][F17h-F19h] Can toggle ON and OFF the Instruction Cache Unit + - [AMD] Checking the Ryzen "OEM Only" processors + - [Intel] Specification of 12th Gen. MSR registers capability + - [Intel] Adding Raptor Lake-S with CPUID 06_BF + - [AMD] Introducing Zen 4 / Raphael architecture + - [Intel][SNB,IVB,HSW] Attempt to assign the Rank per DIMM slot + - [Intel][SNB,IVB,HSW] Attempt to fix the DIMM(s) topology layout + - ClockSource: TSC udelay() asm implementation builtin as a default + - [Intel][Alder Lake] Adding IMC entry for i5-12500 processor + - [Intel][Alder Lake] Added default case if Processor has only Pcores + - [Intel][Atom/Bonnell][IMC] Attempt to compute the DIMM geometry + - [UI][Custom view] Show the Uncore unit in watt or joule + - [UI] Display HWP or CPPC in footer for capable processors. + - [CLI] Added HWP Capabilities and HWP Request to the JSON export + - [CLI] Don't allow the HWP dialog box if feature is not available. + - [CPPC][Firmware] allows (de)activation of the feature. + - [CLI] Added CPU ratios to JSON export + - [CPPC] Improved scaling + - [CPPC] Build fixed down to Kernel version 3 + - [Kernel/ACPI] Attempt to write CPPC registers + +------------------------------------------------------------------- Old: ---- CoreFreq-1.91.6.tar.gz New: ---- CoreFreq-1.92.3.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ CoreFreq.spec ++++++ --- /var/tmp/diff_new_pack.oHexoH/_old 2022-11-04 17:41:58.563008000 +0100 +++ /var/tmp/diff_new_pack.oHexoH/_new 2022-11-04 17:41:58.567008020 +0100 @@ -17,9 +17,9 @@ Name: CoreFreq -Version: 1.91.6 +Version: 1.92.3 Release: 0 -Summary: CPU monitoring software designed for 64-bits processors +Summary: CPU monitoring software for 64-bit processors License: GPL-2.0-or-later URL: https://github.com/cyring/CoreFreq Source: %{url}/archive/refs/tags/%{version}.tar.gz#/%{name}-%{version}.tar.gz @@ -34,9 +34,10 @@ %kernel_module_package -x preempt %description -A CPU monitoring software with BIOS like functionalities, is designed for the 64-bits -Processors of architecture Intel Atom, Core2, Nehalem, SandyBridge and superiors; -AMD Families 0Fh ... 17h (Zen), 18h (Hygon Dhyana) +A CPU monitoring software with BIOS-like functionalities for +64-bit processors like Intel Atom, Core2, Nehalem, SandyBridge +and superiors, and AMD Families 0Fh???17h (Zen), 18h (Hygon +Dhyana). %prep %setup -q ++++++ CoreFreq-1.91.6.tar.gz -> CoreFreq-1.92.3.tar.gz ++++++ ++++ 18219 lines of diff (skipped)
