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Hello community,
here is the log from the commit of package cpuid for openSUSE:Factory checked
in at 2022-12-05 18:01:57
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/cpuid (Old)
and /work/SRC/openSUSE:Factory/.cpuid.new.1835 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid"
Mon Dec 5 18:01:57 2022 rev:16 rq:1040214 version:20221201
Changes:
--------
--- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2022-10-14
15:43:17.211993299 +0200
+++ /work/SRC/openSUSE:Factory/.cpuid.new.1835/cpuid.changes 2022-12-05
18:02:09.828896113 +0100
@@ -1,0 +2,27 @@
+Mon Dec 05 09:50:12 UTC 2022 - Valentin Lefebvre <valentin.lefeb...@suse.com>
+
+- Update to release 20221201
+ * Clarified synth decoding for Intel Xeon D-1700.
+ * Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
+ instlatx64 sample.
+ * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
+ * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
+ * Added synth & uarch decoding for (10,15),(10,1) Bergamo.
+ * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
+ * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
+ * Added 0x8000001f/eax bits: RMPQUERY instruction support,
+ VMPL supervisor shadow stack support, VMGEXIT parameter support,
+ virtual TOM MSR support, IBS virtual support for SEV-ES guests,
+ SMT protection support, SVSM communication page MSR support,
+ VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
+ * Added 0x80000020/0/ecx bit: L3 range reservation support.
+ * Added 0x80000021/eax bits: automatic IBRS,
+ CPUID disable for non-privileged.
+ * Added 0x80000022/eax bit: AMD LBR & PMC freezing.
+ * Added 0x80000022/ebx field: number of LBR stack entries.
+ * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
+ * Added 0x80000026 leaf: AMD Extended CPU Topology.
+ * cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
+ AMD LBR V2 flag, from LX*.
+
+-------------------------------------------------------------------
Old:
----
cpuid-20221003.src.tar.gz
New:
----
cpuid-20221201.src.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ cpuid.spec ++++++
--- /var/tmp/diff_new_pack.RCuwgh/_old 2022-12-05 18:02:10.280898575 +0100
+++ /var/tmp/diff_new_pack.RCuwgh/_new 2022-12-05 18:02:10.288898618 +0100
@@ -17,7 +17,7 @@
Name: cpuid
-Version: 20221003
+Version: 20221201
Release: 0
Summary: x86 CPU identification tool
License: GPL-2.0-or-later
++++++ cpuid-20221003.src.tar.gz -> cpuid-20221201.src.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221003/ChangeLog new/cpuid-20221201/ChangeLog
--- old/cpuid-20221003/ChangeLog 2022-10-03 15:38:23.000000000 +0200
+++ new/cpuid-20221201/ChangeLog 2022-12-01 12:38:25.000000000 +0100
@@ -1,3 +1,46 @@
+Thu Dec 1 2022 Todd Allen <todd.al...@etallen.com>
+ * Made new release.
+
+Wed Nov 30 2022 Todd Allen <todd.al...@etallen.com>
+ * Clarified synth decoding for Intel Xeon D-1700.
+
+Wed Nov 30 2022 Todd Allen <todd.al...@etallen.com>
+ * Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
+ instlatx64 sample. The generation is known to be Zen 2 (7nm), but
+ the core is unknown. I heard speculation for each of Ariel (rejected
+ PlayStation 5 CPU), or Lockhart/Scarlett (rejected Xbox CPU).
+ * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
+ from @IanCutress.
+
+Mon Nov 28 2022 Todd Allen <todd.al...@etallen.com>
+ * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
+
+Mon Nov 28 2022 Todd Allen <todd.al...@etallen.com>
+ * Added synth & uarch decoding for (10,15),(10,1) Bergamo.
+
+Mon Nov 28 2022 Todd Allen <todd.al...@etallen.com>
+ * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
+ * Added 0x8000001b/eax bit: IBS L3 miss filtering support.
+ * Added 0x8000001f/eax bits: RMPQUERY instruction support,
+ VMPL supervisor shadow stack support, VMGEXIT parameter support,
+ virtual TOM MSR support, IBS virtual support for SEV-ES guests,
+ SMT protection support, SVSM communication page MSR support,
+ VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
+ * Added 0x80000020/0/ecx bit: L3 range reservation support.
+ * Added 0x80000021/eax bits: automatic IBRS,
+ CPUID disable for non-privileged.
+ * Added 0x80000022/eax bit: AMD LBR & PMC freezing.
+ * Added 0x80000022/ebx field: number of LBR stack entries.
+ * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
+ * Added 0x80000026 leaf: AMD Extended CPU Topology.
+
+Fri Nov 11 2022 Mateusz Guzik <mjgu...@gmail.com>
+ * cpuid.c: FreeBSD patch to use lseek64 and cpuset_setaffinity.
+
+Tue Oct 11 2022 Todd Allen <todd.al...@etallen.com>
+ * cpuid.c: Added 0x80000022/eax AMD LBR V2 flag, from LX*.
+ * cpuid.c: Note that (8,15),(10,0) Mendocino now is documented.
+
Mon Oct 3 2022 Todd Allen <todd.al...@etallen.com>
* Made new release.
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221003/FAMILY.NOTES
new/cpuid-20221201/FAMILY.NOTES
--- old/cpuid-20221003/FAMILY.NOTES 2022-10-03 13:41:23.000000000 +0200
+++ new/cpuid-20221201/FAMILY.NOTES 2022-10-11 15:02:58.000000000 +0200
@@ -277,7 +277,7 @@
9 = prosumer (16-core)
1st digit: generation
- 2nd digit (performance):
+ 2nd digit (performance) (old):
1,2,3 = mainstream
4,5,6 = high performance
7,8 = enthusiast
@@ -295,6 +295,35 @@
U = mobile: ultra low power (thin laptops)
C = chromebook
+ Zen (circa 2022)-based:
+ 1st digit: year
+ 7 = 2023
+ 8 = 2024
+ 9 = 2025
+ 2nd digit (performance) (new):
+ 1 = Athlon Silver
+ 2 = Athlon Gold
+ 3,4 = Ryzen 3
+ 5,6 = Ryzen 5
+ 7 = Ryzen 7
+ 8 = Ryzen 7/9
+ 9 = Ryzen 9
+ 3rd digit: architecture
+ 1 = Zen/Zen+
+ 2 = Zen 2
+ 3 = Zen 3
+ 4 = Zen 4
+ 5 = Zen 5
+ 4th digit: segment
+ 0 = lower
+ 5 = higher
+ Suffixes:
+ HX = mobile: high performance >= 55W (big laptops)
+ HS = mobile: high performance 35W
+ U = mobile: ultra low power 15-28W (thin laptops)
+ e = lowest power 9W
+ C = chromebook
+
======================================================================================================================================
Zhaoxin (VIA + Shanghai Municipal Government), began ~2013:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221003/Makefile new/cpuid-20221201/Makefile
--- old/cpuid-20221003/Makefile 2022-10-03 13:37:40.000000000 +0200
+++ new/cpuid-20221201/Makefile 2022-12-01 12:38:36.000000000 +0100
@@ -8,7 +8,7 @@
INSTALL_STRIP=-s
PACKAGE=cpuid
-VERSION=20221003
+VERSION=20221201
RELEASE=1
PROG=$(PACKAGE)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221003/cpuid.c new/cpuid-20221201/cpuid.c
--- old/cpuid-20221003/cpuid.c 2022-10-03 15:34:33.000000000 +0200
+++ new/cpuid-20221201/cpuid.c 2022-11-30 15:11:48.000000000 +0100
@@ -72,10 +72,6 @@
// include/cpuinfo_x86.h
// src/impl_x86__base_implementation.inl
-// SKC* indicates features that I have seen no (or incomplete) documentation
-// for, but which were sent to me in patch form by Smita Koralahalli
-// Channabasappa of AMD.
-
#ifdef __linux__
#define USE_CPUID_MODULE
#define USE_KERNEL_SCHED_SETAFFINITY
@@ -85,6 +81,11 @@
#define USE_PROCESSOR_BIND
#endif
+#if defined(__FreeBSD__)
+#define lseek64 lseek
+#define USE_CPUSET_SETAFFINITY
+#endif
+
#if defined(__GNUC__) && defined(__GNUC_MINOR__) &&
defined(__GNUC_PATCHLEVEL__)
#if __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ >= 40300
#define USE_CPUID_COUNT
@@ -2175,14 +2176,15 @@
FM ( 0, 6, 10,10, *u = "Redwood Cove",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but
-L); (engr?) sample via instlatx64 from Komachi_ENSAKA
FM ( 0, 6, 10,11, *u = "Redwood Cove",
*f = "Golden Cove", *p = "Intel 4"); // DPTF*
FM ( 0, 6, 10,12, *u = "Redwood Cove",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample
via instlatx64 from Komachi_ENSAKA
- FM ( 0, 6, 10,13, *u = "Granite Rapids",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample
via instlatx64 from Komachi_ENSAKA
- FM ( 0, 6, 10,14, *u = "Granite Rapids",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*
- FM ( 0, 6, 10,15, *u = "Sierra Forest");
// MSR_CPUID_table*; (engr?) sample
via instlatx64 from Komachi_ENSAKA
+ FM ( 0, 6, 10,13, *u = "Granite Rapids",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*; (engr?)
sample via instlatx64 from Komachi_ENSAKA
+ FM ( 0, 6, 10,14, *u = "Granite Rapids",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*
+ FM ( 0, 6, 10,15, *u = "Sierra Forest");
// MSR_CPUID_table*; LX*; (engr?)
sample via instlatx64 from Komachi_ENSAKA
FM ( 0, 6, 11, 5, *u = "Redwood Cove",
*f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*
- FM ( 0, 6, 11, 6, *u = "Crestmont",
*p = "Intel 7"); // MSR_CPUID_table* (although
assumption that Grand Ridge is Crestmont)
+ FM ( 0, 6, 11, 6, *u = "Crestmont",
*p = "Intel 7"); // MSR_CPUID_table*; LX*; (although
assumption that Grand Ridge is Crestmont)
FM ( 0, 6, 11, 7, *u = "Raptor Cove",
*f = "Golden Cove", *p = "Intel 7"); // LX*, DPTF*
FM ( 0, 6, 11,10, *u = "Raptor Cove",
*f = "Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot*
FM ( 0, 6, 11,14, *u = "Golden Cove",
*p = "Intel 7"); // Coreboot*
+ FM ( 0, 6, 12,15, *u = "Emerald Rapids",
*p = "Intel 7"); // LX*
F ( 0, 7, *u = "Itanium");
FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu =
TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org
FM ( 0,11, 0, 1, *u = "Knights Corner", *ciu =
TRUE, *f = "K1OM", *p = "22nm");
@@ -2299,9 +2301,10 @@
FM ( 8,15, 6, 0, *u = "Zen 2", *p = "7nm");
FM ( 8,15, 6, 8, *u = "Zen 2", *p = "7nm"); //
undocumented, but instlatx64 samples
FM ( 8,15, 7, 1, *u = "Zen 2", *p = "7nm"); //
undocumented, but samples from Steven Noonan
+ FM ( 8,15, 8, 4, *u = "Zen 2", *p = "7nm"); //
undocumented, but sample via instlatx64
FM ( 8,15, 9, 0, *u = "Zen 2", *p = "7nm"); //
undocumented, but sample via instlatx64 from @patrickschur_
FM ( 8,15, 9, 8, *u = "Zen 2", *p = "7nm"); //
undocumented, but sample via instlatx64 from @zimogorets
- FM ( 8,15, 10, 0, *u = "Zen 2", *p = "7nm"); //
undocumented, but sample via instlatx64 from @ExecuFix
+ FM ( 8,15, 10, 0, *u = "Zen 2", *p = "7nm"); // sample via
instlatx64 from @ExecuFix
FM (10,15, 0, 1, *u = "Zen 3", *p = "7nm");
FM (10,15, 0, 8, *u = "Zen 3", *p = "7nm"); //
undocumented, but sample via instlatx64 from @ExecuFix
FM (10,15, 1, 0, *u = "Zen 4", *p = "5nm"); //
undocumented, but sample via instlatx64 from @ExecuFix
@@ -2316,6 +2319,7 @@
FM (10,15, 6, 1, *u = "Zen 4", *p = "5nm"); //
undocumented, but instlatx64 sample
FM (10,15, 7, 0, *u = "Zen 4", *p = "5nm"); //
undocumented, but sample via instlatx64 from @patrickschur_
FM (10,15, 10, 0, *u = "Zen 4c", *p = "5nm"); //
undocumented, but sample via instlatx64 from @ExecuFix; 4c from 2021-11-8
roadmap from Lisa Su
+ FM (10,15, 10, 1, *u = "Zen 4c", *p = "5nm");
DEFAULT ((void)NULL);
}
@@ -3373,7 +3377,8 @@
FMSQ( 0, 6, 6,10, 6, sS, "Intel Scalable (3rd Gen)
Bronze/Silver/Gold/Platinum (Ice Lake D2/M1)");
FMQ ( 0, 6, 6,10, sS, "Intel Scalable (3rd Gen)
Bronze/Silver/Gold/Platinum (Ice Lake)");
FM ( 0, 6, 6,10, "Intel (unknown type) (Ice Lake)");
- FM ( 0, 6, 6,12, "Intel Core (Ice Lake)"); // no spec update;
only MSR_CPUID_table* so far; DPTF* claims this is Meteor Lake S.
+ FMQ ( 0, 6, 6,12, sX, "Intel Xeon (Ice Lake)"); // no spec update;
only MSR_CPUID_table* so far; DPTF* claims this is Meteor Lake S; sample from
instlatx64
+ FM ( 0, 6, 6,12, "Intel (unknown type) (Ice Lake)"); // no
spec update; only MSR_CPUID_table* so far; DPTF* claims this is Meteor Lake S.
// No spec update; only MRG* 2018-03-06, 2019-08-31. It is some sort of
Atom,
// but no idea which uarch or core.
FM ( 0, 6, 6,14, "Intel Puma 7 (Cougar Mountain)");
@@ -3595,6 +3600,7 @@
FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); //
MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA
FM ( 0, 6, 11, 5, "Intel (unknown type) (Meteor Lake)"); //
MSR_CPUID_table*
FM ( 0, 6, 11, 6, "Intel Atom (Grand Ridge)"); //
MSR_CPUID_table*
+ FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 (Raptor Lake)"); //
MSR_CPUID_table*; LX*; DPTF* (which also says Raptor Lake-S); instlatx64 samples
FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake)"); //
MSR_CPUID_table*; LX*; DPTF* (which also says Raptor Lake-S)
FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-P J0)");
// Coreboot*
FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)");
// Coreboot*
@@ -4542,11 +4548,13 @@
FM ( 8,15, 6, 8, "AMD Ryzen 5000 (Lucienne)"); // undocumented,
but instlatx64 samples
FMS ( 8,15, 7, 1, 0, "AMD Ryzen 3000 (Matisse B0)"); // undocumented,
but samples from Steven Noonan
FM ( 8,15, 7, 1, "AMD Ryzen 3000 (Matisse)"); // undocumented,
but samples from Steven Noonan
+ FM ( 8,15, 8, 4, "AMD 4800S Desktop Kit"); // undocumented, but
sample via instlatx64
FMS ( 8,15, 9, 0, 0, "AMD Ryzen (Van Gogh A0)"); // undocumented, but
(engr?) sample via instlatx64 from @patrickschur_
FMS ( 8,15, 9, 0, 2, "AMD Ryzen (Van Gogh A2)"); // undocumented, but
example from instlatx64
FM ( 8,15, 9, 0, "AMD Ryzen (Van Gogh)"); // undocumented, but
(engr?) sample via instlatx64 from @patrickschur_
FM ( 8,15, 9, 8, "AMD Ryzen (Mero)"); // undocumented, but
(engr?) sample via instlatx64 from @zimogorets
- FM ( 8,15, 10, 0, "AMD Ryzen (Mendocino)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
+ FMS ( 8,15, 10, 0, 0, "AMD Ryzen (Mendocino A0)"); // (engr?) samples
via instlatx64
+ FM ( 8,15, 10, 0, "AMD Ryzen (Mendocino)"); // (engr?) sample via
instlatx64 from @ExecuFix
F ( 8,15, "AMD (unknown model)");
FMS (10,15, 0, 1, 1, "AMD EPYC (3rd Gen) (Milan B1)");
FMS (10,15, 0, 1, 2, "AMD EPYC (3rd Gen) (Milan B2)");
@@ -4555,6 +4563,7 @@
FMS (10,15, 0, 8, 2, "AMD Ryzen Threadripper 5000 (Chagall A2)"); //
undocumented, but sample from CCRT
FM (10,15, 0, 8, "AMD Ryzen Threadripper 5000 (Chagall)"); //
undocumented, but sample from CCRT
FMS (10,15, 1, 0, 0, "AMD EPYC (Genoa A0)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
+ FMS (10,15, 1, 0, 1, "AMD EPYC (Genoa A1)"); // undocumented, but
(engr?) sample via instlatx64 from @IanCutress
FM (10,15, 1, 0, "AMD EPYC (Genoa)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
FMS (10,15, 1, 8, 0, "AMD Ryzen (Storm Peak A0)"); // undocumented,
but (engr?) sample from @patrickschur_
FMS (10,15, 1, 8, 1, "AMD Ryzen (Storm Peak A1)"); // undocumented,
but engr sample via instlatx64 from einstein11.aei.uni-hannover.de (12981157)
@@ -4583,6 +4592,8 @@
FM (10,15, 7, 4, "AMD Ryzen (Phoenix)"); // undocumented, but
engr sample via instlatx64 from bakerlab.org (6220795)
FMS (10,15, 10, 0, 0, "AMD Ryzen (Bergamo A0)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
FM (10,15, 10, 0, "AMD Ryzen (Bergamo)"); // undocumented, but
(engr?) sample via instlatx64 from @ExecuFix
+ FMS (10,15, 10, 1, 1, "AMD Ryzen (Bergamo B1)");
+ FM (10,15, 10, 1, "AMD Ryzen (Bergamo)");
F (10,15, "AMD (unknown model)");
DEFAULT ("unknown");
@@ -8480,11 +8491,14 @@
{ "virtualized VMLOAD/VMSAVE" , 15, 15, bools },
{ "virtualized global interrupt flag (GIF)" , 16, 16, bools },
{ "GMET: guest mode execute trap" , 17, 17, bools },
- { "X2AVIC: virtualized X2APIC" , 18, 18, bools }, // LX*
+ { "X2AVIC: virtualized X2APIC" , 18, 18, bools },
{ "supervisor shadow stack" , 19, 19, bools },
{ "guest Spec_ctl support" , 20, 20, bools },
+ { "ROGPT: read-only guest page table" , 21, 21, bools },
{ "host MCE override" , 23, 23, bools },
{ "INVLPGB/TLBSYNC hyperv interc enable" , 24, 24, bools },
+ { "VNMI: NMI virtualization" , 25, 25, bools },
+ { "IBS virtualization" , 26, 26, bools },
{ "guest SVME addr check" , 28, 28, bools }, //
LX*, Qemu*
};
@@ -8559,6 +8573,7 @@
{ "fused branch micro-op indication support", 8, 8, bools },
{ "IBS fetch control extended MSR support" , 9, 9, bools },
{ "IBS op data 4 MSR support" , 10, 10, bools },
+ { "IBS L3 miss filtering support" , 11, 11, bools },
};
printf(" Instruction Based Sampling Identifiers (0x8000001b/eax):\n");
@@ -8765,8 +8780,10 @@
{ "SEV-ES: SEV encrypted state support" , 3, 3, bools },
{ "SEV-SNP: SEV secure nested paging" , 4, 4, bools },
{ "VMPL: VM permission levels" , 5, 5, bools },
+ { "RMPQUERY instruction support" , 6, 6, bools },
+ { "VMPL supervisor shadow stack support" , 7, 7, bools },
{ "Secure TSC supported" , 8, 8, bools },
- { "virtual TSC_AUX supported" , 9, 9, bools }, // LX*
+ { "virtual TSC_AUX supported" , 9, 9, bools },
{ "hardware cache coher across enc domains" , 10, 10, bools },
{ "SEV guest exec only from 64-bit host" , 11, 11, bools },
{ "restricted injection" , 12, 12, bools },
@@ -8774,7 +8791,13 @@
{ "full debug state swap for SEV-ES guests" , 14, 14, bools },
{ "disallowing IBS use by host" , 15, 15, bools },
{ "VTE: SEV virtual transparent encryption" , 16, 16, bools },
- { "VMSA register protection" , 24, 24, bools },
+ { "VMGEXIT parameter support" , 17, 17, bools },
+ { "virtual TOM MSR support" , 18, 18, bools },
+ { "IBS virtual support for SEV-ES guests" , 19, 19, bools },
+ { "VMSA register protection support" , 24, 24, bools },
+ { "SMT protection support" , 25, 25, bools },
+ { "SVSM communication page MSR support" , 28, 28, bools },
+ { "VIRT_RMPUPDATE & VIRT_PSMASH MSR support", 29, 29, bools },
};
print_names(value, names, LENGTH(names),
@@ -8803,7 +8826,18 @@
};
print_names(value, names, LENGTH(names),
- /* max_len => */ 0);
+ /* max_len => */ 40);
+}
+
+static void
+print_80000020_0_ecx(unsigned int value)
+{
+ static named_item names[]
+ = { { "L3 range reservation support" , 4, 4, bools },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 40);
}
static void
@@ -8841,8 +8875,10 @@
{ "SMM paging configuration lock support" , 3, 3, bools },
{ "null selector clears base" , 6, 6, bools },
{ "upper address ignore support" , 7, 7, bools },
+ { "automatic IBRS" , 8, 8, bools },
{ "SMM_CTL MSR not supported" , 9, 9, bools },
{ "prefetch control MSR support" , 13, 13, bools },
+ { "CPUID disable for non-privileged" , 17, 17, bools },
};
print_names(value, names, LENGTH(names),
@@ -8865,7 +8901,9 @@
print_80000022_eax(unsigned int value)
{
static named_item names[]
- = { { "AMD performance monitoring V2" , 0, 0, bools }, // LX*
+ = { { "AMD performance monitoring V2" , 0, 0, bools },
+ { "AMD LBR V2" , 1, 1, bools },
+ { "AMD LBR stack & PMC freezing" , 2, 2, bools },
};
print_names(value, names, LENGTH(names),
@@ -8877,6 +8915,7 @@
{
static named_item names[]
= { { "number of core perf ctrs" , 0, 3, NIL_IMAGES },
+ { "number of LBR stack entries" , 4, 9, NIL_IMAGES },
{ "number of avail Northbridge perf ctrs" , 10, 15, NIL_IMAGES },
};
@@ -8885,6 +8924,85 @@
}
static void
+print_80000023_eax(unsigned int value)
+{
+ static named_item names[]
+ = { { "secure host multi-key memory support" , 0, 0, bools },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 36);
+}
+
+static void
+print_80000023_ebx(unsigned int value)
+{
+ static named_item names[]
+ = { { "number of encryption key IDs" , 0, 15, NIL_IMAGES },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 36);
+}
+
+static void
+print_80000026_eax(unsigned int value)
+{
+ static named_item names[]
+ = { { "bit width of level" , 0, 4, NIL_IMAGES },
+ { "power efficiency ranking available" , 29, 29, bools },
+ { "cores heterogeneous at this level" , 30, 30, bools },
+ { "components have varying number of cores" , 31, 31, bools },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 39);
+}
+
+static void
+print_80000026_1_ebx(unsigned int value)
+{
+ static named_item names[]
+ = { { "number of logical processors at level" , 0, 15, NIL_IMAGES },
+ { "power efficiency ranking" , 16, 23, NIL_IMAGES },
+ { "native mode ID" , 24, 27, NIL_IMAGES },
+ { "core type" , 28, 31, NIL_IMAGES },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 39);
+}
+
+static void
+print_80000026_n_ebx(unsigned int value)
+{
+ static named_item names[]
+ = { { "number of logical processors at level" , 0, 15, NIL_IMAGES },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 39);
+}
+
+static void
+print_80000026_ecx(unsigned int value)
+{
+ static ccstring level_type[1<<8] = { "invalid (0)",
+ "core (1)",
+ "complex (2)",
+ "die (3)",
+ "socket (4)" };
+
+ static named_item names[]
+ = { { "level number" , 0, 7, NIL_IMAGES },
+ { "level type" , 8, 15, level_type },
+ };
+
+ print_names(value, names, LENGTH(names),
+ /* max_len => */ 39);
+}
+
+static void
print_80860001_eax(unsigned int value)
{
static named_item names[]
@@ -9966,6 +10084,7 @@
if (try == 0) {
printf(" PQoS Enforcement (0x80000020):\n");
print_80000020_0_ebx(words[WORD_EBX]);
+ print_80000020_0_ecx(words[WORD_ECX]);
} else if (try == 1) {
printf(" PQoS Enforcement for L3 External Bandwidth"
" (0x80000020/1):\n");
@@ -9998,6 +10117,23 @@
printf(" Extended Performance Monitoring and Debugging
(0x80000022):\n");
print_80000022_eax(words[WORD_EAX]);
print_80000022_ebx(words[WORD_EBX]);
+ } else if (reg == 0x80000023) {
+ printf(" Multi-Key Encrypted Memory Capabilities (0x80000023):\n");
+ print_80000023_eax(words[WORD_EAX]);
+ print_80000023_ebx(words[WORD_EBX]);
+ } else if (reg == 0x80000026) {
+ /* Similar to 0xb & 0x1f, but with extra bit fields */
+ if (try == 0) {
+ printf(" AMD Extended CPU Topology (0x80000026):\n");
+ }
+ printf(" --- level %d ---\n", try);
+ print_80000026_ecx(words[WORD_ECX]);
+ print_80000026_eax(words[WORD_EAX]);
+ if (try == 1) {
+ print_80000026_1_ebx(words[WORD_EBX]);
+ } else {
+ print_80000026_n_ebx(words[WORD_EBX]);
+ }
} else if (reg == 0x80860000) {
// max already set to words[WORD_EAX]
} else if (reg == 0x80860001) {
@@ -10114,6 +10250,15 @@
return result;
#elif defined(USE_PROCESSOR_BIND)
return sysconf(_SC_NPROCESSORS_CONF);
+#elif defined(USE_CPUSET_SETAFFINITY)
+ cpuset_t mask;
+ CPU_ZERO(&mask);
+ if (cpuset_getaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(mask),
+ &mask) == 0) {
+ return CPU_COUNT(&mask);
+ } else {
+ return sysconf(_SC_NPROCESSORS_CONF);
+ }
#else
unsigned long result = sysconf(_SC_NPROCESSORS_CONF);
if (result > CPU_SETSIZE) result = CPU_SETSIZE;
@@ -10152,6 +10297,14 @@
#elif defined(USE_PROCESSOR_BIND)
pthread_t thread = pthread_self();
int status = processor_bind(P_LWPID, thread, cpu, NULL);
+#elif defined(USE_CPUSET_SETAFFINITY)
+ int status = 0;
+ cpuset_t mask;
+ CPU_ZERO(&mask);
+ CPU_SET(cpu, &mask);
+ if (cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_PID, -1,
+ sizeof(mask), &mask) != 0)
+ status = -1;
#else
cpu_set_t cpuset;
CPU_ZERO(&cpuset);
@@ -10585,6 +10738,15 @@
if (try > max_tries) break;
real_get(cpuid_fd, reg, words, try, FALSE);
}
+ } else if (reg == 0x80000026) {
+ print_reg(reg, words, raw, 0, &stash);
+ unsigned int try;
+ for (try = 1; try < 256; try++) {
+ real_get(cpuid_fd, reg, words, try, FALSE);
+ print_reg(reg, words, raw, try, &stash);
+ // exit when level type indicates invalid (0).
+ if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break;
+ }
} else {
print_reg(reg, words, raw, 0, &stash);
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221003/cpuid.man new/cpuid-20221201/cpuid.man
--- old/cpuid-20221003/cpuid.man 2022-10-03 15:37:49.000000000 +0200
+++ new/cpuid-20221201/cpuid.man 2022-12-01 12:39:18.000000000 +0100
@@ -1,7 +1,7 @@
.\"
-.\" $Id: cpuid.man,v 20221003 2022/10/03 07:37:43 todd $
+.\" $Id: cpuid.man,v 20221201 2022/12/01 04:38:20 todd $
.\"
-.TH CPUID 1 "3 Oct 2022" "20221003"
+.TH CPUID 1 "1 Dec 2022" "20221201"
.SH NAME
cpuid \- Dump CPUID information for each CPU
.SH SYNOPSIS
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/cpuid-20221003/cpuid.spec
new/cpuid-20221201/cpuid.spec
--- old/cpuid-20221003/cpuid.spec 2022-10-03 15:38:34.000000000 +0200
+++ new/cpuid-20221201/cpuid.spec 2022-12-01 12:41:02.000000000 +0100
@@ -1,4 +1,4 @@
-%define version 20221003
+%define version 20221201
%define release 1
Summary: dumps CPUID information about the CPU(s)
Name: cpuid
