Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2023-02-23 16:29:29
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.1706 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Thu Feb 23 16:29:29 2023 rev:23 rq:1067280 version:1.95.4
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2023-02-10
14:35:52.414118877 +0100
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.1706/CoreFreq.changes
2023-02-23 16:53:35.289199091 +0100
@@ -1,0 +2,16 @@
+Wed Feb 22 23:24:52 UTC 2023 - Michael Pujos <pujos.mich...@gmail.com>
+
+- update to 1.95.4
+ * [Intel] [from 11th to 14th gen]
+ Convert the DRAM Speed to MT/s unit
+ Compute the Bus Rate based on the BIOS MC PLL
+
+- update to 1.95.3
+ * [Intel] [Airmont]
+ Improved the IMC geometry
+ Introducing the Spreadtrum architecture
+ Fixed the Bus and DRAM frequency rates
+ * [Intel] [from 11th to 13th gen] Attempt to probe the interleaved
controllers
+ * [Intel] [Alder Lake/H] Attempt to decode the TCO Watchdog
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.95.2.tar.gz
New:
----
CoreFreq-1.95.4.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.BelmZQ/_old 2023-02-23 16:53:35.701201479 +0100
+++ /var/tmp/diff_new_pack.BelmZQ/_new 2023-02-23 16:53:35.709201526 +0100
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.95.2
+Version: 1.95.4
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.95.2.tar.gz -> CoreFreq-1.95.4.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/corefreq-api.h
new/CoreFreq-1.95.4/corefreq-api.h
--- old/CoreFreq-1.95.2/corefreq-api.h 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/corefreq-api.h 2023-02-19 00:29:35.000000000 +0100
@@ -750,13 +750,13 @@
struct {
NHM_IMC_CLK_RATIO_STATUS DimmClock;
QPI_FREQUENCY QuickPath;
+ BIOS_MEMCLOCK BIOS_DDR;
};
union {
struct {
MCH_CLKCFG ClkCfg;
SNB_CAPID_A SNB_Cap;
IVB_CAPID_B IVB_Cap;
- BIOS_MEMCLOCK BIOS_DDR;
};
struct {
SNB_EP_CAPID0 SNB_EP_Cap0;
@@ -1425,6 +1425,9 @@
#define DID_INTEL_ALDERLAKE_WM690_PCH 0x7a8d
#define DID_INTEL_ALDERLAKE_HM670_PCH 0x7a8c
#define DID_INTEL_PCH_600_SMBUS 0xa0a3
+/* Source: 12th Gen Intel(R) Core(TM) i7-12700H */
+#define DID_INTEL_ALDERLAKE_PCH_P 0x5182 /* PCH eSPI Controller */
+#define DID_INTEL_PCH_P_SMBUS 0x51a3
/* Source: 13th Generation Intel Core Processors Datasheet, vol 1 */
#define DID_INTEL_RAPTORLAKE_S_8P_16E_HB 0xa700
#define DID_INTEL_RAPTORLAKE_S_8P_8E_HB 0xa703
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/corefreq.h
new/CoreFreq-1.95.4/corefreq.h
--- old/CoreFreq-1.95.2/corefreq.h 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/corefreq.h 2023-02-19 00:29:35.000000000 +0100
@@ -77,6 +77,7 @@
IC_W680,
IC_WM690,
IC_HM670,
+ IC_ADL_PCH_P,
IC_Z790,
IC_H770,
IC_B760,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/corefreqd.c
new/CoreFreq-1.95.4/corefreqd.c
--- old/CoreFreq-1.95.2/corefreqd.c 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/corefreqd.c 2023-02-19 00:29:35.000000000 +0100
@@ -3210,11 +3210,36 @@
{
unsigned short mc, cha, slot;
/* BUS & DRAM frequency */
- RO(Shm)->Uncore.CtrlSpeed = 800LLU + (
- ((2134LLU * RO(Proc)->Uncore.MC[0].SLM.DTR0.DFREQ) >> 3)
- );
- RO(Shm)->Uncore.Bus.Rate = 5000;
-
+ switch (RO(Proc)->Uncore.MC[0].SLM.DTR2.AMT.DFREQ) {
+ case 0b000:
+ RO(Shm)->Uncore.CtrlSpeed = 400LLU;
+ RO(Shm)->Uncore.Bus.Rate = 800;
+ break;
+ case 0b001:
+ RO(Shm)->Uncore.CtrlSpeed = 533LLU;
+ RO(Shm)->Uncore.Bus.Rate = 1066;
+ break;
+ case 0b010:
+ RO(Shm)->Uncore.CtrlSpeed = 666LLU;
+ RO(Shm)->Uncore.Bus.Rate = 1333;
+ break;
+ case 0b011:
+ RO(Shm)->Uncore.CtrlSpeed = 800LLU;
+ RO(Shm)->Uncore.Bus.Rate = 1600;
+ break;
+ case 0b100:
+ RO(Shm)->Uncore.CtrlSpeed = 933LLU;
+ RO(Shm)->Uncore.Bus.Rate = 1866;
+ break;
+ case 0b101:
+ RO(Shm)->Uncore.CtrlSpeed = 1066LLU;
+ RO(Shm)->Uncore.Bus.Rate = 2133;
+ break;
+ default:
+ RO(Shm)->Uncore.CtrlSpeed = 1066LLU;
+ RO(Shm)->Uncore.Bus.Rate = 2133;
+ break;
+ }
RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
* RO(Shm)->Uncore.Bus.Rate)
/ RO(Shm)->Proc.Features.Factory.Clock.Hz;
@@ -3232,20 +3257,20 @@
for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++)
{
/* Standard Timings */
- TIMING(mc, cha).tCL = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tCL + 5;
+ TIMING(mc, cha).tCL = RO(Proc)->Uncore.MC[mc].SLM.DTR0.AMT.tCL + 5;
- TIMING(mc, cha).tRCD = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tRCD + 5;
+ TIMING(mc, cha).tRCD = RO(Proc)->Uncore.MC[mc].SLM.DTR0.AMT.tRCD + 5;
- TIMING(mc, cha).tRP = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tRP + 5;
+ TIMING(mc, cha).tRP = RO(Proc)->Uncore.MC[mc].SLM.DTR0.AMT.tRP + 5;
- TIMING(mc, cha).tRAS = RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRAS + 14;
+ TIMING(mc, cha).tRAS = RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tRAS + 14;
- TIMING(mc, cha).tRRD = RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRRD + 4;
+ TIMING(mc, cha).tRRD = RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tRRD + 4;
TIMING(mc, cha).tRFC = \
- RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tXS == 0 ? 256 : 384;
+ RO(Proc)->Uncore.MC[mc].SLM.DTR0.AMT.tXS == 0 ? 256 : 384;
- switch (RO(Proc)->Uncore.MC[mc].SLM.DRFC.Z8000.tREFI) {
+ switch (RO(Proc)->Uncore.MC[mc].SLM.DRFC.AMT.tREFI) {
case 0 ... 1:
TIMING(mc, cha).tREFI = 0;
break;
@@ -3259,88 +3284,88 @@
TIMING(mc, cha).tREFI *= RO(Shm)->Uncore.CtrlSpeed;
TIMING(mc, cha).tREFI /= 20;
- TIMING(mc, cha).tCKE = RO(Proc)->Uncore.MC[mc].SLM.DRMC.Z8000.CKEVAL;
+ TIMING(mc, cha).tCKE = RO(Proc)->Uncore.MC[mc].SLM.DRMC.AMT.CKEVAL;
- TIMING(mc, cha).tRTPr= RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tRTP + 4;
+ TIMING(mc, cha).tRTPr= RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tRTP + 4;
- TIMING(mc, cha).tWTPr= RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tWTP + 15;
+ TIMING(mc, cha).tWTPr= RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tWTP + 15;
- switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tCCD) {
- case 0:
- TIMING(mc, cha).B2B = 4;
- break;
- case 1:
- TIMING(mc, cha).B2B = 12;
- break;
- case 2:
- TIMING(mc, cha).B2B = 18;
- break;
- case 3:
- default:
- TIMING(mc, cha).B2B = 0;
- break;
- }
+ switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tCCD) {
+ case 0:
+ TIMING(mc, cha).B2B = 4;
+ break;
+ case 1:
+ TIMING(mc, cha).B2B = 12;
+ break;
+ case 2:
+ TIMING(mc, cha).B2B = 18;
+ break;
+ case 3:
+ default:
+ TIMING(mc, cha).B2B = 0;
+ break;
+ }
- switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tFAW) {
- case 0 ... 1:
- case 0xd ... 0xf:
- TIMING(mc, cha).tFAW = 0;
- break;
- default:
- TIMING(mc, cha).tFAW = \
- 10 + ((unsigned int)RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tFAW << 1);
- break;
- }
+ switch (RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tFAW) {
+ case 0 ... 1:
+ case 0xd ... 0xf:
+ TIMING(mc, cha).tFAW = 0;
+ break;
+ default:
+ TIMING(mc, cha).tFAW = \
+ 10 + ((unsigned int)RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tFAW
<< 1);
+ break;
+ }
- TIMING(mc, cha).tCWL = RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tWCL + 3;
+ TIMING(mc, cha).tCWL = RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tWCL + 3;
/*TODO( Read to Read. Same Rank )
TIMING(mc, cha).tsrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
*/
TIMING(mc, cha).tsrRdTWr = 6
- + RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tRWSR;
+ + RO(Proc)->Uncore.MC[mc].SLM.DTR3.AMT.tRWSR;
TIMING(mc, cha).tsrWrTRd = 11
- + RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tWRSR;
+ + RO(Proc)->Uncore.MC[mc].SLM.DTR3.AMT.tWRSR;
/*TODO( Write to Write. Same Rank )
TIMING(mc, cha).tsrWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR?.;
*/
/* Different Rank */
- TIMING(mc, cha).tdrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRRDR;
+ TIMING(mc, cha).tdrRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.AMT.tRRDR;
if (TIMING(mc, cha).tdrRdTRd > 0) {
TIMING(mc, cha).tdrRdTRd += 5;
}
- TIMING(mc, cha).tdrRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRWDR;
+ TIMING(mc, cha).tdrRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.AMT.tRWDR;
if (TIMING(mc, cha).tdrRdTWr > 0) {
TIMING(mc, cha).tdrRdTWr += 5;
}
- TIMING(mc, cha).tdrWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tWRDR;
+ TIMING(mc, cha).tdrWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.AMT.tWRDR;
if (TIMING(mc, cha).tdrWrTRd > 0) {
TIMING(mc, cha).tdrWrTRd += 3;
}
- TIMING(mc, cha).tdrWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tWWDR;
+ TIMING(mc, cha).tdrWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.AMT.tWWDR;
if (TIMING(mc, cha).tdrWrTWr > 1) {
TIMING(mc, cha).tdrWrTWr += 4;
}
/*TODO( Different DIMM )
- TIMING(mc, cha).tddRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRRDD;
+ TIMING(mc, cha).tddRdTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR2.AMT.tRRDD;
- TIMING(mc, cha).tddRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tRWDD;
+ TIMING(mc, cha).tddRdTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.AMT.tRWDD;
- TIMING(mc, cha).tddWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tWRDD;
+ TIMING(mc, cha).tddWrTRd = RO(Proc)->Uncore.MC[mc].SLM.DTR3.AMT.tWRDD;
- TIMING(mc, cha).tddWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.Z8000.tWWDD;
+ TIMING(mc, cha).tddWrTWr = RO(Proc)->Uncore.MC[mc].SLM.DTR2.AMT.tWWDD;
*/
/* Command Rate */
TIMING(mc, cha).CMD_Rate = 1
- + RO(Proc)->Uncore.MC[mc].SLM.DTR1.Z8000.tCMD;
+ + RO(Proc)->Uncore.MC[mc].SLM.DTR1.AMT.tCMD;
- TIMING(mc, cha).tXS = RO(Proc)->Uncore.MC[mc].SLM.DTR0.Z8000.tXS;
+ TIMING(mc, cha).tXS = RO(Proc)->Uncore.MC[mc].SLM.DTR0.AMT.tXS;
- TIMING(mc, cha).tXP = RO(Proc)->Uncore.MC[mc].SLM.DTR3.Z8000.tXP;
+ TIMING(mc, cha).tXP = RO(Proc)->Uncore.MC[mc].SLM.DTR3.AMT.tXP;
/* Topology */
for (slot = 0; slot < RO(Shm)->Uncore.MC[mc].SlotCount; slot++)
{
@@ -3355,33 +3380,20 @@
{ .Banks = 8, .Rows = 1<<16, .Cols = 1<<10 },
{ .Banks = 8, .Rows = 1<<14, .Cols = 1<<10 }
};
- if (cha == 0) {
- RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
- RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN0
- + RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN1;
-
- RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = \
- DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN0].Banks;
-
- RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = \
- DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN0].Rows;
- RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = \
- DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN0].Cols;
- } else {
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Ranks = \
- RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN2
- + RO(Proc)->Uncore.MC[mc].SLM.DRP.RKEN3;
+ RO(Proc)->Uncore.MC[mc].SLM.DRP.AMT.RKEN0
+ + RO(Proc)->Uncore.MC[mc].SLM.DRP.AMT.RKEN1;
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Banks = \
- DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Banks;
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.AMT.DIMMDDEN0].Banks;
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows = \
- DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Rows;
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.AMT.DIMMDDEN0].Rows;
RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols = \
- DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.DIMMDDEN1].Cols;
- }
+ DDR3L[RO(Proc)->Uncore.MC[mc].SLM.DRP.AMT.DIMMDDEN0].Cols;
+
DIMM_Size = 8LLU
* RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Rows
* RO(Shm)->Uncore.MC[mc].Channel[cha].DIMM[slot].Cols
@@ -3392,21 +3404,14 @@
(unsigned int)(DIMM_Size >> 20);
}
/* Error Correcting Code */
- TIMING(mc, cha).ECC = \
- RO(Proc)->Uncore.MC[mc].SLM.BIOS_CFG.EFF_ECC_EN
- | RO(Proc)->Uncore.MC[mc].SLM.BIOS_CFG.ECC_EN;
+ TIMING(mc, cha).ECC = RO(Proc)->Uncore.MC[mc].SLM.BIOS_CFG.ECC_EN;
}
- if (RO(Proc)->Uncore.MC[mc].SLM.DRP.DRAMTYPE) {
+ if (RO(Proc)->Uncore.MC[mc].SLM.DRP.AMT.DRAMTYPE) {
RO(Shm)->Uncore.Unit.DDR_Ver = 2;
RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_LPDDR;
} else {
RO(Shm)->Uncore.Unit.DDR_Ver = 3;
-
- if (RO(Proc)->Uncore.MC[mc].SLM.DRP.ENLPDDR3) {
- RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_LPDDR;
- } else {
- RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_SDRAM;
- }
+ RO(Shm)->Uncore.Unit.DDR_Std = RAM_STD_SDRAM;
}
}
}
@@ -5074,22 +5079,9 @@
void RKL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
{
unsigned int units = 12;
+ unsigned int Bus_Rate = RO(Proc)->Uncore.Bus.BIOS_DDR.MC_PLL_RATIO;
unsigned short mc, clock_done;
- if (RO(Proc)->Uncore.Bus.RKL_SA_Pll.UCLK_RATIO > 0) {/* Ring Interconnect
*/
- RO(Shm)->Uncore.Bus.Rate = RO(Proc)->Uncore.Bus.RKL_SA_Pll.UCLK_RATIO;
- RO(Shm)->Uncore.Bus.Rate *= 100;
- RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
- RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
- } else { /* Advertised Bus Speed */
- RO(Shm)->Uncore.Bus.Rate = 8000;
- RO(Shm)->Uncore.Unit.Bus_Rate = MC_MTS;
- RO(Shm)->Uncore.Unit.BusSpeed = MC_MTS;
- }
- RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
- * RO(Shm)->Uncore.Bus.Rate)
- / RO(Shm)->Proc.Features.Factory.Clock.Hz;
-
for (mc = 0, clock_done = 0;
mc < RO(Shm)->Uncore.CtrlCount && !clock_done;
mc++)
@@ -5147,7 +5139,8 @@
if (RO(Proc)->Uncore.Bus.RKL_SA_Pll.QCLK_RATIO == 0)
{
RO(Shm)->Uncore.CtrlSpeed = (266 * units) + ((334 * units) / 501);
- RO(Shm)->Uncore.Unit.DDRSpeed = MC_MTS;
+
+ Bus_Rate = Bus_Rate * 100U;
}
else /* Is Memory frequency overclocked ? */
{
@@ -5155,18 +5148,30 @@
if (RO(Proc)->Uncore.Bus.RKL_SA_Pll.QCLK_REF == 0) {
Freq_Hz = RO(Proc)->Uncore.Bus.RKL_SA_Pll.QCLK_RATIO;
- Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 400LLU;
+ Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 800LLU;
Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
Freq_Hz = Freq_Hz / 3LLU;
+
+ Bus_Rate = Bus_Rate * 400U;
+ Bus_Rate = Bus_Rate / 3U;
} else {
Freq_Hz = RO(Proc)->Uncore.Bus.RKL_SA_Pll.QCLK_RATIO;
- Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 100LLU;
+ Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 200LLU;
Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+ Bus_Rate = Bus_Rate * 100U;
}
RO(Shm)->Uncore.CtrlSpeed = (unsigned short) Freq_Hz;
- RO(Shm)->Uncore.Unit.DDRSpeed = MC_MHZ;
}
+ RO(Shm)->Uncore.Bus.Rate = Bus_Rate;
+ RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
+ * RO(Shm)->Uncore.Bus.Rate)
+ / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+ RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
+ RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
RO(Shm)->Uncore.Unit.DDR_Rate = MC_NIL;
+ RO(Shm)->Uncore.Unit.DDRSpeed = MC_MTS;
RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.RKL_Cap_A.VT_d;
@@ -5626,22 +5631,9 @@
void ADL_CAP(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) *RO(Core))
{
unsigned int units = 12;
+ unsigned int Bus_Rate = RO(Proc)->Uncore.Bus.BIOS_DDR.MC_PLL_RATIO;
unsigned short mc, clock_done;
- if (RO(Proc)->Uncore.Bus.ADL_SA_Pll.UCLK_RATIO > 0) {/* Ring Interconnect
*/
- RO(Shm)->Uncore.Bus.Rate = RO(Proc)->Uncore.Bus.ADL_SA_Pll.UCLK_RATIO;
- RO(Shm)->Uncore.Bus.Rate *= 100;
- RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
- RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
- } else { /* Advertised Bus Speed */
- RO(Shm)->Uncore.Bus.Rate = 8000;
- RO(Shm)->Uncore.Unit.Bus_Rate = MC_MTS;
- RO(Shm)->Uncore.Unit.BusSpeed = MC_MTS;
- }
- RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
- * RO(Shm)->Uncore.Bus.Rate)
- / RO(Shm)->Proc.Features.Factory.Clock.Hz;
-
for (mc = 0, clock_done = 0;
mc < RO(Shm)->Uncore.CtrlCount && !clock_done;
mc++)
@@ -5699,7 +5691,8 @@
if (RO(Proc)->Uncore.Bus.ADL_SA_Pll.QCLK_RATIO == 0)
{
RO(Shm)->Uncore.CtrlSpeed = (266 * units) + ((334 * units) / 501);
- RO(Shm)->Uncore.Unit.DDRSpeed = MC_MTS;
+
+ Bus_Rate = Bus_Rate * 100U;
}
else /* Is Memory frequency overclocked ? */
{
@@ -5707,18 +5700,30 @@
if (RO(Proc)->Uncore.Bus.ADL_SA_Pll.QCLK_REF == 0) {
Freq_Hz = RO(Proc)->Uncore.Bus.ADL_SA_Pll.QCLK_RATIO;
- Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 400LLU;
+ Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 800LLU;
Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
Freq_Hz = Freq_Hz / 3LLU;
+
+ Bus_Rate = Bus_Rate * 400U;
+ Bus_Rate = Bus_Rate / 3U;
} else {
Freq_Hz = RO(Proc)->Uncore.Bus.ADL_SA_Pll.QCLK_RATIO;
- Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 100LLU;
+ Freq_Hz = Freq_Hz * RO(Core)->Clock.Hz * 200LLU;
Freq_Hz = Freq_Hz / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+ Bus_Rate = Bus_Rate * 100U;
}
RO(Shm)->Uncore.CtrlSpeed = (unsigned short) Freq_Hz;
- RO(Shm)->Uncore.Unit.DDRSpeed = MC_MHZ;
}
+ RO(Shm)->Uncore.Bus.Rate = Bus_Rate;
+ RO(Shm)->Uncore.Bus.Speed = (RO(Core)->Clock.Hz
+ * RO(Shm)->Uncore.Bus.Rate)
+ / RO(Shm)->Proc.Features.Factory.Clock.Hz;
+
+ RO(Shm)->Uncore.Unit.Bus_Rate = MC_MHZ;
+ RO(Shm)->Uncore.Unit.BusSpeed = MC_MHZ;
RO(Shm)->Uncore.Unit.DDR_Rate = MC_NIL;
+ RO(Shm)->Uncore.Unit.DDRSpeed = MC_MTS;
RO(Shm)->Proc.Technology.IOMMU = !RO(Proc)->Uncore.Bus.ADL_Cap_A.VT_d;
@@ -6434,6 +6439,7 @@
[IC_W680] = "Intel W680",
[IC_WM690] = "Intel WM690",
[IC_HM670] = "Intel HM670",
+ [IC_ADL_PCH_P] = "Intel ADL PCH-P",
[IC_Z790] = "Intel Z790",
[IC_H770] = "Intel H770",
[IC_B760] = "Intel B760",
@@ -6927,6 +6933,9 @@
case DID_INTEL_ALDERLAKE_HM670_PCH:
SET_CHIPSET(IC_HM670);
break;
+ case DID_INTEL_ALDERLAKE_PCH_P:
+ SET_CHIPSET(IC_ADL_PCH_P);
+ break;
case DID_INTEL_GEMINILAKE_HB:
GLK_CAP(RO(Shm), RO(Proc), RO(Core));
GLK_IMC(RO(Shm), RO(Proc));
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/corefreqk.c
new/CoreFreq-1.95.4/corefreqk.c
--- old/CoreFreq-1.95.2/corefreqk.c 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/corefreqk.c 2023-02-19 00:29:35.000000000 +0100
@@ -5102,6 +5102,7 @@
}
if (mc == 0) {
Query_Turbo_TDP_Config(mchmap);
+ BIOS_DDR(mchmap);
RKL_SA(mchmap);
}
}
@@ -5112,8 +5113,16 @@
{ /*Source: 11th Generation Intel® Core Processor Datasheet Vol 2 */
unsigned short cha;
+ PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0;
+ PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 0;
+
/* Intra channel configuration */
PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADCH.value = readl(mchmap+0x5000);
+
+ if (PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADCH.value == 0xffffffff)
+ {
+ goto EXIT_TGL_IMC;
+ }
if (PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADCH.CH_L_MAP)
{
PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADC0.value = readl(mchmap+0x5008);
@@ -5122,9 +5131,20 @@
PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADC0.value = readl(mchmap+0x5004);
PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADC1.value = readl(mchmap+0x5008);
}
+ if ( (PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADC0.value == 0xffffffff)
+ || (PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADC1.value == 0xffffffff) )
+ {
+ goto EXIT_TGL_IMC;
+ }
/* DIMM parameters */
PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADD0.value = readl(mchmap+0x500c);
PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADD1.value = readl(mchmap+0x5010);
+
+ if ( (PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADD0.value == 0xffffffff)
+ || (PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADD1.value == 0xffffffff) )
+ {
+ goto EXIT_TGL_IMC;
+ }
/* Sum up any present DIMM per channel. */
PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = \
((PUBLIC(RO(Proc))->Uncore.MC[mc].TGL.MADD0.Dimm_L_Size != 0)
@@ -5171,18 +5191,28 @@
}
if (mc == 0) {
Query_Turbo_TDP_Config(mchmap);
+ BIOS_DDR(mchmap);
TGL_SA(mchmap);
}
+EXIT_TGL_IMC:
}
#define ADL_SA TGL_SA
void Query_ADL_IMC(void __iomem *mchmap, unsigned short mc)
{ /*Source: 12th Generation Intel® Core Processor Datasheet Vol 2 */
- unsigned short cha, channelCount;
+ unsigned short cha;
+
+ PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0;
+ PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 0;
/* Intra channel configuration */
PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value = readl(mchmap+0xd800);
+
+ if (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value == 0xffffffff)
+ {
+ goto EXIT_ADL_IMC;
+ }
if (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.CH_L_MAP)
{
PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADC0.value = readl(mchmap+0xd808);
@@ -5191,18 +5221,34 @@
PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADC0.value = readl(mchmap+0xd804);
PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADC1.value = readl(mchmap+0xd808);
}
+ if ( (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADC0.value == 0xffffffff)
+ || (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADC1.value == 0xffffffff) )
+ {
+ goto EXIT_ADL_IMC;
+ }
/* DIMM parameters */
PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.value = readl(mchmap+0xd80c);
PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.value = readl(mchmap+0xd810);
+
+ if ( (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.value == 0xffffffff)
+ || (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.value == 0xffffffff) )
+ {
+ goto EXIT_ADL_IMC;
+ }
+ /* Check for 2 DIMMs Per Channel is enabled */
+ if (PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_A.DDPCD == 0) {
+ PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 2;
+ } else {
/* Guessing activated channel from the populated DIMM. */
- channelCount = \
+ PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = \
((PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.Dimm_L_Size != 0)
|| (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD0.Dimm_S_Size != 0))
+ ((PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.Dimm_L_Size != 0)
|| (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADD1.Dimm_S_Size != 0));
+ }
+ PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 2;
- for (cha = 0 ; (cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount)
- && (cha < channelCount); cha++)
+ for (cha = 0 ; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++)
{
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].ADL.Timing.value = \
readq(mchmap + 0xe000 + 0x800 * cha);
@@ -5239,8 +5285,10 @@
}
if (mc == 0) {
Query_Turbo_TDP_Config(mchmap);
+ BIOS_DDR(mchmap);
ADL_SA(mchmap);
}
+EXIT_ADL_IMC:
}
void Query_GLK_IMC(void __iomem *mchmap, unsigned short mc)
@@ -5351,7 +5399,7 @@
#undef WDT_Technology
-static PCI_CALLBACK SoC_SLM(struct pci_dev *dev)
+static PCI_CALLBACK SoC_MCR(struct pci_dev *dev)
{/* DRP */
PCI_MCR MsgCtrlReg = {
.MBZ = 0, .Bytes = 0, .Offset = 0x0, .Port = 0x1, .OpCode = 0x10
@@ -5412,6 +5460,14 @@
pci_read_config_dword(dev, 0xd4,
&PUBLIC(RO(Proc))->Uncore.MC[0].SLM.BIOS_CFG.value);
+ return (PCI_CALLBACK) 0;
+}
+
+static PCI_CALLBACK SoC_SLM(struct pci_dev *dev)
+{
+ PCI_CALLBACK rc = SoC_MCR(dev);
+ if ((PCI_CALLBACK) 0 == rc)
+ {
PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
PUBLIC(RO(Proc))->Uncore.MC[0].ChannelCount = 1
@@ -5425,7 +5481,24 @@
PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRP.RKEN2
| PUBLIC(RO(Proc))->Uncore.MC[0].SLM.DRP.RKEN3
);
- return (PCI_CALLBACK) 0;
+ }
+ return rc;
+}
+
+static PCI_CALLBACK SoC_AMT(struct pci_dev *dev)
+{
+ PCI_CALLBACK rc = SoC_MCR(dev);
+ if ((PCI_CALLBACK) 0 == rc)
+ {
+ PUBLIC(RO(Proc))->Uncore.CtrlCount = 1;
+
+ PUBLIC(RO(Proc))->Uncore.MC[0].ChannelCount = 1
+ + ( PUBLIC(RO(Proc))->Uncore.MC[0].SLM.BIOS_CFG.EFF_DUAL_CH_EN
+ | !PUBLIC(RO(Proc))->Uncore.MC[0].SLM.BIOS_CFG.DUAL_CH_DIS );
+
+ PUBLIC(RO(Proc))->Uncore.MC[0].SlotCount = 1;
+ }
+ return rc;
}
static PCI_CALLBACK Lynnfield_IMC(struct pci_dev *dev)
@@ -6029,21 +6102,27 @@
PCI_CALLBACK rc = 0;
unsigned short mc;
- PUBLIC(RO(Proc))->Uncore.CtrlCount = 2;
+ PUBLIC(RO(Proc))->Uncore.CtrlCount = 0;
/* Controller #0 is not necessary activated but enabled. */
- for (mc = 0; mc < PUBLIC(RO(Proc))->Uncore.CtrlCount; mc++) {
+ for (mc = 0; mc < MC_MAX_CTRL; mc++)
+ {
rc = SKL_HOST(dev, Query_TGL_IMC, 0x10000, mc);
+
+ if ( ((PCI_CALLBACK) 0 == rc)
+ && (PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount > 0) ) {
+ PUBLIC(RO(Proc))->Uncore.CtrlCount = mc + 1;
+ }
}
pci_read_config_dword(dev, 0xf0,
&PUBLIC(RO(Proc))->Uncore.Bus.TGL_Cap_E.value);
return rc;
}
-static PCI_CALLBACK ADL_IMC(struct pci_dev *dev)
-{ /* Source: 12th Generation Intel Core Processors datasheet, vol 2 */
- PCI_CALLBACK rc = 0;
- unsigned short mc, cha;
-
+static PCI_CALLBACK ADL_HOST( struct pci_dev *dev,
+ ROUTER Query,
+ unsigned long long wsize,
+ unsigned short mc )
+{
pci_read_config_dword(dev, 0xe4,
&PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_A.value);
@@ -6056,21 +6135,25 @@
pci_read_config_dword(dev, 0xf0,
&PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_E.value);
- /* MCHBAR corresponds to bits 41 to 17 ; two MC x 64KB memory space */
- PUBLIC(RO(Proc))->Uncore.CtrlCount = 2;
- for (mc = 0; mc < PUBLIC(RO(Proc))->Uncore.CtrlCount; mc++)
- { /* 2 DIMMs Per Channel Enable */
- if (PUBLIC(RO(Proc))->Uncore.Bus.ADL_Cap_A.DDPCD == 0) {
- PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 2;
- } else {
- PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 1;
- }
- PUBLIC(RO(Proc))->Uncore.MC[mc].SlotCount = 2;
+ SoC_SKL_VTD();
- rc = SKL_HOST(dev, Query_ADL_IMC, 0x10000, mc);
+ return Router(dev, 0x48, 64, wsize, Query, mc);
+}
+
+static PCI_CALLBACK ADL_IMC(struct pci_dev *dev)
+{ /* Source: 12th Generation Intel Core Processors datasheet, vol 2 */
+ PCI_CALLBACK rc = 0;
+ unsigned short mc, cha;
- if ((PCI_CALLBACK) 0 == rc) {
- if (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value) {
+ PUBLIC(RO(Proc))->Uncore.CtrlCount = 0;
+ /* MCHBAR matches bits 41 to 17 ; two MC x 64KB memory space */
+ for (mc = 0; mc < MC_MAX_CTRL; mc++)
+ {
+ rc = ADL_HOST(dev, Query_ADL_IMC, 0x10000, mc);
+
+ if ( (PCI_CALLBACK) 0 == rc)
+ {
+ if (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value != 0xffffffff) {
switch (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.DDR_TYPE) {
case 0b01: /* DDR5 */
case 0b10: /* LPDDR5 */
@@ -6085,6 +6168,10 @@
break;
}
}
+ if (PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount > 0)
+ {
+ PUBLIC(RO(Proc))->Uncore.CtrlCount = mc + 1;
+ }
}
}
return rc;
@@ -9418,6 +9505,10 @@
PCI_VDEVICE(INTEL, DID_INTEL_PCH_600_SMBUS),
.driver_data = (kernel_ulong_t) TCOBASE
},
+ {
+ PCI_VDEVICE(INTEL, DID_INTEL_PCH_P_SMBUS),
+ .driver_data = (kernel_ulong_t) TCOBASE
+ },
{0, }
};
if (CoreFreqK_ProbePCI(PCI_WDT_ids, NULL, NULL) < RC_SUCCESS) {
@@ -14110,6 +14201,27 @@
PUBLIC(RO(Proc))->Counter[_T].MC6 = \
readq(PRIVATE(OF(PCU)).BAR + PRIVATE(OF(PCU)).ADDR); \
} \
+ switch (PUBLIC(RO(Proc))->ArchID) { \
+ case Tigerlake: \
+ case Tigerlake_U: \
+ TGL_SA(PRIVATE(OF(PCU)).BAR); \
+ break; \
+ case Rocketlake: \
+ case Rocketlake_U: \
+ RKL_SA(PRIVATE(OF(PCU)).BAR); \
+ break; \
+ case Alderlake_S: \
+ case Alderlake_H: \
+ case Alderlake_N: \
+ case Meteorlake_M: \
+ case Meteorlake_N: \
+ case Meteorlake_S: \
+ case Raptorlake: \
+ case Raptorlake_P: \
+ case Raptorlake_S: \
+ ADL_SA(PRIVATE(OF(PCU)).BAR); \
+ break; \
+ } \
} \
})
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/corefreqk.h
new/CoreFreq-1.95.4/corefreqk.h
--- old/CoreFreq-1.95.2/corefreqk.h 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/corefreqk.h 2023-02-19 00:29:35.000000000 +0100
@@ -1827,6 +1827,9 @@
#define _Cannonlake_U {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x6, .Model=0x6}
#define _Cannonlake_H {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x6, .Model=0x7}
+/* [Spreadtrum] 06_75h SC9853I-IA */
+#define _Spreadtrum {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x7, .Model=0x5}
+
/* [Gemini Lake] 06_7Ah */
#define _Geminilake {.ExtFamily=0x0, .Family=0x6, .ExtModel=0x7, .Model=0xA}
@@ -1999,6 +2002,7 @@
static PCI_CALLBACK G965(struct pci_dev *dev) ;
static PCI_CALLBACK P35(struct pci_dev *dev) ;
static PCI_CALLBACK SoC_SLM(struct pci_dev *dev) ;
+static PCI_CALLBACK SoC_AMT(struct pci_dev *dev) ;
static PCI_CALLBACK Nehalem_IMC(struct pci_dev *dev) ;
#define Bloomfield_IMC Nehalem_IMC
static PCI_CALLBACK Lynnfield_IMC(struct pci_dev *dev) ;
@@ -2159,7 +2163,7 @@
},
{ /* Atom - Airmont */
PCI_VDEVICE(INTEL, DID_INTEL_AIRMONT_HB),
- .driver_data = (kernel_ulong_t) SoC_SLM
+ .driver_data = (kernel_ulong_t) SoC_AMT
},
{0, }
};
@@ -2847,6 +2851,10 @@
PCI_VDEVICE(INTEL, DID_INTEL_ALDERLAKE_HM670_PCH),
.driver_data = (kernel_ulong_t) ADL_PCH
},
+ {
+ PCI_VDEVICE(INTEL, DID_INTEL_ALDERLAKE_PCH_P),
+ .driver_data = (kernel_ulong_t) ADL_PCH
+ },
/* 13th Generation */
{
PCI_VDEVICE(INTEL, DID_INTEL_RAPTORLAKE_S_8P_16E_HB),
@@ -9054,7 +9062,31 @@
.Architecture = Arch_Cannonlake_H
},
-[Geminilake] = { /* 56*/
+[Spreadtrum] = { /* 56*/
+ .Signature = _Spreadtrum,
+ .Query = Query_Airmont,
+ .Update = PerCore_Airmont_Query,
+ .Start = Start_Silvermont,
+ .Stop = Stop_Silvermont,
+ .Exit = NULL,
+ .Timer = InitTimer_Silvermont,
+ .BaseClock = BaseClock_Airmont,
+ .ClockMod = ClockMod_Core2_PPC,
+ .TurboClock = NULL,
+ .thermalFormula = THERMAL_FORMULA_INTEL,
+ .voltageFormula = VOLTAGE_FORMULA_INTEL_SOC,
+ .powerFormula = POWER_FORMULA_INTEL_ATOM,
+ .PCI_ids = PCI_Void_ids,
+ .Uncore = {
+ .Start = NULL,
+ .Stop = NULL,
+ .ClockMod = NULL
+ },
+ .Specific = Void_Specific,
+ .SystemDriver = Airmont_Driver,
+ .Architecture = Arch_Atom_Airmont
+ },
+[Geminilake] = { /* 57*/
.Signature = _Geminilake,
.Query = Query_Goldmont,
.Update = PerCore_Geminilake_Query,
@@ -9079,7 +9111,7 @@
.Architecture = Arch_Geminilake
},
-[Icelake] = { /* 57*/
+[Icelake] = { /* 58*/
.Signature = _Icelake,
.Query = Query_Kaby_Lake,
.Update = PerCore_Skylake_Query,
@@ -9103,7 +9135,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Icelake
},
-[Icelake_UY] = { /* 58*/
+[Icelake_UY] = { /* 59*/
.Signature = _Icelake_UY,
.Query = Query_Kaby_Lake,
.Update = PerCore_Skylake_Query,
@@ -9127,7 +9159,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Icelake_UY
},
-[Icelake_X] = { /* 59*/
+[Icelake_X] = { /* 60*/
.Signature = _Icelake_X,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9151,7 +9183,7 @@
.SystemDriver = ICX_Driver,
.Architecture = Arch_Icelake_X
},
-[Icelake_D] = { /* 60*/
+[Icelake_D] = { /* 61*/
.Signature = _Icelake_D,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9176,7 +9208,7 @@
.Architecture = Arch_Icelake_D
},
-[Sunny_Cove] = { /* 61*/
+[Sunny_Cove] = { /* 62*/
.Signature = _Sunny_Cove,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9201,7 +9233,7 @@
.Architecture = Arch_Sunny_Cove
},
-[Tigerlake] = { /* 62*/
+[Tigerlake] = { /* 63*/
.Signature = _Tigerlake,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9225,7 +9257,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Tigerlake
},
-[Tigerlake_U] = { /* 63*/
+[Tigerlake_U] = { /* 64*/
.Signature = _Tigerlake_U,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9250,7 +9282,7 @@
.Architecture = Arch_Tigerlake_U
},
-[Cometlake] = { /* 64*/
+[Cometlake] = { /* 65*/
.Signature = _Cometlake,
.Query = Query_Kaby_Lake,
.Update = PerCore_Skylake_Query,
@@ -9274,7 +9306,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Cometlake
},
-[Cometlake_UY] = { /* 65*/
+[Cometlake_UY] = { /* 66*/
.Signature = _Cometlake_UY,
.Query = Query_Kaby_Lake,
.Update = PerCore_Skylake_Query,
@@ -9299,7 +9331,7 @@
.Architecture = Arch_Cometlake_UY
},
-[Atom_Denverton] = { /* 66*/
+[Atom_Denverton] = { /* 67*/
.Signature = _Atom_Denverton,
.Query = Query_Goldmont,
.Update = PerCore_Goldmont_Query,
@@ -9323,7 +9355,7 @@
.SystemDriver = SNB_Driver,
.Architecture = Arch_Atom_Denverton
},
-[Tremont_Jacobsville] = { /* 67*/
+[Tremont_Jacobsville] = { /* 68*/
.Signature = _Tremont_Jacobsville,
.Query = Query_Goldmont,
.Update = PerCore_Goldmont_Query,
@@ -9347,7 +9379,7 @@
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Jacobsville
},
-[Tremont_Lakefield] = { /* 68*/
+[Tremont_Lakefield] = { /* 69*/
.Signature = _Tremont_Lakefield,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9371,7 +9403,7 @@
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Lakefield
},
-[Tremont_Elkhartlake] = { /* 69*/
+[Tremont_Elkhartlake] = { /* 70*/
.Signature = _Tremont_Elkhartlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9395,7 +9427,7 @@
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Elkhartlake
},
-[Tremont_Jasperlake] = { /* 70*/
+[Tremont_Jasperlake] = { /* 71*/
.Signature = _Tremont_Jasperlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9419,7 +9451,7 @@
.SystemDriver = Intel_Driver,
.Architecture = Arch_Tremont_Jasperlake
},
-[Sapphire_Rapids] = { /* 71*/
+[Sapphire_Rapids] = { /* 72*/
.Signature = _Sapphire_Rapids,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9443,7 +9475,7 @@
.SystemDriver = Intel_Driver,
.Architecture = Arch_Sapphire_Rapids
},
-[Emerald_Rapids] = { /* 72*/
+[Emerald_Rapids] = { /* 73*/
.Signature = _Emerald_Rapids,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9468,7 +9500,7 @@
.Architecture = Arch_Emerald_Rapids
},
-[Rocketlake] = { /* 73*/
+[Rocketlake] = { /* 74*/
.Signature = _Rocketlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9492,7 +9524,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Rocketlake
},
-[Rocketlake_U] = { /* 74*/
+[Rocketlake_U] = { /* 75*/
.Signature = _Rocketlake_U,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9517,7 +9549,7 @@
.Architecture = Arch_Rocketlake_U
},
-[Alderlake_S] = { /* 75*/
+[Alderlake_S] = { /* 76*/
.Signature = _Alderlake_S,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9541,7 +9573,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Alderlake_S
},
-[Alderlake_H] = { /* 76*/
+[Alderlake_H] = { /* 77*/
.Signature = _Alderlake_H,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9565,7 +9597,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Alderlake_H
},
-[Alderlake_N] = { /* 77*/
+[Alderlake_N] = { /* 78*/
.Signature = _Alderlake_N,
.Query = Query_Skylake,
.Update = PerCore_Kaby_Lake_Query,
@@ -9590,7 +9622,7 @@
.Architecture = Arch_Alderlake_N
},
-[Meteorlake_M] = { /* 78*/
+[Meteorlake_M] = { /* 79*/
.Signature = _Meteorlake_M,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9614,7 +9646,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Meteorlake_M
},
-[Meteorlake_N] = { /* 79*/
+[Meteorlake_N] = { /* 80*/
.Signature = _Meteorlake_N,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9638,7 +9670,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Meteorlake_N
},
-[Meteorlake_S] = { /* 80*/
+[Meteorlake_S] = { /* 81*/
.Signature = _Meteorlake_S,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9662,7 +9694,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Meteorlake_S
},
-[Raptorlake] = { /* 81*/
+[Raptorlake] = { /* 82*/
.Signature = _Raptorlake,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9686,7 +9718,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Raptorlake
},
-[Raptorlake_P] = { /* 82*/
+[Raptorlake_P] = { /* 83*/
.Signature = _Raptorlake_P,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9710,7 +9742,7 @@
.SystemDriver = SKL_Driver,
.Architecture = Arch_Raptorlake_P
},
-[Raptorlake_S] = { /* 83*/
+[Raptorlake_S] = { /* 84*/
.Signature = _Raptorlake_S,
.Query = Query_Skylake,
.Update = PerCore_Skylake_Query,
@@ -9735,7 +9767,7 @@
.Architecture = Arch_Raptorlake_S
},
-[AMD_Zen] = { /* 84*/
+[AMD_Zen] = { /* 85*/
.Signature = _AMD_Zen,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9759,7 +9791,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen
},
-[AMD_Zen_APU] = { /* 85*/
+[AMD_Zen_APU] = { /* 86*/
.Signature = _AMD_Zen_APU,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9783,7 +9815,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen_APU
},
-[AMD_ZenPlus] = { /* 86*/
+[AMD_ZenPlus] = { /* 87*/
.Signature = _AMD_ZenPlus,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9807,7 +9839,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_ZenPlus
},
-[AMD_ZenPlus_APU] = { /* 87*/
+[AMD_ZenPlus_APU] = { /* 88*/
.Signature = _AMD_ZenPlus_APU,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9831,7 +9863,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_ZenPlus_APU
},
-[AMD_Zen_Dali] = { /* 88*/
+[AMD_Zen_Dali] = { /* 89*/
.Signature = _AMD_Zen_Dali,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9855,7 +9887,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen_Dali
},
-[AMD_EPYC_Rome_CPK] = { /* 89*/
+[AMD_EPYC_Rome_CPK] = { /* 90*/
.Signature = _AMD_EPYC_Rome_CPK,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9879,7 +9911,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_EPYC_Rome_CPK
},
-[AMD_Zen2_Renoir] = { /* 90*/
+[AMD_Zen2_Renoir] = { /* 91*/
.Signature = _AMD_Zen2_Renoir,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9903,7 +9935,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_Renoir
},
-[AMD_Zen2_LCN] = { /* 91*/
+[AMD_Zen2_LCN] = { /* 92*/
.Signature = _AMD_Zen2_LCN,
.Query = Query_AMD_F17h_PerSocket,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9927,7 +9959,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_LCN
},
-[AMD_Zen2_MTS] = { /* 92*/
+[AMD_Zen2_MTS] = { /* 93*/
.Signature = _AMD_Zen2_MTS,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9951,7 +9983,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_MTS
},
-[AMD_Zen2_Ariel] = { /* 93*/
+[AMD_Zen2_Ariel] = { /* 94*/
.Signature = _AMD_Zen2_Ariel,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9975,7 +10007,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_Ariel
},
-[AMD_Zen2_Jupiter] = { /* 94*/
+[AMD_Zen2_Jupiter] = { /* 95*/
.Signature = _AMD_Zen2_Jupiter,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -9999,7 +10031,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_Jupiter
},
-[AMD_Zen2_MDN] = { /* 95*/
+[AMD_Zen2_MDN] = { /* 96*/
.Signature = _AMD_Zen2_MDN,
.Query = Query_AMD_F17h_PerCluster,
.Update = PerCore_AMD_Family_17h_Query,
@@ -10023,7 +10055,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen2_MDN
},
-[AMD_Zen3_VMR] = { /* 96*/
+[AMD_Zen3_VMR] = { /* 97*/
.Signature = _AMD_Zen3_VMR,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10047,7 +10079,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_VMR
},
-[AMD_Zen3_CZN] = { /* 97*/
+[AMD_Zen3_CZN] = { /* 98*/
.Signature = _AMD_Zen3_CZN,
.Query = Query_AMD_F19h_PerSocket,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10071,7 +10103,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_CZN
},
-[AMD_EPYC_Milan] = { /* 98*/
+[AMD_EPYC_Milan] = { /* 99*/
.Signature = _AMD_EPYC_Milan,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10095,7 +10127,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_EPYC_Milan
},
-[AMD_Zen3_Chagall] = { /* 99*/
+[AMD_Zen3_Chagall] = { /*100*/
.Signature = _AMD_Zen3_Chagall,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10119,7 +10151,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_Chagall
},
-[AMD_Zen3_Badami] = { /*100*/
+[AMD_Zen3_Badami] = { /*101*/
.Signature = _AMD_Zen3_Badami,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10143,7 +10175,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3_Badami
},
-[AMD_Zen3Plus_RMB] = { /*101*/
+[AMD_Zen3Plus_RMB] = { /*102*/
.Signature = _AMD_Zen3Plus_RMB,
.Query = Query_AMD_F19h_PerSocket,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10167,7 +10199,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen3Plus_RMB
},
-[AMD_Zen4_Genoa] = { /*102*/
+[AMD_Zen4_Genoa] = { /*103*/
.Signature = _AMD_Zen4_Genoa,
.Query = Query_AMD_F19h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
@@ -10191,7 +10223,7 @@
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen4_Genoa
},
-[AMD_Zen4_RPL] = { /*103*/
+[AMD_Zen4_RPL] = { /*104*/
.Signature = _AMD_Zen4_RPL,
.Query = Query_AMD_F19h_61h_PerCluster,
.Update = PerCore_AMD_Family_19h_Query,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/coretypes.h
new/CoreFreq-1.95.4/coretypes.h
--- old/CoreFreq-1.95.2/coretypes.h 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/coretypes.h 2023-02-19 00:29:35.000000000 +0100
@@ -6,7 +6,7 @@
#define COREFREQ_MAJOR 1
#define COREFREQ_MINOR 95
-#define COREFREQ_REV 2
+#define COREFREQ_REV 4
#if !defined(CORE_COUNT)
#define CORE_COUNT 256
@@ -83,6 +83,7 @@
Kabylake_UY,
Cannonlake_U,
Cannonlake_H,
+ Spreadtrum,
Geminilake,
Icelake,
Icelake_UY,
@@ -134,7 +135,6 @@
ARCHITECTURES
};
-
enum HYBRID_ARCH {
Hybrid_RSVD1 = 0x10,
Hybrid_Atom = 0x20,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.95.2/intel_reg.h
new/CoreFreq-1.95.4/intel_reg.h
--- old/CoreFreq-1.95.2/intel_reg.h 2023-02-05 15:34:56.000000000 +0100
+++ new/CoreFreq-1.95.4/intel_reg.h 2023-02-19 00:29:35.000000000 +0100
@@ -2533,7 +2533,7 @@
ECCEN : 22-21, /* ECC 0:Disabled - 1: Enable */
DRAMTYPE : 24-22,
Rsvd_4 : 32-24;
- } Z8000;
+ } AMT;
} SOC_MC_DRP;
typedef union /* MCR: Port=0x01 & Offset=0x1 */
@@ -2572,7 +2572,7 @@
tZQoper : 24-22,
PMEDLY : 26-24,
CKEDLY : 32-26;
- } Z8000;
+ } AMT;
} SOC_MC_DTR0;
typedef union /* MCR: Port=0x01 & Offset=0x2 */
@@ -2607,7 +2607,7 @@
tRAS : 26-21,
tRRD : 29-26,
tRTP : 32-29;
- } Z8000;
+ } AMT;
} SOC_MC_DTR1;
typedef union /* MCR: Port=0x01 & Offset=0x3 */
@@ -2638,7 +2638,7 @@
tRWDR : 20-15,
DFREQ : 23-20, /* DDR3{800,1066,1333,1600,1867,2133}*/
nREFI : 32-23; /* = (DRAM_Clock) / 32 */
- } Z8000;
+ } AMT;
} SOC_MC_DTR2;
typedef union /* MCR: Port=0x01 & Offset=0x4 */
@@ -2672,7 +2672,7 @@
tXP : 24-20,
PWDDLY : 28-24,
Rsvd4_DTR3 : 32-28;
- } Z8000;
+ } AMT;
} SOC_MC_DTR3;
typedef union /* MCR: Port=0x01 & Offset=0x5 */
@@ -2708,7 +2708,7 @@
WRBODTDIS : 19-18, /*Disable Write ODT non-targeted DIMM*/
Rsvd_27 : 23-19,
nRFCab : 32-23; /*Define tRFC(DDR3), tRFCab(LPDDR2/3)*/
- } Z8000;
+ } AMT;
} SOC_MC_DTR4;
typedef union /* MCR: Port=0x01 & Offset=0x6 */
@@ -2745,7 +2745,7 @@
WFZQEN : 23-22, /* Enable ZQ Calibration in WAKEF */
CSTRIST : 24-23, /*Tristate Chip-Select:SRE to SRX+tXS*/
PASR : 32-24; /* Refresh SUSPEND Partial MR17 */
- } Z8000;
+ } AMT;
} SOC_MC_DPMC0;
typedef union /* MCR: Port=0x01 & Offset=0x7 */
@@ -2772,7 +2772,7 @@
CLKGTDIS : 28-27, /* Clock Gating Disabled */
REUTCLKGTDIS : 29-28, /* REUT Clock Gate Disabled */
tWTW : 32-29;
- } Z8000;
+ } AMT;
} SOC_MC_DPMC1;
typedef union /* MCR: Port=0x01 & Offset=0x8 */
@@ -2805,7 +2805,7 @@
REFSKWDIS : 21-20,
REFDBTCLR : 22-21,
Rsvd_DRFC_0 : 32-22;
- } Z8000;
+ } AMT;
} SOC_MC_DRFC;
typedef union /* MCR: Port=0x01 & Offset=0xB */
@@ -2835,7 +2835,7 @@
COLDWAKE : 17-16,
DBPTRCLR : 18-17,
Rsvd_18 : 32-18;
- } Z8000;
+ } AMT;
} SOC_MC_DRMC;
typedef union /* MCR: Port=0x04 & Offset=0x6 */
@@ -3147,6 +3147,16 @@
PLL_REF100 : 9-8, /* 0=133,33 MHz , 1=100,00 MHz */
ReservedBits2 : 32-9;
};
+ struct {
+ unsigned int
+ MC_PLL_RATIO : 8-0, /* Each bin is 133/100MHz */
+ MC_PLL_REF : 12-8, /* 0=133,33 MHz , 1=100,00 MHz */
+ GEAR : 14-12, /* 0:QCLK; 1:2xQCLK; 2:4xQCLK */
+ ReservedBits : 17-14,
+ REQ_VDDQ_TX_VOLT: 27-17,
+ REQ_VDDQ_TX_ICC : 31-27,
+ RUN_BUSY : 32-31;
+ };
} BIOS_MEMCLOCK;
typedef union
