Script 'mail_helper' called by obssrc Hello community, here is the log from the commit of package cpuid for openSUSE:Factory checked in at 2023-04-14 15:40:05 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/cpuid (Old) and /work/SRC/openSUSE:Factory/.cpuid.new.19717 (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "cpuid" Fri Apr 14 15:40:05 2023 rev:18 rq:1079429 version:20230406 Changes: -------- --- /work/SRC/openSUSE:Factory/cpuid/cpuid.changes 2023-02-10 14:34:18.173555746 +0100 +++ /work/SRC/openSUSE:Factory/.cpuid.new.19717/cpuid.changes 2023-04-14 15:40:06.898834286 +0200 @@ -1,0 +2,32 @@ +Fri Apr 14 07:02:53 UTC 2023 - Egbert Eich <[email protected]> + +- Update to release 20230406: + * Support APIC bit fields for the newest 4 topology layers: + module, tile, die, die group. + * Support leaf 0xb method for AMD/Hygon. + * Added prelim Bergamo A1 stepping from sample. + * Added AMX-COMPLEX instructions, UC-lock disable, + non-contiguous 1s value support, event logging supported + bitmap. + * Update CPUID utility with new feature bits as documented in + the AMD Processor Programming Reference for Family 19h and + Model 11h: extended LVT offset fault cange, enhanced + predictive store forwarding, FSRS, FSRC, + FsGsKernelGsBaseNonSerializing, number of available UMC PMCs, + bitmask representing active UMCs. + * Added (synth) decoding for Sapphire Rapids D & E0 steppings + * Improved (synth) decoding for Scalable 3rd Gen Xeons to Ice + Lake-SP, for Intel N-Series, for Raptor Lake-S/HX/P, for + Raptor Lake-H/U/P. + * Differentiate (synth) & (uarch synth) for (0,6),(11,14) + Alder Lake-N based on core type. + * Differentiate Lakefield P-cores from Tremont E-cores. + * Added (4th Gen) to the (synth) description of AMD EPYC Genoa. + * Added (uarch synth) decoding for AMD Ryzen (Phoenix E0) + * Added PkgType decoding for AMD Family 19h CPUs: Vermeer, + Cezanne/Barcelo, Raphael, and Phoenix, based on their + respective PPPRs. + * Added Alder Lake Core names: i*-12000. + * Decode Xen tsc mode. + +------------------------------------------------------------------- @@ -4 +36 @@ -- updaet to 20230120: +- updated to 20230120: Old: ---- cpuid-20230120.src.tar.gz New: ---- cpuid-20230406.src.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ cpuid.spec ++++++ --- /var/tmp/diff_new_pack.mvzmig/_old 2023-04-14 15:40:07.366836984 +0200 +++ /var/tmp/diff_new_pack.mvzmig/_new 2023-04-14 15:40:07.370837006 +0200 @@ -17,7 +17,7 @@ Name: cpuid -Version: 20230120 +Version: 20230406 Release: 0 Summary: x86 CPU identification tool License: GPL-2.0-or-later ++++++ cpuid-20230120.src.tar.gz -> cpuid-20230406.src.tar.gz ++++++ ++++ 2080 lines of diff (skipped)
