Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package CoreFreq for openSUSE:Factory
checked in at 2023-07-05 15:31:36
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/CoreFreq (Old)
and /work/SRC/openSUSE:Factory/.CoreFreq.new.23466 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "CoreFreq"
Wed Jul 5 15:31:36 2023 rev:29 rq:1096931 version:1.96.5
Changes:
--------
--- /work/SRC/openSUSE:Factory/CoreFreq/CoreFreq.changes 2023-06-16
16:55:26.513919001 +0200
+++ /work/SRC/openSUSE:Factory/.CoreFreq.new.23466/CoreFreq.changes
2023-07-05 15:32:18.747190093 +0200
@@ -1,0 +2,10 @@
+Sat Jul 1 08:52:38 UTC 2023 - Michael Pujos <pujos.mich...@gmail.com>
+
+- update to 1.96.5
+ * [AMD]
+ Adding the "AMD Ryzen 5 5600X3D"
+ Introducing the Zen4c Bergamo architecture
+ Specs fixing of Embedded V-series and 3000 Series Processors
+ Adding MENDOCINO, RAPHAEL Pro, PHOENIX Pro among others
+
+-------------------------------------------------------------------
Old:
----
CoreFreq-1.96.4.tar.gz
New:
----
CoreFreq-1.96.5.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ CoreFreq.spec ++++++
--- /var/tmp/diff_new_pack.TbrAiN/_old 2023-07-05 15:32:19.287193297 +0200
+++ /var/tmp/diff_new_pack.TbrAiN/_new 2023-07-05 15:32:19.291193321 +0200
@@ -17,7 +17,7 @@
Name: CoreFreq
-Version: 1.96.4
+Version: 1.96.5
Release: 0
Summary: CPU monitoring software for 64-bit processors
License: GPL-2.0-or-later
++++++ CoreFreq-1.96.4.tar.gz -> CoreFreq-1.96.5.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.4/corefreq-cli.c
new/CoreFreq-1.96.5/corefreq-cli.c
--- old/CoreFreq-1.96.4/corefreq-cli.c 2023-06-11 12:01:08.000000000 +0200
+++ new/CoreFreq-1.96.5/corefreq-cli.c 2023-06-30 17:51:50.000000000 +0200
@@ -6955,6 +6955,7 @@
case AMD_Zen4_Genoa:
case AMD_Zen4_RPL:
case AMD_Zen4_PHX:
+ case AMD_Zen4_Bergamo:
TopologyFunc = Topology_CCD;
OffLineItem = RSC(TOPOLOGY_OFF_2).CODE();
TopologySubHeader[1] = TopologyAltSubHeader[2];
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.4/corefreqd.c
new/CoreFreq-1.96.5/corefreqd.c
--- old/CoreFreq-1.96.4/corefreqd.c 2023-06-11 12:01:08.000000000 +0200
+++ new/CoreFreq-1.96.5/corefreqd.c 2023-06-30 17:51:50.000000000 +0200
@@ -7238,6 +7238,7 @@
case AMD_Zen4_Genoa:
case AMD_Zen4_RPL:
case AMD_Zen4_PHX:
+ case AMD_Zen4_Bergamo:
case AMD_Family_17h:
case Hygon_Family_18h:
case AMD_Family_19h:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.4/corefreqk.c
new/CoreFreq-1.96.5/corefreqk.c
--- old/CoreFreq-1.96.4/corefreqk.c 2023-06-11 12:01:08.000000000 +0200
+++ new/CoreFreq-1.96.5/corefreqk.c 2023-06-30 17:51:50.000000000 +0200
@@ -2054,6 +2054,7 @@
case AMD_Zen4_Genoa:
case AMD_Zen4_RPL:
case AMD_Zen4_PHX:
+ case AMD_Zen4_Bergamo:
case AMD_Family_17h:
case Hygon_Family_18h:
case AMD_Family_19h:
@@ -2119,37 +2120,61 @@
{ /* SMT is enabled . */
Core->T.ThreadID = leaf8000001e.EAX.ExtApicId & 1;
- /* CCD factor for [x24 ... x128] SMT EPYC & Threadripper */
- factor = (leaf80000008.ECX.NC == 0x7f)
+ /* CCD factor for [x24 ... x256] SMT EPYC & Threadripper */
+ factor = (leaf80000008.ECX.NC == 0xff)
+ || (leaf80000008.ECX.NC == 0xdf)
+ || (leaf80000008.ECX.NC == 0xbf)
+ || (leaf80000008.ECX.NC == 0xa7)
+ || (leaf80000008.ECX.NC == 0x7f)
+ || (leaf80000008.ECX.NC == 0x5f)
|| (leaf80000008.ECX.NC == 0x3f)
|| (leaf80000008.ECX.NC == 0x2f)
|| ((leaf80000008.ECX.NC == 0x1f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)))
+ && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)))
|| ((leaf80000008.ECX.NC == 0x17)
&& ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
|| (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
|| (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)));
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)));
}
else
{ /* SMT is disabled. */
Core->T.ThreadID = 0;
- /* CCD factor for [x12 ... x64] physical EPYC & Threadripper */
- factor = (leaf80000008.ECX.NC == 0x3f)
+ /* CCD factor for [x12 ... x128] physical EPYC & Threadripper */
+ factor = (leaf80000008.ECX.NC == 0x7f)
+ || (leaf80000008.ECX.NC == 0x6f)
+ || (leaf80000008.ECX.NC == 0x5f)
+ || (leaf80000008.ECX.NC == 0x53)
+ || (leaf80000008.ECX.NC == 0x3f)
+ || (leaf80000008.ECX.NC == 0x2f)
|| (leaf80000008.ECX.NC == 0x1f)
|| (leaf80000008.ECX.NC == 0x17)
|| ((leaf80000008.ECX.NC == 0x0f)
- && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)))
+ && ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)))
|| ((leaf80000008.ECX.NC == 0x0b)
&& ((PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Rome_CPK)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_EPYC_Milan)
|| (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Chagall)
|| (PUBLIC(RO(Proc))->ArchID == AMD_Zen3_Badami)
- || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)));
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Genoa)
+ || (PUBLIC(RO(Proc))->ArchID == AMD_Zen4_Bergamo)));
}
/* CCD has to remain within range values from 0 to 7 */
factor = factor & (Core->T.CoreID < 32);
@@ -7671,6 +7696,7 @@
SMU_AMD_F17H_MATISSE_COF,
PRIVATE(OF(Zen)).Device.DF);
break;
+ case AMD_Zen4_Bergamo:
case AMD_Zen4_Genoa:
case AMD_EPYC_Rome_CPK:
Core_AMD_SMN_Read(XtraCOF,
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.4/corefreqk.h
new/CoreFreq-1.96.5/corefreqk.h
--- old/CoreFreq-1.96.4/corefreqk.h 2023-06-11 12:01:08.000000000 +0200
+++ new/CoreFreq-1.96.5/corefreqk.h 2023-06-30 17:51:50.000000000 +0200
@@ -1996,16 +1996,21 @@
[Zen3/Vermeer] AF_21h Stepping 0 7 nm
[Zen3/Cezanne] AF_50h Stepping 0 7 nm
[EPYC/Milan] AF_01h Stepping 1 7 nm [Genesis][GN]
- [EPYC/Milan-X] AF_01h Stepping 2 7 nm
+ [EPYC/Milan-X] AF_01h Stepping 2 7 nm SVR
[Zen3/Chagall] AF_08h Stepping 2 7 nm HEDT/TRX4
[Zen3/Badami] AF_30h 7 nm [BA]/SVR
[Zen3+ Rembrandt] AF_44h Stepping 1 6 nm [RMB]
[Zen4/Genoa] AF_11h Stepping 1 5 nm [GNA]/SVR
[Zen4/Raphael] AF_61h Stepping 2 5 nm [RPL]
[Zen4/Dragon Range] AF_61h Stepping 2 5 nm FL1
- [Zen4/Phoenix Point] AF_74h 4 nm [PHX] */
+ [Zen4/Phoenix Point] AF_74h 4 nm [PHX]
+ [Zen4c/Bergamo] AF_A0h Stepping 1 5 nm SVR */
/*
[Zen4/Storm Peak] AF_18h Stepping 1 HEDT/TR5
+ [Zen4/Genoa-X] ??_??h Stepping ? 5 nm
+ "AMD EPYC Embedded 9684X" .Boost = {+12, 0}
+ "AMD EPYC Embedded 9384X" .Boost = {+8, 0}
+ "AMD EPYC Embedded 9184X" .Boost = {+7, 0}
[Zen5/Granite Ridge] */
#define _AMD_Family_19h {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x0,
.Model=0x0}
#define _AMD_Zen3_VMR {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x2, .Model=0x1}
@@ -2021,6 +2026,8 @@
#define _AMD_Zen4_Genoa {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x1,
.Model=0x1}
#define _AMD_Zen4_RPL {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x6, .Model=0x1}
#define _AMD_Zen4_PHX {.ExtFamily=0xa, .Family=0xF, .ExtModel=0x7, .Model=0x4}
+#define _AMD_Zen4_Bergamo \
+ {.ExtFamily=0xa, .Family=0xF, .ExtModel=0xa, .Model=0x0}
typedef kernel_ulong_t (*PCI_CALLBACK)(struct pci_dev *);
@@ -3490,6 +3497,10 @@
CN_DHYANA_V2
};
+enum {
+ CN_BERGAMO
+};
+
static char *Arch_AMD_Zen[] = ZLIST(
[CN_SUMMIT_RIDGE] = "Zen/Summit Ridge",
[CN_WHITEHAVEN] = "Zen/Whitehaven",
@@ -3565,6 +3576,9 @@
static char *Arch_AMD_Zen4_PHX[] = ZLIST(
[CN_PHOENIX] = "Zen4/Phoenix Point"
);
+static char *Arch_AMD_Zen4_Bergamo[] = ZLIST(
+ [CN_BERGAMO] = "Zen4c/Bergamo"
+);
static char *Arch_AMD_Family_17h[] = ZLIST("AMD Zen");
@@ -4736,7 +4750,8 @@
},
/* [Zen/Snowy Owl] 8F_01h Stepping 2 */
{ /* AMD EPYC Embedded Processors */
- .Brand = ZLIST("AMD EPYC 3101"),
+ .Brand = ZLIST( "AMD EPYC Embedded 3101", \
+ "AMD EPYC 3101" ),
.Boost = {+8, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
@@ -4747,7 +4762,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD EPYC 3151"),
+ .Brand = ZLIST( "AMD EPYC Embedded 3151", \
+ "AMD EPYC 3151" ),
.Boost = {+2, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
@@ -4758,7 +4774,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD EPYC 3201"),
+ .Brand = ZLIST( "AMD EPYC Embedded 3201", \
+ "AMD EPYC 3201" ),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
@@ -4769,8 +4786,10 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST( "AMD EPYC 3251", \
- "AMD EPYC 3255" ),
+ .Brand = ZLIST( "AMD EPYC Embedded 3251", \
+ "AMD EPYC Embedded 3255", \
+ "AMD EPYC 3251", \
+ "AMD EPYC 3255" ),
.Boost = {+6, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
@@ -4781,7 +4800,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD EPYC 3351"),
+ .Brand = ZLIST( "AMD EPYC Embedded 3351", \
+ "AMD EPYC 3351" ),
.Boost = {+11, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
@@ -4792,7 +4812,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD EPYC 3451"),
+ .Brand = ZLIST( "AMD EPYC Embedded 3451", \
+ "AMD EPYC 3451" ),
.Boost = {+9, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_SNOWY_OWL,
@@ -4807,7 +4828,8 @@
static PROCESSOR_SPECIFIC AMD_Zen_APU_Specific[] = {
/* [Zen/Raven Ridge] 8F_11h Stepping 0 */
{
- .Brand = ZLIST( "AMD Athlon 240GE", \
+ .Brand = ZLIST( "AMD Athlon PRO 200GE", \
+ "AMD Athlon 240GE", \
"AMD Athlon 220GE", \
"AMD Athlon 200GE" ),
.Boost = {+0, 0},
@@ -4820,6 +4842,17 @@
.Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
},
{
+ .Brand = ZLIST("AMD Athlon PRO 200U"),
+ .Boost = {+9, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_RAVEN_RIDGE,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch = LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK
+ },
+ {
.Brand = ZLIST( "AMD Ryzen 3 PRO 2200GE", \
"AMD Ryzen 5 2600H" ),
.Boost = {+4, 0},
@@ -4955,9 +4988,32 @@
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
- {
/* Ryzen Embedded V1000 Processor Family */
- .Brand = ZLIST("AMD Ryzen Embedded V1605B"),
+ {
+ .Brand = ZLIST("AMD Ryzen Embedded V1202B"),
+ .Boost = {+9, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_GREAT_HORNED_OWL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
+ {
+ .Brand = ZLIST("AMD Ryzen Embedded V1500B"),
+ .Boost = {0, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_GREAT_HORNED_OWL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
+ {
+ .Brand = ZLIST( "AMD Ryzen Embedded V1404I", \
+ "AMD Ryzen Embedded V1605B" ),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_GREAT_HORNED_OWL,
@@ -4967,6 +5023,39 @@
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
+ {
+ .Brand = ZLIST("AMD Ryzen Embedded V1756B"),
+ .Boost = {+4, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_GREAT_HORNED_OWL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
+ {
+ .Brand = ZLIST("AMD Ryzen Embedded V1780B"),
+ .Boost = {+3, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_GREAT_HORNED_OWL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
+ {
+ .Brand = ZLIST("AMD Ryzen Embedded V1807B"),
+ .Boost = {+5, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_GREAT_HORNED_OWL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
+ },
{0}
};
static PROCESSOR_SPECIFIC AMD_ZenPlus_Specific[] = {
@@ -5306,6 +5395,7 @@
{
.Brand = ZLIST( "AMD Ryzen 3 3350U", \
"AMD Ryzen 3 3300U", \
+ "AMD Ryzen 3 PRO 3300U",\
"AMD Ryzen 5 3450U" ),
.Boost = {+14, 0},
.Param.Offset = {0, 0, 0},
@@ -5320,7 +5410,8 @@
.Brand = ZLIST( "AMD Ryzen 5 3580U", \
"AMD Ryzen 5 3550H", \
"AMD Ryzen 5 3500U", \
- "AMD Ryzen 5 3500C" ),
+ "AMD Ryzen 5 3500C",
+ "AMD Ryzen 5 PRO 3500U" ),
.Boost = {+16, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
@@ -5335,7 +5426,7 @@
"AMD Ryzen 7 3750H", \
"AMD Ryzen 7 3700U", \
"AMD Ryzen 7 3700C", \
- "AMD Ryzen 7 PRO 3700U" ),
+ "AMD Ryzen 7 PRO 3700U" ),
.Boost = {+17, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PICASSO,
@@ -5923,7 +6014,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD Ryzen 5 PRO 4650G"),
+ .Brand = ZLIST( "AMD Ryzen 5 PRO 4655G", \
+ "AMD Ryzen 5 PRO 4650G" ),
.Boost = {+5, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RENOIR,
@@ -6314,7 +6406,8 @@
static PROCESSOR_SPECIFIC AMD_Zen2_MDN_Specific[] = {
/* [Zen2/Mendocino] */
{
- .Brand = ZLIST("AMD Ryzen 5 7520U"),
+ .Brand = ZLIST( "AMD Ryzen 5 7520C", \
+ "AMD Ryzen 5 7520U" ),
.Boost = {+15, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MENDOCINO,
@@ -6326,7 +6419,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD Ryzen 3 7320U"),
+ .Brand = ZLIST( "AMD Ryzen 3 7320C", \
+ "AMD Ryzen 3 7320U" ),
.Boost = {+17, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MENDOCINO,
@@ -6338,7 +6432,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD Athlon Gold 7220U"),
+ .Brand = ZLIST( "AMD Athlon Gold 7220C", \
+ "AMD Athlon Gold 7220U" ),
.Boost = {+13, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MENDOCINO,
@@ -6350,7 +6445,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD Athlon Silver 7120U"),
+ .Brand = ZLIST( "AMD Athlon Silver 7120C", \
+ "AMD Athlon Silver 7120U" ),
.Boost = {+11, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_MENDOCINO,
@@ -6365,7 +6461,8 @@
};
static PROCESSOR_SPECIFIC AMD_Zen3_VMR_Specific[] = {
{
- .Brand = ZLIST("AMD Ryzen 7 5800X3D"),
+ .Brand = ZLIST( "AMD Ryzen 5 5600X3D", \
+ "AMD Ryzen 7 5800X3D" ),
.Boost = {+11, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_VERMEER,
@@ -7407,6 +7504,45 @@
};
static PROCESSOR_SPECIFIC AMD_Zen4_RPL_Specific[] = {
{
+ .Brand = ZLIST("AMD Ryzen 9 PRO 7945"),
+ .Boost = {+17, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_RAPHAEL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .HSMP_Capable = 1,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\
+ |LATCH_HSMP_CAPABLE
+ },
+ {
+ .Brand = ZLIST("AMD Ryzen 7 PRO 7745"),
+ .Boost = {+15, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_RAPHAEL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .HSMP_Capable = 1,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\
+ |LATCH_HSMP_CAPABLE
+ },
+ {
+ .Brand = ZLIST("AMD Ryzen 5 PRO 7645"),
+ .Boost = {+13, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_RAPHAEL,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .HSMP_Capable = 1,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\
+ |LATCH_HSMP_CAPABLE
+ },
+ {
.Brand = ZLIST("AMD Ryzen 9 7950X3D"),
.Boost = {+15, 0},
.Param.Offset = {0, 0, 0},
@@ -7604,7 +7740,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST( "AMD Ryzen 5 7640HS", \
+ .Brand = ZLIST( "AMD Ryzen 5 PRO 7640HS", \
+ "AMD Ryzen 5 7640HS", \
"AMD Ryzen 5 7640H" /* zh-cn */ ),
.Boost = {+7, 0},
.Param.Offset = {0, 0, 0},
@@ -7617,8 +7754,9 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST( "AMD Ryzen 7 7840U", \
- "AMD Ryzen Z1 Extreme" ),
+ .Brand = ZLIST( "AMD Ryzen 7 PRO 7840U", \
+ "AMD Ryzen 7 7840U", \
+ "AMD Ryzen Z1 Extreme" ),
.Boost = {+18, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PHOENIX,
@@ -7630,8 +7768,9 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST( "AMD Ryzen 5 7540U", \
- "AMD Ryzen Z1" ),
+ .Brand = ZLIST( "AMD Ryzen 5 PRO 7540U", \
+ "AMD Ryzen 5 7540U", \
+ "AMD Ryzen Z1" ),
.Boost = {+17, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PHOENIX,
@@ -7643,7 +7782,8 @@
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
{
- .Brand = ZLIST("AMD Ryzen 5 7640U"),
+ .Brand = ZLIST( "AMD Ryzen 5 PRO 7640U", \
+ "AMD Ryzen 5 7640U" ),
.Boost = {+14, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_PHOENIX,
@@ -7656,6 +7796,36 @@
},
{0}
};
+static PROCESSOR_SPECIFIC AMD_Zen4_Bergamo_Specific[] = {
+ {
+ .Brand = ZLIST( "AMD EPYC Embedded 9754S", \
+ "AMD EPYC Embedded 9754" ),
+ .Boost = {+9, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_BERGAMO,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .HSMP_Capable = 1,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\
+ |LATCH_HSMP_CAPABLE
+ },
+ {
+ .Brand = ZLIST("AMD EPYC Embedded 9734"),
+ .Boost = {+8, 0},
+ .Param.Offset = {0, 0, 0},
+ .CodeNameIdx = CN_BERGAMO,
+ .TgtRatioUnlocked = 1,
+ .ClkRatioUnlocked = 0b10,
+ .TurboUnlocked = 0,
+ .UncoreUnlocked = 0,
+ .HSMP_Capable = 1,
+ .Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\
+ |LATCH_HSMP_CAPABLE
+ },
+ {0}
+};
static PROCESSOR_SPECIFIC Misc_Specific_Processor[] = {
{0}
@@ -11034,5 +11204,29 @@
.Specific = AMD_Zen4_PHX_Specific,
.SystemDriver = AMD_Zen_Driver,
.Architecture = Arch_AMD_Zen4_PHX
+ },
+[AMD_Zen4_Bergamo] = { /*112*/
+ .Signature = _AMD_Zen4_Bergamo,
+ .Query = Query_AMD_F19h_PerCluster,
+ .Update = PerCore_AMD_Family_19h_Query,
+ .Start = Start_AMD_Family_19h,
+ .Stop = Stop_AMD_Family_19h,
+ .Exit = Exit_AMD_F19h,
+ .Timer = InitTimer_AMD_F19h_Zen3_MP,
+ .BaseClock = BaseClock_AMD_Family_19h,
+ .ClockMod = ClockMod_AMD_Zen,
+ .TurboClock = TurboClock_AMD_Zen,
+ .thermalFormula = THERMAL_FORMULA_AMD_ZEN4,
+ .voltageFormula = VOLTAGE_FORMULA_AMD_ZEN4,
+ .powerFormula = POWER_FORMULA_AMD_19h,
+ .PCI_ids = PCI_AMD_19h_ids,
+ .Uncore = {
+ .Start = Start_Uncore_AMD_Family_19h,
+ .Stop = Stop_Uncore_AMD_Family_19h,
+ .ClockMod = NULL
+ },
+ .Specific = AMD_Zen4_Bergamo_Specific,
+ .SystemDriver = AMD_Zen_Driver,
+ .Architecture = Arch_AMD_Zen4_Bergamo
}
};
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/CoreFreq-1.96.4/coretypes.h
new/CoreFreq-1.96.5/coretypes.h
--- old/CoreFreq-1.96.4/coretypes.h 2023-06-11 12:01:08.000000000 +0200
+++ new/CoreFreq-1.96.5/coretypes.h 2023-06-30 17:51:50.000000000 +0200
@@ -6,7 +6,7 @@
#define COREFREQ_MAJOR 1
#define COREFREQ_MINOR 96
-#define COREFREQ_REV 4
+#define COREFREQ_REV 5
#if !defined(CORE_COUNT)
#define CORE_COUNT 256
@@ -139,6 +139,7 @@
AMD_Zen4_Genoa,
AMD_Zen4_RPL,
AMD_Zen4_PHX,
+ AMD_Zen4_Bergamo,
ARCHITECTURES
};
