Script 'mail_helper' called by obssrc
Hello community,
here is the log from the commit of package opensbi for openSUSE:Factory checked
in at 2023-07-24 18:24:47
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/opensbi (Old)
and /work/SRC/openSUSE:Factory/.opensbi.new.1467 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "opensbi"
Mon Jul 24 18:24:47 2023 rev:11 rq:1099548 version:1.3.1
Changes:
--------
--- /work/SRC/openSUSE:Factory/opensbi/opensbi.changes 2023-06-26
18:17:14.174774874 +0200
+++ /work/SRC/openSUSE:Factory/.opensbi.new.1467/opensbi.changes
2023-07-24 18:24:50.477753571 +0200
@@ -1,0 +2,8 @@
+Wed Jul 19 15:22:59 UTC 2023 - Andreas Schwab <sch...@suse.de>
+
+- Update to opensbi 1.3.1
+ * ACLINT driver fix for disabled CPUs
+ * SBI PMU fix for out-of-bound access
+ * Designware GPIO driver
+
+-------------------------------------------------------------------
Old:
----
opensbi-1.3.tar.gz
New:
----
opensbi-1.3.1.tar.gz
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ opensbi.spec ++++++
--- /var/tmp/diff_new_pack.DYkyf3/_old 2023-07-24 18:24:51.585760080 +0200
+++ /var/tmp/diff_new_pack.DYkyf3/_new 2023-07-24 18:24:51.589760103 +0200
@@ -23,7 +23,7 @@
%else
Name: opensbi-%{target}
%endif
-Version: 1.3
+Version: 1.3.1
Release: 0
Summary: RISC-V Open Source Supervisor Binary Interface
License: BSD-2-Clause
++++++ opensbi-1.3.tar.gz -> opensbi-1.3.1.tar.gz ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/sbi/sbi_ecall_dbcn.c
new/opensbi-1.3.1/lib/sbi/sbi_ecall_dbcn.c
--- old/opensbi-1.3/lib/sbi/sbi_ecall_dbcn.c 2023-06-23 07:31:49.000000000
+0200
+++ new/opensbi-1.3.1/lib/sbi/sbi_ecall_dbcn.c 2023-07-19 08:21:59.000000000
+0200
@@ -34,10 +34,10 @@
* Based on above, we simply fail if the upper 32bits of
* the physical address (i.e. a2 register) is non-zero on
* RV32.
- *
- * Analogously, we fail if the upper 64bit of the
- * physical address (i.e. a2 register) is non-zero on
- * RV64.
+ *
+ * Analogously, we fail if the upper 64bit of the
+ * physical address (i.e. a2 register) is non-zero on
+ * RV64.
*/
if (regs->a2)
return SBI_ERR_FAILED;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/sbi/sbi_pmu.c
new/opensbi-1.3.1/lib/sbi/sbi_pmu.c
--- old/opensbi-1.3/lib/sbi/sbi_pmu.c 2023-06-23 07:31:49.000000000 +0200
+++ new/opensbi-1.3.1/lib/sbi/sbi_pmu.c 2023-07-19 08:21:59.000000000 +0200
@@ -933,6 +933,8 @@
/* mcycle & minstret is available always */
num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 3;
+ if (num_hw_ctrs > SBI_PMU_HW_CTR_MAX)
+ return SBI_EINVAL;
total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/utils/gpio/Kconfig
new/opensbi-1.3.1/lib/utils/gpio/Kconfig
--- old/opensbi-1.3/lib/utils/gpio/Kconfig 2023-06-23 07:31:49.000000000
+0200
+++ new/opensbi-1.3.1/lib/utils/gpio/Kconfig 2023-07-19 08:21:59.000000000
+0200
@@ -10,6 +10,10 @@
if FDT_GPIO
+config FDT_GPIO_DESIGNWARE
+ bool "DesignWare GPIO driver"
+ default n
+
config FDT_GPIO_SIFIVE
bool "SiFive GPIO FDT driver"
default n
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/utils/gpio/fdt_gpio_designware.c
new/opensbi-1.3.1/lib/utils/gpio/fdt_gpio_designware.c
--- old/opensbi-1.3/lib/utils/gpio/fdt_gpio_designware.c 1970-01-01
01:00:00.000000000 +0100
+++ new/opensbi-1.3.1/lib/utils/gpio/fdt_gpio_designware.c 2023-07-19
08:21:59.000000000 +0200
@@ -0,0 +1,140 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 SiFive
+ *
+ * GPIO driver for Synopsys DesignWare APB GPIO
+ *
+ * Authors:
+ * Ben Dooks <ben.do...@sifive.com>
+ */
+
+#include <libfdt.h>
+
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_error.h>
+
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/gpio/fdt_gpio.h>
+
+#define DW_GPIO_CHIP_MAX 4 /* need 1 per bank in use */
+#define DW_GPIO_PINS_MAX 32
+
+#define DW_GPIO_DDR 0x4
+#define DW_GPIO_DR 0x0
+#define DW_GPIO_BIT(_b) (1UL << (_b))
+
+struct dw_gpio_chip {
+ void *dr;
+ void *ext;
+ struct gpio_chip chip;
+};
+
+extern struct fdt_gpio fdt_gpio_designware;
+
+static unsigned int dw_gpio_chip_count;
+static struct dw_gpio_chip dw_gpio_chip_array[DW_GPIO_CHIP_MAX];
+
+#define pin_to_chip(__p) container_of((__p)->chip, struct dw_gpio_chip, chip);
+
+static int dw_gpio_direction_output(struct gpio_pin *gp, int value)
+{
+ struct dw_gpio_chip *chip = pin_to_chip(gp);
+ unsigned long v;
+
+ v = readl(chip->dr + DW_GPIO_DR);
+ if (!value)
+ v &= ~DW_GPIO_BIT(gp->offset);
+ else
+ v |= DW_GPIO_BIT(gp->offset);
+ writel(v, chip->dr + DW_GPIO_DR);
+
+ /* the DR is output only so we can set it then the DDR to set
+ * the data direction, to avoid glitches.
+ */
+ v = readl(chip->dr + DW_GPIO_DDR);
+ v |= DW_GPIO_BIT(gp->offset);
+ writel(v, chip->dr + DW_GPIO_DDR);
+
+ return 0;
+}
+
+static void dw_gpio_set(struct gpio_pin *gp, int value)
+{
+ struct dw_gpio_chip *chip = pin_to_chip(gp);
+ unsigned long v;
+
+ v = readl(chip->dr + DW_GPIO_DR);
+ if (!value)
+ v &= ~DW_GPIO_BIT(gp->offset);
+ else
+ v |= DW_GPIO_BIT(gp->offset);
+ writel(v, chip->dr + DW_GPIO_DR);
+}
+
+/* notes:
+ * each sub node is a bank and has ngpios or snpns,nr-gpios and a reg property
+ * with the compatible `snps,dw-apb-gpio-port`.
+ * bank A is the only one with irq support but we're not using it here
+*/
+
+static int dw_gpio_init_bank(void *fdt, int nodeoff, u32 phandle,
+ const struct fdt_match *match)
+{
+ struct dw_gpio_chip *chip;
+ const fdt32_t *val;
+ uint64_t addr;
+ int rc, poff, nr_pins, bank, len;
+
+ if (dw_gpio_chip_count >= DW_GPIO_CHIP_MAX)
+ return SBI_ENOSPC;
+
+ /* need to get parent for the address property */
+ poff = fdt_parent_offset(fdt, nodeoff);
+ if (poff < 0)
+ return SBI_EINVAL;
+
+ rc = fdt_get_node_addr_size(fdt, poff, 0, &addr, NULL);
+ if (rc)
+ return rc;
+
+ val = fdt_getprop(fdt, nodeoff, "reg", &len);
+ if (!val || len <= 0)
+ return SBI_EINVAL;
+ bank = fdt32_to_cpu(*val);
+
+ val = fdt_getprop(fdt, nodeoff, "snps,nr-gpios", &len);
+ if (!val)
+ val = fdt_getprop(fdt, nodeoff, "ngpios", &len);
+ if (!val || len <= 0)
+ return SBI_EINVAL;
+ nr_pins = fdt32_to_cpu(*val);
+
+ chip = &dw_gpio_chip_array[dw_gpio_chip_count];
+
+ chip->dr = (void *)(uintptr_t)addr + (bank * 0xc);
+ chip->ext = (void *)(uintptr_t)addr + (bank * 4) + 0x50;
+ chip->chip.driver = &fdt_gpio_designware;
+ chip->chip.id = phandle;
+ chip->chip.ngpio = nr_pins;
+ chip->chip.set = dw_gpio_set;
+ chip->chip.direction_output = dw_gpio_direction_output;
+ rc = gpio_chip_add(&chip->chip);
+ if (rc)
+ return rc;
+
+ dw_gpio_chip_count++;
+ return 0;
+}
+
+/* since we're only probed when used, match on port not main controller node */
+static const struct fdt_match dw_gpio_match[] = {
+ { .compatible = "snps,dw-apb-gpio-port" },
+ { },
+};
+
+struct fdt_gpio fdt_gpio_designware = {
+ .match_table = dw_gpio_match,
+ .xlate = fdt_gpio_simple_xlate,
+ .init = dw_gpio_init_bank,
+};
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/utils/gpio/objects.mk
new/opensbi-1.3.1/lib/utils/gpio/objects.mk
--- old/opensbi-1.3/lib/utils/gpio/objects.mk 2023-06-23 07:31:49.000000000
+0200
+++ new/opensbi-1.3.1/lib/utils/gpio/objects.mk 2023-07-19 08:21:59.000000000
+0200
@@ -10,6 +10,9 @@
libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio.o
libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
+carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_DESIGNWARE) += fdt_gpio_designware
+libsbiutils-objs-$(CONFIG_FDT_GPIO_DESIGNWARE) += gpio/fdt_gpio_designware.o
+
carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/utils/ipi/aclint_mswi.c
new/opensbi-1.3.1/lib/utils/ipi/aclint_mswi.c
--- old/opensbi-1.3/lib/utils/ipi/aclint_mswi.c 2023-06-23 07:31:49.000000000
+0200
+++ new/opensbi-1.3.1/lib/utils/ipi/aclint_mswi.c 2023-07-19
08:21:59.000000000 +0200
@@ -101,8 +101,13 @@
/* Update MSWI pointer in scratch space */
for (i = 0; i < mswi->hart_count; i++) {
scratch = sbi_hartid_to_scratch(mswi->first_hartid + i);
+ /*
+ * We don't need to fail if scratch pointer is not available
+ * because we might be dealing with hartid of a HART disabled
+ * in the device tree.
+ */
if (!scratch)
- return SBI_ENOENT;
+ continue;
mswi_set_hart_data_ptr(scratch, mswi);
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/lib/utils/timer/aclint_mtimer.c
new/opensbi-1.3.1/lib/utils/timer/aclint_mtimer.c
--- old/opensbi-1.3/lib/utils/timer/aclint_mtimer.c 2023-06-23
07:31:49.000000000 +0200
+++ new/opensbi-1.3.1/lib/utils/timer/aclint_mtimer.c 2023-07-19
08:21:59.000000000 +0200
@@ -219,8 +219,13 @@
/* Update MTIMER pointer in scratch space */
for (i = 0; i < mt->hart_count; i++) {
scratch = sbi_hartid_to_scratch(mt->first_hartid + i);
+ /*
+ * We don't need to fail if scratch pointer is not available
+ * because we might be dealing with hartid of a HART disabled
+ * in the device tree.
+ */
if (!scratch)
- return SBI_ENOENT;
+ continue;
mtimer_set_hart_data_ptr(scratch, mt);
}
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/opensbi-1.3/platform/generic/configs/defconfig
new/opensbi-1.3.1/platform/generic/configs/defconfig
--- old/opensbi-1.3/platform/generic/configs/defconfig 2023-06-23
07:31:49.000000000 +0200
+++ new/opensbi-1.3.1/platform/generic/configs/defconfig 2023-07-19
08:21:59.000000000 +0200
@@ -5,6 +5,7 @@
CONFIG_PLATFORM_SIFIVE_FU740=y
CONFIG_PLATFORM_STARFIVE_JH7110=y
CONFIG_FDT_GPIO=y
+CONFIG_FDT_GPIO_DESIGNWARE=y
CONFIG_FDT_GPIO_SIFIVE=y
CONFIG_FDT_GPIO_STARFIVE=y
CONFIG_FDT_I2C=y
