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Hello community,
here is the log from the commit of package intel-graphics-compiler for
openSUSE:Factory checked in at 2024-02-01 18:04:44
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/intel-graphics-compiler (Old)
and /work/SRC/openSUSE:Factory/.intel-graphics-compiler.new.1815 (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "intel-graphics-compiler"
Thu Feb 1 18:04:44 2024 rev:9 rq:1142915 version:1.0.15610.11
Changes:
--------
---
/work/SRC/openSUSE:Factory/intel-graphics-compiler/intel-graphics-compiler.changes
2024-01-04 16:01:26.157370555 +0100
+++
/work/SRC/openSUSE:Factory/.intel-graphics-compiler.new.1815/intel-graphics-compiler.changes
2024-02-01 18:05:12.602704414 +0100
@@ -1,0 +2,16 @@
+Tue Jan 30 10:14:46 UTC 2024 - Patrik Jakobsson <patrik.jakobs...@suse.com>
+
+- Only update LongConstantCompositeINTEL on suse_version > 1506
+
+-------------------------------------------------------------------
+Tue Jan 30 07:47:01 UTC 2024 - Patrik Jakobsson <patrik.jakobs...@suse.com>
+
+- Update to version 1.0.15610.11
+- Update spirv_llvm_translator_commit to
493353d7fdc655f9f31abc874dd0adef7dd241c1
+- Update vc_intrinsics_commit to v0.14.0
+- 0001-Fix-PromotePredicate-to-keep-sequence-of-instruction.patch
+ * Now included in current version
+- 0001-Backport-to-17-Update-LongConstantCompositeINTEL-to-.patch
+ * Adapt to name change made in spirv-headers
+
+-------------------------------------------------------------------
Old:
----
0001-Fix-PromotePredicate-to-keep-sequence-of-instruction.patch
igc-1.0.15136.4.tar.gz
New:
----
0001-Backport-to-17-Update-LongConstantCompositeINTEL-to-.patch
igc-1.0.15610.11.tar.gz
BETA DEBUG BEGIN:
Old:- Update vc_intrinsics_commit to v0.14.0
- 0001-Fix-PromotePredicate-to-keep-sequence-of-instruction.patch
* Now included in current version
BETA DEBUG END:
BETA DEBUG BEGIN:
New: * Now included in current version
- 0001-Backport-to-17-Update-LongConstantCompositeINTEL-to-.patch
* Adapt to name change made in spirv-headers
BETA DEBUG END:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ intel-graphics-compiler.spec ++++++
--- /var/tmp/diff_new_pack.7Fu3oF/_old 2024-02-01 18:05:13.674743202 +0100
+++ /var/tmp/diff_new_pack.7Fu3oF/_new 2024-02-01 18:05:13.678743346 +0100
@@ -18,10 +18,10 @@
%global llvm_commit llvmorg-14.0.5
%global opencl_clang_commit cf95b338d14685e4f3402ab1828bef31d48f1fd6
-%global spirv_llvm_translator_commit 43baf90f96fb9df607595b63858fd9e85fbb2604
-%global vc_intrinsics_commit v0.13.0
+%global spirv_llvm_translator_commit 493353d7fdc655f9f31abc874dd0adef7dd241c1
+%global vc_intrinsics_commit v0.14.0
Name: intel-graphics-compiler
-Version: 1.0.15136.4
+Version: 1.0.15610.11
Release: 1%{?dist}
Summary: Intel Graphics Compiler for OpenCL
License: MIT
@@ -33,7 +33,7 @@
Source3:
https://github.com/llvm/llvm-project/archive/%{llvm_commit}/llvm-project.tar.gz
Source4:
https://github.com/intel/vc-intrinsics/archive/%{vc_intrinsics_commit}/vc-intrinsics.zip
Patch0: 0001-Use-patch-instead-of-git-to-apply-opencl-clang-patch.patch
-Patch1: 0001-Fix-PromotePredicate-to-keep-sequence-of-instruction.patch
+Patch1: 0001-Backport-to-17-Update-LongConstantCompositeINTEL-to-.patch
BuildRequires: bison
BuildRequires: cmake
BuildRequires: flex
@@ -125,12 +125,16 @@
%patch0 -p1
popd
tar -xzf %{_sourcedir}/spirv-llvm-translator.tar.gz -C llvm-spirv
--strip-components=1
+pushd llvm-spirv
+%if 0%{?suse_version} > 1506
+%patch1 -p1
+%endif
+popd
popd
mkdir igc
tar -xzf %{_sourcedir}/igc-%{version}.tar.gz -C igc --strip-components=1
pushd igc
-%patch1 -p1
popd
%build
++++++ 0001-Backport-to-17-Update-LongConstantCompositeINTEL-to-.patch ++++++
>From de5778bd04d0cd830cd56f08741c42dc7126b28c Mon Sep 17 00:00:00 2001
From: Dmitry Sidorov <dmitry.sido...@intel.com>
Date: Tue, 23 Jan 2024 12:41:32 +0100
Subject: [PATCH] [Backport to 17] Update LongConstantCompositeINTEL to
LongCompositesINTEL capability after Headers change (#2258) (#2308)
* Bump SPIRV-Headers to 1c6bb2743599e6eb6f37b2969acc0aef812e32e3
* replace internal SPV_INTEL_long_composites ext with the published
SPV_INTEL_long_composites
* don't rename extension for now
This closes: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/2261
Co-authored-by: Viktoria Maximova <viktoria.maksim...@intel.com>
Co-authored-by: Wlodarczyk, Bertrand <bertrand.wlodarc...@intel.com>
---
include/LLVMSPIRVExtensions.inc | 4 +++-
lib/SPIRV/libSPIRV/SPIRVEntry.h | 2 +-
lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 2 +-
spirv-headers-tag.conf | 2 +-
test/SpecConstants/long-spec-const-composite.ll | 2 +-
test/long-constant-array.ll | 2 +-
test/long-type-struct.ll | 2 +-
7 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc
index 7757b624..c766f807 100644
--- a/include/LLVMSPIRVExtensions.inc
+++ b/include/LLVMSPIRVExtensions.inc
@@ -41,7 +41,9 @@ EXT(SPV_INTEL_variable_length_array)
EXT(SPV_INTEL_fp_fast_math_mode)
EXT(SPV_INTEL_fpga_cluster_attributes)
EXT(SPV_INTEL_loop_fuse)
-EXT(SPV_INTEL_long_constant_composite)
+EXT(SPV_INTEL_long_composites)
+EXT(SPV_INTEL_long_constant_composite) // TODO: rename to
+ // SPV_INTEL_long_composites later
EXT(SPV_INTEL_optnone)
EXT(SPV_INTEL_fpga_dsp_control)
EXT(SPV_INTEL_memory_access_aliasing)
diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.h b/lib/SPIRV/libSPIRV/SPIRVEntry.h
index f497c95d..0e0bd3ce 100644
--- a/lib/SPIRV/libSPIRV/SPIRVEntry.h
+++ b/lib/SPIRV/libSPIRV/SPIRVEntry.h
@@ -905,7 +905,7 @@ public:
}
SPIRVCapVec getRequiredCapability() const override {
- return getVec(CapabilityLongConstantCompositeINTEL);
+ return getVec(CapabilityLongCompositesINTEL);
}
llvm::Optional<ExtensionID> getRequiredExtension() const override {
diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
index ab5865a7..a8e06260 100644
--- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
+++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -594,7 +594,7 @@ template <> inline void SPIRVMap<Capability,
std::string>::init() {
add(CapabilityGroupNonUniformRotateKHR, "GroupNonUniformRotateKHR");
add(CapabilityAtomicFloat32AddEXT, "AtomicFloat32AddEXT");
add(CapabilityAtomicFloat64AddEXT, "AtomicFloat64AddEXT");
- add(CapabilityLongConstantCompositeINTEL, "LongConstantCompositeINTEL");
+ add(CapabilityLongCompositesINTEL, "LongCompositesINTEL");
add(CapabilityOptNoneINTEL, "OptNoneINTEL");
add(CapabilityAtomicFloat16AddEXT, "AtomicFloat16AddEXT");
add(CapabilityDebugInfoModuleINTEL, "DebugInfoModuleINTEL");
diff --git a/spirv-headers-tag.conf b/spirv-headers-tag.conf
index 9a532ba5..7fae55f3 100644
--- a/spirv-headers-tag.conf
+++ b/spirv-headers-tag.conf
@@ -1 +1 @@
-9b527c0fb60124936d0906d44803bec51a0200fb
+1c6bb2743599e6eb6f37b2969acc0aef812e32e3
diff --git a/test/SpecConstants/long-spec-const-composite.ll
b/test/SpecConstants/long-spec-const-composite.ll
index 974a0776..4510a1e6 100644
--- a/test/SpecConstants/long-spec-const-composite.ll
+++ b/test/SpecConstants/long-spec-const-composite.ll
@@ -11,7 +11,7 @@
target datalayout =
"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
target triple = "spir64-unknown-unknown"
-; CHECK-SPIRV: Capability LongConstantCompositeINTEL
+; CHECK-SPIRV: Capability LongCompositesINTEL
; CHECK-SPIRV: Extension "SPV_INTEL_long_constant_composite"
; CHECK-SPIRV-DAG: Decorate [[First:[0-9]+]] SpecId 0
; CHECK-SPIRV-DAG: Decorate [[Last:[0-9]+]] SpecId 65548
diff --git a/test/long-constant-array.ll b/test/long-constant-array.ll
index 03b33771..d0b4c3b3 100644
--- a/test/long-constant-array.ll
+++ b/test/long-constant-array.ll
@@ -9,7 +9,7 @@
; TODO: run validator once it supports the extension
; RUNx: spirv-val %t.spv
-; CHECK-SPIRV: Capability LongConstantCompositeINTEL
+; CHECK-SPIRV: Capability LongCompositesINTEL
; CHECK-SPIRV: Extension "SPV_INTEL_long_constant_composite"
; CHECK-SPIRV: TypeInt [[TInt:[0-9]+]] 8
; CHECK-SPIRV: Constant {{[0-9]+}} [[ArrSize:[0-9]+]] 78000
diff --git a/test/long-type-struct.ll b/test/long-type-struct.ll
index b9478f0f..a1cdfc6b 100644
--- a/test/long-type-struct.ll
+++ b/test/long-type-struct.ll
@@ -10,7 +10,7 @@
; RUN: not llvm-spirv %t.bc -o %t.spv 2>&1 | FileCheck %s
--check-prefix=CHECK-ERROR
-; CHECK-SPIRV: Capability LongConstantCompositeINTEL
+; CHECK-SPIRV: Capability LongCompositesINTEL
; CHECK-SPIRV: Extension "SPV_INTEL_long_constant_composite"
; CHECK-SPIRV: TypeForwardPointer [[TFwdPtr:[0-9]+]]
; CHECK-SPIRV: TypeInt [[TInt:[0-9]+]]
--
2.43.0
++++++ igc-1.0.15136.4.tar.gz -> igc-1.0.15610.11.tar.gz ++++++
/work/SRC/openSUSE:Factory/intel-graphics-compiler/igc-1.0.15136.4.tar.gz
/work/SRC/openSUSE:Factory/.intel-graphics-compiler.new.1815/igc-1.0.15610.11.tar.gz
differ: char 23, line 1
++++++ spirv-llvm-translator.tar.gz ++++++
++++ 2833 lines of diff (skipped)
++++++ vc-intrinsics.zip ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
new/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h
2023-10-25 00:27:31.000000000 +0200
@@ -17,7 +17,6 @@
#ifndef GENX_INTRINSIC_INTERFACE_H
#define GENX_INTRINSIC_INTERFACE_H
-#include "llvm/ADT/None.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/include/llvmVCWrapper/ADT/Optional.h
new/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvmVCWrapper/ADT/Optional.h
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/include/llvmVCWrapper/ADT/Optional.h
1970-01-01 01:00:00.000000000 +0100
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvmVCWrapper/ADT/Optional.h
2023-10-25 00:27:31.000000000 +0200
@@ -0,0 +1,28 @@
+/*========================== begin_copyright_notice
============================
+
+Copyright (C) 2020-2022 Intel Corporation
+
+SPDX-License-Identifier: MIT
+
+============================= end_copyright_notice
===========================*/
+
+#ifndef VCINTR_ADT_OPTIONAL_H
+#define VCINTR_ADT_OPTIONAL_H
+
+#if VC_INTR_LLVM_VERSION_MAJOR < 16
+#include <llvm/ADT/Optional.h>
+
+namespace VCINTR {
+
+template <class T> using Optional = llvm::Optional<T>;
+}
+#else
+#include <optional>
+
+namespace VCINTR {
+template <class T> using Optional = std::optional<T>;
+}
+
+#endif
+
+#endif
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h
new/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/include/llvmVCWrapper/IR/Instructions.h
2023-10-25 00:27:31.000000000 +0200
@@ -10,8 +10,8 @@
#define VCINTR_IR_INSTRUCTIONS_H
#include <algorithm>
-#include <llvm/ADT/Optional.h>
#include <llvm/IR/Instructions.h>
+#include <llvmVCWrapper/ADT/Optional.h>
namespace VCINTR {
namespace ShuffleVectorInst {
@@ -44,7 +44,7 @@
} // namespace ShuffleVectorInst
template <class ArgKind>
-inline ArgKind &getValue(llvm::Optional<ArgKind> &opt) {
+inline ArgKind &getValue(VCINTR::Optional<ArgKind> &opt) {
#if VC_INTR_LLVM_VERSION_MAJOR < 15
return opt.getValue();
#else
@@ -53,7 +53,7 @@
}
template <class ArgKind>
-inline const ArgKind &getValue(const llvm::Optional<ArgKind> &opt) {
+inline const ArgKind &getValue(const VCINTR::Optional<ArgKind> &opt) {
#if VC_INTR_LLVM_VERSION_MAJOR < 15
return opt.getValue();
#else
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXIntrinsics.cpp
2023-10-25 00:27:31.000000000 +0200
@@ -97,8 +97,10 @@
IIT_VARARG = 29,
IIT_HALF_VEC_ARG = 30,
IIT_SAME_VEC_WIDTH_ARG = 31,
+#if VC_INTR_LLVM_VERSION_MAJOR < 18
IIT_PTR_TO_ARG = 32,
IIT_PTR_TO_ELT = 33,
+#endif
IIT_VEC_OF_ANYPTRS_TO_ELT = 34,
IIT_I128 = 35,
IIT_V512 = 36,
@@ -109,6 +111,15 @@
IIT_F128 = 41
};
+static Intrinsic::IITDescriptor getVector(unsigned Width) {
+ using namespace Intrinsic;
+#if VC_INTR_LLVM_VERSION_MAJOR >= 11
+ return IITDescriptor::getVector(Width, false);
+#else
+ return IITDescriptor::get(IITDescriptor::Vector, Width);
+#endif
+}
+
static void
DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
SmallVectorImpl<Intrinsic::IITDescriptor> &OutputTable) {
@@ -164,39 +175,39 @@
OutputTable.push_back(IITDescriptor::get(IITDescriptor::Integer, 128));
return;
case IIT_V1:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 1));
+ OutputTable.push_back(getVector(1));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V2:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 2));
+ OutputTable.push_back(getVector(2));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V4:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 4));
+ OutputTable.push_back(getVector(4));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V8:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 8));
+ OutputTable.push_back(getVector(8));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V16:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 16));
+ OutputTable.push_back(getVector(16));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V32:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 32));
+ OutputTable.push_back(getVector(32));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V64:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 64));
+ OutputTable.push_back(getVector(64));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V512:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 512));
+ OutputTable.push_back(getVector(512));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_V1024:
- OutputTable.push_back(IITDescriptor::get(IITDescriptor::Vector, 1024));
+ OutputTable.push_back(getVector(1024));
DecodeIITType(NextElt, Infos, OutputTable);
return;
case IIT_PTR:
@@ -238,6 +249,7 @@
ArgInfo));
return;
}
+#if VC_INTR_LLVM_VERSION_MAJOR < 17
case IIT_PTR_TO_ARG: {
unsigned ArgInfo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
OutputTable.push_back(IITDescriptor::get(IITDescriptor::PtrToArgument,
@@ -249,6 +261,7 @@
OutputTable.push_back(IITDescriptor::get(IITDescriptor::PtrToElt,
ArgInfo));
return;
}
+#endif
case IIT_VEC_OF_ANYPTRS_TO_ELT: {
unsigned short ArgNo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
unsigned short RefNo = (NextElt == Infos.size() ? 0 : Infos[NextElt++]);
@@ -337,6 +350,7 @@
}
llvm_unreachable("unhandled");
}
+#if VC_INTR_LLVM_VERSION_MAJOR < 17
case IITDescriptor::PtrToArgument: {
Type *Ty = Tys[D.getArgumentNumber()];
return PointerType::getUnqual(Ty);
@@ -349,6 +363,7 @@
Type *EltTy = cast<VectorType>(VTy)->getElementType();
return PointerType::getUnqual(EltTy);
}
+#endif
case IITDescriptor::VecOfAnyPtrsToElt:
// Return the overloaded type (which determines the pointers address space)
return Tys[D.getOverloadArgNumber()];
@@ -437,10 +452,9 @@
Result += "vararg";
// Ensure nested function types are distinguishable.
Result += "f";
- } else if (isa<VectorType>(Ty)) {
- Result += "v" +
- utostr(VCINTR::VectorType::getNumElements(cast<VectorType>(Ty)))
+
- getMangledTypeStr(cast<VectorType>(Ty)->getElementType());
+ } else if (auto *VTy = dyn_cast<VectorType>(Ty)) {
+ Result += "v" + utostr(VCINTR::VectorType::getNumElements(VTy)) +
+ getMangledTypeStr(VTy->getElementType());
#if VC_INTR_LLVM_VERSION_MAJOR >= 16
} else if (auto *TargetTy = dyn_cast<TargetExtType>(Ty)) {
Result += "t_" + TargetTy->getName().str();
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVReaderAdaptor.cpp
2023-10-25 00:27:31.000000000 +0200
@@ -201,7 +201,7 @@
return {ResultType, AccessTy};
}
-static Optional<SPIRVArgDesc> parseIntelType(StringRef TyName) {
+static VCINTR::Optional<SPIRVArgDesc> parseIntelType(StringRef TyName) {
if (!TyName.consume_front(IntelTypes::TypePrefix))
return {};
@@ -213,7 +213,7 @@
return SPIRVArgDesc{MainType, AccType};
}
-static Optional<SPIRVArgDesc> parseOCLType(StringRef TyName) {
+static VCINTR::Optional<SPIRVArgDesc> parseOCLType(StringRef TyName) {
if (!TyName.consume_front(OCLTypes::TypePrefix))
return {};
@@ -227,7 +227,7 @@
return parseImageType(TyName);
}
-static Optional<SPIRVArgDesc> parseSPIRVIRType(StringRef TyName) {
+static VCINTR::Optional<SPIRVArgDesc> parseSPIRVIRType(StringRef TyName) {
if (!TyName.consume_front(SPIRVIRTypes::TypePrefix))
return {};
@@ -248,7 +248,7 @@
// SPVImageTy -> "Image." _..._{Dim}_..._{Arrayed}_..._{Acc}
// Dim, Arrayed, Acc - literal operands matching OpTypeImage operands in SPIRV
// Assume that "opencl." "spirv." and "intel.buffer" types are well-formed.
-static Optional<SPIRVArgDesc> parseOpaqueType(StringRef TyName) {
+static VCINTR::Optional<SPIRVArgDesc> parseOpaqueType(StringRef TyName) {
if (auto MaybeIntelTy = parseIntelType(TyName))
return VCINTR::getValue(MaybeIntelTy);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSPIRVWriterAdaptor.cpp
2023-10-25 00:27:31.000000000 +0200
@@ -356,11 +356,11 @@
Desc.split(Tokens, /*Separator=*/' ', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
// Scan tokens until end or required info is found.
- Optional<AccessType> AccTy;
- Optional<SPIRVType> Ty;
+ VCINTR::Optional<AccessType> AccTy;
+ VCINTR::Optional<SPIRVType> Ty;
for (StringRef Tok : Tokens) {
if (!Ty) {
- Ty = StringSwitch<Optional<SPIRVType>>(Tok)
+ Ty = StringSwitch<VCINTR::Optional<SPIRVType>>(Tok)
.Case(ArgDesc::Buffer, SPIRVType::Buffer)
.Case(ArgDesc::Image1d, SPIRVType::Image1d)
.Case(ArgDesc::Image1dArray, SPIRVType::Image1dArray)
@@ -375,7 +375,7 @@
}
if (!AccTy) {
- AccTy = StringSwitch<Optional<AccessType>>(Tok)
+ AccTy = StringSwitch<VCINTR::Optional<AccessType>>(Tok)
.Case(ArgDesc::ReadOnly, AccessType::ReadOnly)
.Case(ArgDesc::WriteOnly, AccessType::WriteOnly)
.Case(ArgDesc::ReadWrite, AccessType::ReadWrite)
@@ -466,7 +466,7 @@
// value can be out of listed in ArgKind enum.
// Such values are not processed later.
// Return None if there is no such attribute.
-static Optional<ArgKind> extractArgumentKind(const Argument &Arg) {
+static VCINTR::Optional<ArgKind> extractArgumentKind(const Argument &Arg) {
const Function *F = Arg.getParent();
const AttributeList Attrs = F->getAttributes();
if (!Attrs.hasParamAttr(Arg.getArgNo(), VCFunctionMD::VCArgumentKind))
@@ -539,7 +539,7 @@
#endif
Instruction *InsPt = &NewF->getEntryBlock().front();
- for (auto ArgPair : llvm::zip(F.args(), NewF->args()))
+ for (auto &&ArgPair : llvm::zip(F.args(), NewF->args()))
rewriteArgumentUses(InsPt, std::get<0>(ArgPair), std::get<1>(ArgPair));
F.eraseFromParent();
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSimdCFLowering.cpp
2023-10-25 00:27:31.000000000 +0200
@@ -1707,7 +1707,7 @@
}
Value *Cond = Br->getCondition();
Use *CondUse = getSimdConditionUse(Cond);
- DebugLoc DL = Br->getDebugLoc();
+ const auto &DL = Br->getDebugLoc();
if (CondUse)
Cond = *CondUse;
else {
@@ -1863,7 +1863,7 @@
MaskBegins.push_back(CIB);
MaskEnds.push_back(CIE);
// put in genx_simdcf_savemask and genx_simdcf_remask
- auto DL = CIB->getDebugLoc();
+ const auto &DL = CIB->getDebugLoc();
Instruction *OldEM =
new
LoadInst(VCINTR::Type::getNonOpaquePtrEltTy(EMVar->getType()), EMVar,
EMVar->getName(), false /* isVolatile */, CIB);
@@ -1887,19 +1887,19 @@
(new StoreInst(Unmask, EMVar, false /* isVolatile */, CIB))
->setDebugLoc(DL);
// put in genx_simdcf_remask
- DL = CIE->getDebugLoc();
+ const auto &DLCIE = CIE->getDebugLoc();
OldEM = new
LoadInst(VCINTR::Type::getNonOpaquePtrEltTy(EMVar->getType()), EMVar,
EMVar->getName(), false /* isVolatile */, CIE);
- OldEM->setDebugLoc(DL);
+ OldEM->setDebugLoc(DLCIE);
Type *Ty2s[] = {OldEM->getType()};
auto RemaskFunc = GenXIntrinsic::getGenXDeclaration(
BB->getParent()->getParent(),
GenXIntrinsic::genx_simdcf_remask, Ty2s);
Value *Arg2s[] = {OldEM, LoadV};
auto Remask = CallInst::Create(RemaskFunc, Arg2s, "remask", CIE);
- Remask->setDebugLoc(DL);
+ Remask->setDebugLoc(DLCIE);
(new StoreInst(Remask, EMVar, false /* isVolatile */, CIE))
- ->setDebugLoc(DL);
+ ->setDebugLoc(DLCIE);
updateFnAttr(SavemaskFunc);
updateFnAttr(UnmaskFunc);
updateFnAttr(RemaskFunc);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/lib/GenXIntrinsics/GenXSingleElementVectorUtil.cpp
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
/*========================== begin_copyright_notice
============================
-Copyright (C) 2020-2021 Intel Corporation
+Copyright (C) 2020-2023 Intel Corporation
SPDX-License-Identifier: MIT
@@ -305,7 +305,8 @@
Instruction *InsertBefore) {
if (isa<UndefValue>(Scalar))
return UndefValue::get(ReferenceType);
- else if (isa<PointerType>(Scalar->getType())) {
+ else if (isa<PointerType>(Scalar->getType()) &&
+ isa<PointerType>(ReferenceType)) {
auto Inner = getInnerPointerVectorNesting(ReferenceType);
return new BitCastInst(
Scalar, getTypeWithSingleElementVector(Scalar->getType(), Inner),
@@ -428,7 +429,7 @@
assert(OldInst);
auto NewParams = SmallVector<Value *, 8>{};
- for (auto ArgPair : llvm::zip(OldF.args(), NewF.args())) {
+ for (auto &&ArgPair : llvm::zip(OldF.args(), NewF.args())) {
auto &&OldArg = std::get<0>(ArgPair);
auto &&NewArg = std::get<1>(ArgPair);
auto ArgNo = OldArg.getArgNo();
@@ -622,7 +623,7 @@
manageSingleElementVectorAttributes(F, NewF);
if (NewF.size() > 0) {
- for (auto ArgPair : llvm::zip(F.args(), NewF.args()))
+ for (auto &&ArgPair : llvm::zip(F.args(), NewF.args()))
replaceAllUsesWith(std::get<0>(ArgPair), std::get<1>(ArgPair), NewF);
if (NewF.getReturnType() != F.getReturnType())
rewriteSingleElementVectorReturns(NewF);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/addr_conv_attribute_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -8,6 +8,7 @@
; Test @llvm.genx.address.convert intrinsic generation with proper attributes
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
define void @test(i32 %buf) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annot_mess_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -9,6 +9,7 @@
; Test messy annnotations translation in writer. First valid
; annotation should be matched.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
define void @test(i32 %im2d, i32 %samp, i64 %ptr, i32 %gen) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_mixed_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -9,6 +9,7 @@
; Test that reader can cope with mixed mode when some
; arguments use address convert and some do not.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%intel.buffer_rw_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -10,6 +10,7 @@
; not change other things if there is no address conversion
; but correct SPIRV types in signature.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%intel.buffer_rw_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_no_conv_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -9,6 +9,7 @@
; Test that writer does not changes signature if correct
; types are already used. Just drop all annotations.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
%intel.buffer_rw_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -10,6 +10,7 @@
; that SPIRV translator can understand to old style with
; metadata. Here annotations for OCL runtime are used.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%intel.buffer_rw_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/annotated_args_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -9,7 +9,7 @@
; Test kernel arguments translation from old style with metadata to
; new style with opaque types that SPIRV translator can
; understand. Here annotations for OCL runtime are used.
-; XFAIL: llvm13, llvm14, llvm15
+; XFAIL: llvm13, llvm14, llvm15, llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
; RUN: opt %pass%GenXSPIRVWriterAdaptor %pass%GenXSPIRVWriterAdaptor -S < %s |
FileCheck %s
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -8,7 +8,7 @@
; Test that adaptor correctly handles parameter attributes with types.
-; UNSUPPORTED: llvm8
+; UNSUPPORTED: llvm8, llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
; CHECK: @test
; CHECK-SAME: (%foo addrspace(1)* byval(%foo) %arg)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/args_attributes_transform_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -8,7 +8,7 @@
; Test that adaptor correctly handles parameter attributes with types.
-; UNSUPPORTED: llvm8
+; UNSUPPORTED: llvm8, llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
; CHECK: @test
; CHECK-SAME: %foo addrspace(1)* byval(%foo)
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/combined_args_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/combined_args_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/combined_args_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/combined_args_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -10,6 +10,7 @@
; and impicit arguments. Implicit arguments would not show in normal
; flow, though they appear in old cmc.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%opencl.image2d_ro_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/combined_args_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/combined_args_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/combined_args_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/combined_args_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -10,6 +10,7 @@
; arguments and impicit arguments. Implicit arguments would not show
; in normal flow, though they appear in old cmc.
; XFAIL: llvm13, llvm14, llvm15
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
; RUN: opt %pass%GenXSPIRVWriterAdaptor %pass%GenXSPIRVWriterAdaptor -S < %s |
FileCheck %s
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/fun_attributes_transform_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2021-2022 Intel Corporation
+; Copyright (C) 2021-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -9,7 +9,8 @@
; Test that adaptor correctly translates function attributes to VC-specific
; metadata (the processed attributes are expected to be discarded)
-; UNSUPPORTED: llvm8
+; UNSUPPORTED: llvm8, llvm17, llvm18
+; XFAIL: llvm15
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
; CHECK: @test_VCFunction()
; CHECK: @test_VCStackCall()
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/image_array_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/image_array_reader.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/image_array_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/image_array_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2021-2022 Intel Corporation
+; Copyright (C) 2021-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -8,6 +8,7 @@
; Test reader translation of image array arguments.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%opencl.image1d_array_ro_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/image_array_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/image_array_writer.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/image_array_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/image_array_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -8,6 +8,7 @@
; Test writer translation of image array arguments.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
define void @test(i32 %im1darr, i32 %im2darr) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/media_block_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/media_block_reader.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/media_block_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/media_block_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2021-2022 Intel Corporation
+; Copyright (C) 2021-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -8,6 +8,7 @@
; Test reader translation of media block image arguments.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%intel.image2d_media_block_ro_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/media_block_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/media_block_writer.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/media_block_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/media_block_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -8,6 +8,7 @@
; Test writer translation of media block images arguments.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
define void @test(i32 %image) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/non_global_ptr_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -9,6 +9,7 @@
; Test that reader treats only global pointer as svmptr type
; and ignores other address spaces.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
define spir_kernel void @test(i32* %ptr) #0 {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/old_decorated_args_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -11,6 +11,8 @@
; kernel metadata without any checks. Required until full transition
; is done.
+; UNSUPPORTED: llvm17, llvm18
+; XFAIL: llvm15
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
define spir_kernel void @test(i32 "VCArgumentDesc"="image2d_t read_only"
"VCArgumentKind"="2" %in, i32 "VCArgumentDesc"="image2d_t write_only"
"VCArgumentKind"="2" %out, <3 x i32> "VCArgumentKind"="24"
%__arg_llvm.genx.local.id) #0 {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/plain_args_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/plain_args_reader.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/plain_args_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/plain_args_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -10,6 +10,7 @@
; that SPIRV translator can understand to old style with
; metadata. Arguments without annotations are used here (CMRT like).
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%intel.buffer_rw_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/plain_args_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/plain_args_writer.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/plain_args_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/plain_args_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -9,6 +9,7 @@
; Test kernel arguments translation from old style with metadata to
; new style with opaque types that SPIRV translator can
; understand. Arguments without annotations are used here (CMRT like).
+; UNSUPPORTED: llvm17, llvm18
; XFAIL: llvm13, llvm14, llvm15
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
; RUN: opt %pass%GenXSPIRVWriterAdaptor %pass%GenXSPIRVWriterAdaptor -S < %s |
FileCheck %s
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2022 Intel Corporation
+; Copyright (C) 2022-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -9,6 +9,7 @@
; Test GenXSingleElementVectorUtil preserves calling convention
; (spir_func here)
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_calling_conv_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2022 Intel Corporation
+; Copyright (C) 2022-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -9,6 +9,7 @@
; Test GenXSingleElementVectorUtil preserves calling convention
; (spir_func here)
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
; ModuleID = 'sev_calling_conv_reader.ll'
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_ptr_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_ptr_reader.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_ptr_reader.ll
1970-01-01 01:00:00.000000000 +0100
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_ptr_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -0,0 +1,32 @@
+;=========================== begin_copyright_notice
============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice
=============================
+
+; UNSUPPORTED: llvm17, llvm18
+; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
+
+define internal void @foo(i32** "VCSingleElementVector"="1" %v) #0 {
+entry:
+ ; CHECK: [[SEV:[^ ]+]] = bitcast <1 x i32*>* %v to i32**
+ ; CHECK: %ld.v = load i32*, i32** [[SEV]], align 8
+ ; CHECK: %ld.ex = load i32, i32* %ld.v, align 4
+ %ld.v = load i32*, i32** %v, align 8
+ %ld.ex = load i32, i32* %ld.v, align 4
+ ret void
+}
+
+define internal "VCSingleElementVector"="2" i64*** @bar(i64**
"VCSingleElementVector"="2" %in, i64*** "VCSingleElementVector"="2" %out) #0 {
+entry:
+ ; CHECK: [[SEV:[^ ]+]] = bitcast <1 x i64**>* %out to i64***
+ ; CHECK: [[SEVIN:[^ ]+]] = extractelement <1 x i64**> %in, i64 0
+ ; CHECK: store i64** [[SEVIN]], i64*** [[SEV]], align 8
+ store i64** %in, i64*** %out, align 8
+ ; CHECK: ret <1 x i64**>* %out
+ ret i64*** %out
+}
+
+attributes #0 = { "VCFunction" }
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_ptr_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_ptr_writer.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_ptr_writer.ll
1970-01-01 01:00:00.000000000 +0100
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_ptr_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -0,0 +1,29 @@
+;=========================== begin_copyright_notice
============================
+;
+; Copyright (C) 2023 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice
=============================
+
+; UNSUPPORTED: llvm17, llvm18
+; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
+
+define internal void @foo(<1 x i32*>* %v) #0 {
+entry:
+ ; CHECK: %ld.v = load i32*, i32** %v, align 8
+ ; CHECK: %ld.ex = load i32, i32* %ld.v, align 4
+ %ld.v = load <1 x i32*>, <1 x i32*>* %v, align 8
+ %ex = extractelement <1 x i32*> %ld.v, i32 0
+ %ld.ex = load i32, i32* %ex, align 4
+ ret void
+}
+
+define internal <1 x i64**>* @bar(<1 x i64**> %in, <1 x i64**>* %out) #0 {
+entry:
+ ; CHECK: store i64** %in, i64*** %out, align 8
+ store <1 x i64**> %in, <1 x i64**>* %out, align 8
+ ret <1 x i64**>* %out
+}
+
+attributes #0 = { "VCFunction" }
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_signature_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -8,7 +8,8 @@
; Test simple signatures tranform
-; LLVM16 error: symbol with local linkage cannot have a DLL storage class
+; UNSUPPORTED: llvm17, llvm18
+; LLVM16 error: symbol with local linkage cannot have a DLL storage class
; for test-function (internal dllexport)
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_signature_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -8,6 +8,7 @@
; Test simple signatures tranform
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
; CHECK: @global_var_0 = internal global i32 undef, align 4
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_struct.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_struct.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/sev_struct.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/sev_struct.ll
2023-10-25 00:27:31.000000000 +0200
@@ -6,12 +6,13 @@
;
;============================ end_copyright_notice
=============================
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
target datalayout = "e-p:64:64-i64:64-n8:16:32"
target triple = "spir64"
-; CHECK: [[STRUCT1:[^ ]+]] = type { i32, <2 x i32>, [[STRUCT2:[^ ]+]] }
+; CHECK: [[STRUCT1:[^ ]+]] = type { i32, <2 x i32>, [[STRUCT2:[^ ]+]] }
%struct.sev_test = type { <1 x i32>, <2 x i32>, %struct.sev_test_nested }
; CHECK: [[STRUCT2]] = type { i32*, <2 x i32>*, [[STRUCT1]]* }
%struct.sev_test_nested = type { <1 x i32>*, <2 x i32>*, %struct.sev_test* }
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/spirv_friendly_types_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2021-2022 Intel Corporation
+; Copyright (C) 2021-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -8,6 +8,7 @@
; Test reader translation of SPIRV friendly IR types
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%spirv.Sampler = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/surface_access_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/surface_access_reader.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/surface_access_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/surface_access_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -10,6 +10,7 @@
; types that SPIRV translator can understand to old style with
; metadata. This test checks access qualifiers translation.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
%intel.buffer_ro_t = type opaque
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/surface_access_writer.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/surface_access_writer.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/surface_access_writer.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/surface_access_writer.ll
2023-10-25 00:27:31.000000000 +0200
@@ -10,6 +10,7 @@
; metadata to new style with opaque types that SPIRV translator can
; understand. This test checks access qualifiers translation.
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%GenXSPIRVWriterAdaptor -S < %s | FileCheck %s
define void @test(i32 %buf, i32 %im1d, i32 %im1db, i32 %im2d, i32 %im3d) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll
2023-05-16 01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/Adaptors/unknown_arg_reader.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,6 +1,6 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
@@ -9,6 +9,8 @@
; Test reader translation of implicit argument with argument kind
; decoration.
+; UNSUPPORTED: llvm17, llvm18
+; XFAIL: llvm15
; RUN: opt %pass%GenXSPIRVReaderAdaptor -S < %s | FileCheck %s
define spir_kernel void @test(<3 x i32> "VCArgumentKind"="24"
%__arg_llvm.genx.local.id) #0 {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/bitcast_between_wrrs.ll
2023-10-25 00:27:31.000000000 +0200
@@ -6,6 +6,7 @@
;
;============================ end_copyright_notice
=============================
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s
@Rcp_T2 = internal global <64 x double> undef
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/predicate_masked_gather.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,14 +1,15 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice
=============================
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s
-; CHECK: @EM = internal global <32 x i1>
+; CHECK: @EM = internal global <32 x i1>
@g2 = internal global <32 x i32> undef
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,16 +1,17 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice
=============================
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s
@g1 = internal global <64 x i32> undef
-; CHECK: @EM = internal global <32 x i1>
+; CHECK: @EM = internal global <32 x i1>
; CHECK-LABEL: @test
define dso_local dllexport void @test(<32 x i16> %mask) {
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/replicate_mask_masked_gather4.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,16 +1,17 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2021-2022 Intel Corporation
+; Copyright (C) 2021-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice
=============================
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s
@Rcp_T2 = internal global <64 x i32> undef
-; CHECK: @EM = internal global <32 x i1>
+; CHECK: @EM = internal global <32 x i1>
define dso_local dllexport void @test(<32 x i16> %mask, <32 x i32> %addrs) {
entry:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll
---
old/vc-intrinsics-0.13.0/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll
2023-05-16 01:51:29.000000000 +0200
+++
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/SimdCFLowering/update_mask_masked_gather4.ll
2023-10-25 00:27:31.000000000 +0200
@@ -1,16 +1,17 @@
;=========================== begin_copyright_notice
============================
;
-; Copyright (C) 2020-2022 Intel Corporation
+; Copyright (C) 2020-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice
=============================
+; UNSUPPORTED: llvm17, llvm18
; RUN: opt %pass%cmsimdcflowering -S < %s | FileCheck %s
@g1 = internal global <64 x i32> undef
-; CHECK: @EM = internal global <32 x i1>
+; CHECK: @EM = internal global <32 x i1>
define dso_local dllexport void @test(<32 x i16> %cond1, <32 x i16> %cond2,
<32 x i32> %addrs, <32 x i1> %pred) {
entry:
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/vc-intrinsics-0.13.0/GenXIntrinsics/test/lit.cfg.py
new/vc-intrinsics-0.14.0/GenXIntrinsics/test/lit.cfg.py
--- old/vc-intrinsics-0.13.0/GenXIntrinsics/test/lit.cfg.py 2023-05-16
01:51:29.000000000 +0200
+++ new/vc-intrinsics-0.14.0/GenXIntrinsics/test/lit.cfg.py 2023-10-25
00:27:31.000000000 +0200
@@ -63,7 +63,8 @@
else:
config.substitutions.append(('%pass%', ' -passes='))
-if int(config.llvm_version_major) >= 16:
+print(f"llvm_version_major:{config.llvm_version_major}")
+if int(config.llvm_version_major) == 16:
opt_extra_args.insert(0, '-opaque-pointers=0')
tools = [ToolSubst('opt', extra_args=opt_extra_args)]
