--- Begin Message ---
Author: laforge
Date: 2007-08-27 14:25:11 +0200 (Mon, 27 Aug 2007)
New Revision: 2834
Added:
trunk/src/target/u-boot/patches/uboot-s3c2442.patch
Modified:
trunk/src/target/u-boot/patches/series
trunk/src/target/u-boot/patches/uboot-cmd_s3c2410.patch
trunk/src/target/u-boot/patches/uboot-gta02.patch
trunk/src/target/u-boot/patches/uboot-s3c2410-mmc.patch
trunk/src/target/u-boot/patches/uboot-s3c2440.patch
trunk/src/target/u-boot/patches/uboot-s3c2443.patch
Log:
* split s3c2442 support from s3c2440 (different PLL config)
* fix s3c2440/2442 pll speed calculation
* add pll speed settings to cmd_s3c24xx for s3c2440 and s3c2442
* fix hand-calculated UPLL initializers for 2442 (user manual is wrong)
Modified: trunk/src/target/u-boot/patches/series
===================================================================
--- trunk/src/target/u-boot/patches/series 2007-08-27 00:27:06 UTC (rev
2833)
+++ trunk/src/target/u-boot/patches/series 2007-08-27 12:25:11 UTC (rev
2834)
@@ -66,6 +66,7 @@
uboot-smdk2440.patch
uboot-hxd8.patch
+uboot-s3c2442.patch
uboot-license.patch
uboot-gta02.patch
Modified: trunk/src/target/u-boot/patches/uboot-cmd_s3c2410.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-cmd_s3c2410.patch 2007-08-27
00:27:06 UTC (rev 2833)
+++ trunk/src/target/u-boot/patches/uboot-cmd_s3c2410.patch 2007-08-27
12:25:11 UTC (rev 2834)
@@ -12,15 +12,15 @@
COBJS = i2c.o interrupts.o serial.o speed.o \
- usb.o nand_read.o nand.o
-+ usb.o nand_read.o nand.o cmd_s3c2410.o
++ usb.o nand_read.o nand.o cmd_s3c24xx.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c2410.c
+Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
===================================================================
--- /dev/null
-+++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c2410.c
-@@ -0,0 +1,152 @@
++++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2006 by OpenMoko, Inc.
+ * Author: Harald Welte <[EMAIL PROTECTED]>
@@ -61,11 +61,11 @@
+
+static void print_cpu_speed(void)
+{
-+ printf("FCLK = %u MHz, HCLK = %u MHz, PCLK = %u MHz\n",
-+ get_FCLK()/MHZ, get_HCLK()/MHZ, get_PCLK()/MHZ);
++ printf("FCLK = %u MHz, HCLK = %u MHz, PCLK = %u MHz, UCLK = %u MHz\n",
++ get_FCLK()/MHZ, get_HCLK()/MHZ, get_PCLK()/MHZ, get_UCLK()/MHZ);
+}
+
-+struct s3c2410_pll_speed {
++struct s3c24x0_pll_speed {
+ u_int16_t mhz;
+ u_int32_t mpllcon;
+ u_int32_t clkdivn;
@@ -76,7 +76,9 @@
+#define CLKDIVN_1_2_4 0x03
+#define CLKDIVN_1_4_4 0x04
+
-+static const struct s3c2410_pll_speed pll_configs[] = {
++#if defined(CONFIG_S3C2410)
++static const u_int32_t upllcon = ((0x78 << 12) + (0x2 << 4) + 0x3);
++static const struct s3c24x0_pll_speed pll_configs[] = {
+ {
+ .mhz = 50,
+ .mpllcon = ((0x5c << 12) + (0x4 << 4) + 0x2),
@@ -98,6 +100,9 @@
+ .clkdivn = CLKDIVN_1_2_4,
+ },
+};
++#else
++#error "please define valid pll configurations for your cpu type"
++#endif
+
+static void list_cpu_speeds(void)
+{
@@ -118,7 +123,7 @@
+
+ /* configure MPLL */
+ clk_power->MPLLCON = pll_configs[i].mpllcon;
-+ clk_power->UPLLCON = ((0x78 << 12) + (0x2 << 4) + 0x3),
++ clk_power->UPLLCON = upllcon;
+ clk_power->CLKDIVN = pll_configs[i].clkdivn;
+
+ /* If we changed the speed, we need to re-configure
@@ -130,7 +135,7 @@
+ return -1;
+}
+
-+int do_s3c2410 ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++int do_s3c24xx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (!strcmp(argv[1], "speed")) {
+ if (argc < 2)
@@ -165,11 +170,11 @@
+
+
+U_BOOT_CMD(
-+ s3c2410, 4, 1, do_s3c2410,
-+ "s3c2410 - SoC specific commands\n",
++ s3c24xx, 4, 1, do_s3c24xx,
++ "s3c24x0 - SoC specific commands\n",
+ "speed get - display current PLL speed config\n"
-+ "s3c2410 speed list - display supporte PLL speed configs\n"
-+ "s3c2410 speed set - set PLL speed\n"
++ "s3c24x0 speed list - display supporte PLL speed configs\n"
++ "s3c24x0 speed set - set PLL speed\n"
+);
+
+#endif
Modified: trunk/src/target/u-boot/patches/uboot-gta02.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-gta02.patch 2007-08-27 00:27:06 UTC
(rev 2833)
+++ trunk/src/target/u-boot/patches/uboot-gta02.patch 2007-08-27 12:25:11 UTC
(rev 2834)
@@ -152,9 +152,9 @@
+#define M_MDIV 80
+#define M_PDIV 8
+#define M_SDIV 0
-+#define U_M_MDIV 80
-+#define U_M_PDIV 8
-+#define U_M_SDIV 1
++#define U_M_MDIV 88
++#define U_M_PDIV 4
++#define U_M_SDIV 2
+#endif
+
+unsigned int neo1973_wakeup_cause;
@@ -529,7 +529,7 @@
===================================================================
--- /dev/null
+++ u-boot/include/configs/neo1973_gta02.h
-@@ -0,0 +1,274 @@
+@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2007 OpenMoko, Inc.
+ * Author: Harald Welte <[EMAIL PROTECTED]>
@@ -570,7 +570,6 @@
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core
*/
-+#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2410 SoC
*/
+#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board
*/
+
+/* input clock of PLL */
@@ -655,8 +654,10 @@
+#define CFG_LONGHELP /* undef to save memory
*/
+#if defined(CONFIG_ARCH_GTA02_v1)
+#define CFG_PROMPT "GTA02v1 # " /* Monitor Command
Prompt */
++#define CONFIG_S3C2440 1 /* SAMSUNG S3C2440 SoC
*/
+#elif defined(CONFIG_ARCH_GTA02_v2)
+#define CFG_PROMPT "GTA02v2 # " /* Monitor Command
Prompt */
++#define CONFIG_S3C2442 1 /* SAMSUNG S3C2442 SoC
*/
+#endif
+#define CFG_CBSIZE 256 /* Console I/O Buffer
Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer
Size */
Modified: trunk/src/target/u-boot/patches/uboot-s3c2410-mmc.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2410-mmc.patch 2007-08-27
00:27:06 UTC (rev 2833)
+++ trunk/src/target/u-boot/patches/uboot-s3c2410-mmc.patch 2007-08-27
12:25:11 UTC (rev 2834)
@@ -11,8 +11,8 @@
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
-- usb.o nand_read.o nand.o cmd_s3c2410.o
-+ usb.o nand_read.o nand.o mmc.o cmd_s3c2410.o
+- usb.o nand_read.o nand.o cmd_s3c24xx.o
++ usb.o nand_read.o nand.o mmc.o cmd_s3c24xx.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
Modified: trunk/src/target/u-boot/patches/uboot-s3c2440.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2440.patch 2007-08-27 00:27:06 UTC
(rev 2833)
+++ trunk/src/target/u-boot/patches/uboot-s3c2440.patch 2007-08-27 12:25:11 UTC
(rev 2834)
@@ -526,27 +526,32 @@
#endif
#define MPLL 0
-@@ -66,8 +69,12 @@
+@@ -66,8 +69,17 @@
m = ((r & 0xFF000) >> 12) + 8;
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
-
-+#ifndef CONFIG_S3C2440
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
++#elif defined(CONFIG_S3C2440)
++ /* To avoid integer overflow, changed the calc order */
++ if (pllreg == MPLL)
++ return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
++ else
++ return ( m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
+#else
-+ /* To avoid integer overflow, changed the calc order */
-+ return( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
++#error "get_PLLCLK not implemented for CPU type"
+#endif
}
/* return FCLK frequency */
-@@ -81,7 +88,21 @@
+@@ -81,7 +93,23 @@
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
-+#ifndef CONFIG_S3C2440
++#if defined(CONFOG_S3C2400) || defined(CONFIG_S3C2410)
return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
-+#else
++#elif defined(CONFIG_S3C2440)
+ switch (clk_power->CLKDIVN & 0x6) {
+ case 0x0:
+ return get_FCLK();
@@ -558,11 +563,13 @@
+ return (clk_power->CAMDIVN & 0x100) ? get_FCLK()/6 : get_FCLK()/3;
+ }
+ return 0;
++#else
++#error "get_HCLK not implemented for CPU type"
+#endif
}
/* return PCLK frequency */
-@@ -98,4 +119,5 @@
+@@ -98,4 +126,5 @@
return(get_PLLCLK(UPLL));
}
@@ -1338,3 +1345,112 @@
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
defined(CONFIG_MPC5200)
+Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
++++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+@@ -27,7 +27,11 @@
+ #include <common.h>
+ #include <command.h>
+ #include <net.h> /* for print_IPaddr */
++#if defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
++#elif defined(CONFIG_S3C2440)
++#include <s3c2440.h>
++#endif
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -46,6 +50,7 @@
+ u_int16_t mhz;
+ u_int32_t mpllcon;
+ u_int32_t clkdivn;
++ u_int32_t camdivn;
+ };
+
+ #define CLKDIVN_1_1_1 0x00
+@@ -53,6 +58,11 @@
+ #define CLKDIVN_1_2_4 0x03
+ #define CLKDIVN_1_4_4 0x04
+
++#if defined(CONFIG_S3C2440)
++#define CLKDIVN_1_4_8 0x05
++#define CLKDIVN_1_3_6 0x07
++#endif
++
+ #if defined(CONFIG_S3C2410)
+ static const u_int32_t upllcon = ((0x78 << 12) + (0x2 << 4) + 0x3);
+ static const struct s3c24x0_pll_speed pll_configs[] = {
+@@ -77,6 +87,61 @@
+ .clkdivn = CLKDIVN_1_2_4,
+ },
+ };
++#elif defined(CONFIG_S3C2440)
++/* from page 7-21 of S3C2440A user's manual Revision 1 */
++#if (CONFIG_SYS_CLK_FREQ == 12000000)
++static const u_int32_t upllcon = ((0x38 << 12) + (2 << 4) + 2);
++static const struct s3c24x0_pll_speed pll_configs[] = {
++ {
++ .mhz = 200,
++ .mpllcon = ((142 << 12) + (7 << 4) + 1),
++ .clkdivn = CLKDIVN_1_2_4,
++ },
++ {
++ .mhz = 271,
++ .mpllcon = ((0xad << 12) + (0x2 << 4) + 0x2),
++ .clkdivn = CLKDIVN_1_2_4,
++ },
++ {
++ .mhz = 304,
++ .mpllcon = ((0x7d << 12) + (0x1 << 4) + 0x1),
++ .clkdivn = CLKDIVN_1_3_6,
++ },
++ {
++ .mhz = 405,
++ .mpllcon = ((0x7f << 12) + (0x2 << 4) + 0x1),
++ .clkdivn = CLKDIVN_1_3_6,
++ },
++#elif (CONFIG_SYS_CLK_FREQ == 16934400)
++static const u_int32_t upllcon = ((0x3c << 12) + (2 << 4) + 2);
++static const struct s3c24x0_pll_speed pll_configs[] = {
++ {
++ .mhz = 200,
++ .mpllcon = ((181 << 12) + (14 << 4) + 1),
++ .clkdivn = CLKDIVN_1_2_4,
++ },
++ {
++ .mhz = 266,
++ .mpllcon = ((0x76 << 12) + (0x2 << 4) + 0x2),
++ .clkdivn = CLKDIVN_1_2_4,
++ .camdivn = 0,
++ },
++ {
++ .mhz = 296,
++ .mpllcon = ((0x61 << 12) + (0x1 << 4) + 0x2),
++ .clkdivn = CLKDIVN_1_3_6,
++ .camdivn = 0,
++ },
++ {
++ .mhz = 399,
++ .mpllcon = ((0x6e << 12) + (0x3 << 4) + 0x1),
++ .clkdivn = CLKDIVN_1_3_6,
++ .camdivn = 0,
++ },
++#else
++#error "clock frequencies != 12MHz / 16.9344MHz not supported"
++#endif
++};
+ #else
+ #error "please define valid pll configurations for your cpu type"
+ #endif
+@@ -95,6 +160,10 @@
+
+ for (i = 0; i < ARRAY_SIZE(pll_configs); i++) {
+ if (pll_configs[i].mhz == mhz) {
++#if defined(CONFIG_S3C2440)
++ clk_power->CAMDIVN &= ~0x30;
++ clk_power->CAMDIVN |= pll_configs[i].camdivn;
++#endif
+ /* to reduce PLL lock time, adjust the LOCKTIME
register */
+ clk_power->LOCKTIME = 0xFFFFFF;
+
Added: trunk/src/target/u-boot/patches/uboot-s3c2442.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2442.patch 2007-08-27 00:27:06 UTC
(rev 2833)
+++ trunk/src/target/u-boot/patches/uboot-s3c2442.patch 2007-08-27 12:25:11 UTC
(rev 2834)
@@ -0,0 +1,630 @@
+Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
++++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+@@ -29,7 +29,7 @@
+ #include <net.h> /* for print_IPaddr */
+ #if defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+
+@@ -58,7 +58,7 @@
+ #define CLKDIVN_1_2_4 0x03
+ #define CLKDIVN_1_4_4 0x04
+
+-#if defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #define CLKDIVN_1_4_8 0x05
+ #define CLKDIVN_1_3_6 0x07
+ #endif
+@@ -142,6 +142,49 @@
+ #error "clock frequencies != 12MHz / 16.9344MHz not supported"
+ #endif
+ };
++#elif defined(CONFIG_S3C2442)
++#if (CONFIG_SYS_CLK_FREQ == 12000000)
++/* The value suggested in the user manual ((80 << 12) + (8 << 4) + 1) leads to
++ * 52MHz, i.e. completely wrong */
++static const u_int32_t upllcon = ((88 << 12) + (4 << 4) + 2);
++static const struct s3c24x0_pll_speed pll_configs[] = {
++ {
++ .mhz = 200,
++ .mpllcon = ((42 << 12) + (1 << 4) + 1),
++ .clkdivn = CLKDIVN_1_2_4,
++ .camdivn = 0,
++ },
++ {
++ .mhz = 300,
++ .mpllcon = ((67 << 12) + (1 << 4) + 1),
++ .clkdivn = CLKDIVN_1_3_6,
++ .camdivn = 0,
++ },
++ {
++ .mhz = 400,
++ .mpllcon = ((42 << 12) + (1 << 4) + 0),
++ .clkdivn = CLKDIVN_1_4_8,
++ .camdivn = 0,
++ },
++#elif (CONFIG_SYS_CLK_FREQ == 16934400)
++static const u_int32_t upllcon = ((26 << 12) + (4 << 4) + 1);
++static const struct s3c24x0_pll_speed pll_configs[] = {
++ {
++ .mhz = 296,
++ .mpllcon = ((62 << 12) + (1 << 4) + 2),
++ .clkdivn = CLKDIVN_1_3_6,
++ .camdivn = 0,
++ },
++ {
++ .mhz = 400,
++ .mpllcon = ((63 << 12) + (4 << 4) + 0),
++ .clkdivn = CLKDIVN_1_4_8,
++ .camdivn = 0,
++ },
++#else
++#error "clock frequencies != 12MHz / 16.9344MHz not supported"
++#endif
++};
+ #else
+ #error "please define valid pll configurations for your cpu type"
+ #endif
+Index: u-boot/cpu/arm920t/s3c24x0/i2c.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/i2c.c
++++ u-boot/cpu/arm920t/s3c24x0/i2c.c
+@@ -34,7 +34,7 @@
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+ #include <i2c.h>
+@@ -65,7 +65,8 @@
+ {
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ return (gpio->GPEDAT & 0x8000) >> 15;
+ #endif
+ #ifdef CONFIG_S3C2400
+@@ -84,7 +85,8 @@
+ {
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
+ #endif
+ #ifdef CONFIG_S3C2400
+@@ -141,7 +143,8 @@
+ }
+
+ if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ ulong old_gpecon = gpio->GPECON;
+ #endif
+ #ifdef CONFIG_S3C2400
+@@ -149,7 +152,8 @@
+ #endif
+ /* bus still busy probably by (most) previously interrupted
transfer */
+
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
+ gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
+ #endif
+@@ -173,7 +177,8 @@
+ udelay (1000);
+
+ /* restore pin functions */
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ gpio->GPECON = old_gpecon;
+ #endif
+ #ifdef CONFIG_S3C2400
+Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
++++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
+@@ -31,14 +31,15 @@
+
+ #include <common.h>
+ #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
++ defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) || \
++ defined (CONFIG_TRAB)
+
+ #include <arm920t.h>
+ #if defined(CONFIG_S3C2400)
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+
+@@ -62,7 +63,7 @@
+ /* use PWM Timer 4 because it has no output */
+ /* prescaler for Timer 4 is 16 */
+ timers->TCFG0 = 0x0f00;
+-#ifndef CONFIG_S3C2440
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+ if (timer_load_val == 0)
+ {
+ /*
+@@ -241,4 +242,5 @@
+ #endif /* USE_IRQ */
+
+ #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
+- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
++ defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) ||
++ defined (CONFIG_TRAB) */
+Index: u-boot/cpu/arm920t/s3c24x0/mmc.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/mmc.c
++++ u-boot/cpu/arm920t/s3c24x0/mmc.c
+@@ -137,7 +137,7 @@
+ dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART;
+ if (wide)
+ dcon |= S3C2410_SDIDCON_WIDEBUS;
+-#if defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
+ #endif
+ sdi->SDIDCON = dcon;
+@@ -403,7 +403,7 @@
+ //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */
+ sdi->SDIPRE = 0x02; /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */
+ sdi->SDIDTIMER = 0xffff;
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ sdi->SDIPRE = 0x05; /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */
+ sdi->SDIDTIMER = 0x7fffff;
+ #endif
+Index: u-boot/cpu/arm920t/s3c24x0/nand.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c
++++ u-boot/cpu/arm920t/s3c24x0/nand.c
+@@ -58,7 +58,7 @@
+ #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
+ #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
+
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+
+ #define oNFCMD 0x8
+ #define oNFADDR 0xc
+@@ -147,7 +147,7 @@
+ case NAND_CTL_SETNCE:
+ #if defined(CONFIG_S3C2410)
+ NFCONF &= ~NFCONF_nFCE;
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ NFCONT &= ~NFCONF_nFCE;
+ #endif
+ DEBUGN("NFCONF=0x%08x\n", NFCONF);
+@@ -155,7 +155,7 @@
+ case NAND_CTL_CLRNCE:
+ #if defined(CONFIG_S3C2410)
+ NFCONF |= NFCONF_nFCE;
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ NFCONT &= ~NFCONF_nFCE;
+ #endif
+ DEBUGN("NFCONF=0x%08x\n", NFCONF);
+@@ -278,7 +278,7 @@
+ cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
+
+ NFCONF = cfg;
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ twrph0 = 7; twrph1 = 7; tacls = 7;
+ NFCONF = (tacls<<12)|(twrph0<<8)|(twrph1<<4)|(0<<0);
+ NFCONT =
(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
+@@ -315,7 +315,7 @@
+ nand->options = 0;
+ #endif
+
+-#if defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ /*
+ nand_select();
+ nand_clear_RnB();
+Index: u-boot/cpu/arm920t/s3c24x0/nand_read.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/nand_read.c
++++ u-boot/cpu/arm920t/s3c24x0/nand_read.c
+@@ -34,7 +34,7 @@
+ #define nand_select() (NFCONF &= ~0x800)
+ #define nand_deselect() (NFCONF |= 0x800)
+ #define nand_clear_RnB() do {} while (0)
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #define NFCONF __REGi(NF_BASE + 0x0)
+ #define NFCONT __REGi(NF_BASE + 0x4)
+ #define NFCMD __REGb(NF_BASE + 0x8)
+@@ -142,7 +142,7 @@
+ *buf = (NFDATA & 0xff);
+ buf++;
+ }
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ for (i = 0; i < NAND_PAGE_SIZE/2; i++) {
+ *ptr16 = NFDATA16;
+ ptr16++;
+Index: u-boot/cpu/arm920t/s3c24x0/serial.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/serial.c
++++ u-boot/cpu/arm920t/s3c24x0/serial.c
+@@ -20,13 +20,14 @@
+
+ #include <common.h>
+ #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
++ defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) || \
++ defined (CONFIG_TRAB)
+
+ #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+
+@@ -184,4 +185,5 @@
+ }
+
+ #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
+- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
++ defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) ||
++ defined (CONFIG_TRAB) */
+Index: u-boot/cpu/arm920t/s3c24x0/speed.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/speed.c
++++ u-boot/cpu/arm920t/s3c24x0/speed.c
+@@ -31,13 +31,13 @@
+
+ #include <common.h>
+ #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
+- defined (CONFIG_S3C2440) || defined (CONFIG_TRAB)
++ defined (CONFIG_S3C2440) || defined(CONFIG_S3C2442) || defined
(CONFIG_TRAB)
+
+ #if defined(CONFIG_S3C2400)
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+
+@@ -71,7 +71,7 @@
+ s = r & 0x3;
+ #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
+ return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ /* To avoid integer overflow, changed the calc order */
+ if (pllreg == MPLL)
+ return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
+@@ -95,7 +95,7 @@
+
+ #if defined(CONFOG_S3C2400) || defined(CONFIG_S3C2410)
+ return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ switch (clk_power->CLKDIVN & 0x6) {
+ case 0x0:
+ return get_FCLK();
+@@ -127,4 +127,5 @@
+ }
+
+ #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
+- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
++ defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) ||
++ defined (CONFIG_TRAB) */
+Index: u-boot/cpu/arm920t/s3c24x0/usb.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/usb.c
++++ u-boot/cpu/arm920t/s3c24x0/usb.c
+@@ -24,13 +24,14 @@
+ #include <common.h>
+
+ #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+-# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440)
++# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+
+ #if defined(CONFIG_S3C2400)
+ # include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ # include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ # include <s3c2440.h>
+ #endif
+
+@@ -70,5 +71,6 @@
+ return 0;
+ }
+
+-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440) */
++# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) */
+ #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
+Index: u-boot/cpu/arm920t/s3c24x0/usb_ohci.c
+===================================================================
+--- u-boot.orig/cpu/arm920t/s3c24x0/usb_ohci.c
++++ u-boot/cpu/arm920t/s3c24x0/usb_ohci.c
+@@ -44,7 +44,7 @@
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+
+Index: u-boot/cpu/arm920t/start.S
+===================================================================
+--- u-boot.orig/cpu/arm920t/start.S
++++ u-boot/cpu/arm920t/start.S
+@@ -33,7 +33,7 @@
+ #include <version.h>
+ #if defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+ #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) ||
defined(CONFIG_AT91RM9200DF)
+@@ -211,7 +211,7 @@
+ # define pWTCON 0x15300000
+ # define INTMSK 0x14400008 /* Interupt-Controller base
addresses */
+ # define CLKDIVN 0x14800014 /* clock divisor register */
+-#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) ||
defined(CONFIG_S3C2442)
+ # define pWTCON 0x53000000
+ # define INTMSK 0x4A000008 /* Interupt-Controller base
addresses */
+ # define INTSUBMSK 0x4A00001C
+@@ -234,9 +234,21 @@
+ #endif
+ # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
+ # define CAMDIVN 0x4C000018
++#elif defined(CONFIG_S3C2442)
++# define INTSUBMSK_val 0xffff
++# if (CONFIG_SYS_CLK_FREQ == 12000000)
++# define MPLLCON_val ((142 << 12) + (7 << 4) + 1)
++# define UPLLCON_val (( 88 << 12) + (8 << 4) + 2)
++# elif (CONFIG_SYS_CLK_FREQ == 16934400)
++# define MPLLCON_val ((181 << 12) + (14<< 4) + 1)
++# define UPLLCON_val (( 26 << 12) + (4 << 4) + 1)
++# endif
++# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
++# define CAMDIVN 0x4C000018
+ #endif
+
+-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
+@@ -247,13 +259,13 @@
+ mov r1, #0xffffffff
+ ldr r0, =INTMSK
+ str r1, [r0]
+-# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ||
defined(CONFIG_S3C2442)
+ ldr r1, =INTSUBMSK_val
+ ldr r0, =INTSUBMSK
+ str r1, [r0]
+ # endif
+
+-#if defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
+ ldr r0, =CAMDIVN
+ mov r1, #0
+@@ -319,7 +331,7 @@
+ str r1, [r0, #0x28]
+ #endif
+
+-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */
++#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 ||
CONFIG_S3C2442 */
+
+ #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ #ifndef CONFIG_LL_INIT_NAND_ONLY
+@@ -396,7 +408,7 @@
+ #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
+ bl cpu_init_crit
+ #endif
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ||
defined(CONFIG_S3C2442)
+ /* ensure some refresh has happened */
+ ldr r1, =0xfffff
+ 1: subs r1, r1, #1
+@@ -407,7 +419,7 @@
+ ldr r0, [ r1 ]
+ tst r0, #0x02 /* is this resume from power down */
+ ldrne pc, [r1, #4] /* gstatus3 */
+-#endif /* CONFIG_S3C2410 || CONFIG_S3C2440 */
++#endif /* CONFIG_S3C2410 || CONFIG_S3C2440 || CONFIG_S3C2442*/
+ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+ /* mov r10, lr */
+@@ -432,7 +444,7 @@
+ ldr r2, [r1, #oNFCONF]
+ orr r2, r2, #0x800 @ disable chip
+ str r2, [r1, #oNFCONF]
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ mov r1, #S3C2440_NAND_BASE
+ ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7
+ ldr r3, [r1, #oNFCONF]
+@@ -511,7 +523,8 @@
+ #endif /* CONFIG_S3C2410_NAND_BOOT */
+ done_relocate:
+
+-#if defined(CONFIG_USE_IRQ) && (defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440))
++#if defined(CONFIG_USE_IRQ) && (defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442))
+ /* In the case of the S3C2410, if we've somehow magically (JTAG, ...)
+ ended up in RAM, then that ram is mapped to 0x30000000 and not 0.
+ So we need to copy the interrupt vectors, etc. */
+Index: u-boot/drivers/usbdcore_s3c2410.c
+===================================================================
+--- u-boot.orig/drivers/usbdcore_s3c2410.c
++++ u-boot/drivers/usbdcore_s3c2410.c
+@@ -24,7 +24,8 @@
+
+ #include <config.h>
+
+-#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) &&
defined(CONFIG_USB_DEVICE)
++#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)) && defined(CONFIG_USB_DEVICE)
+
+ #include <common.h>
+
+Index: u-boot/drivers/usbtty.h
+===================================================================
+--- u-boot.orig/drivers/usbtty.h
++++ u-boot/drivers/usbtty.h
+@@ -29,7 +29,8 @@
+ #include "usbdcore_mpc8xx.h"
+ #elif defined(CONFIG_OMAP1510)
+ #include "usbdcore_omap1510.h"
+-#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ #include "usbdcore_s3c2410.h"
+ #endif
+
+Index: u-boot/include/common.h
+===================================================================
+--- u-boot.orig/include/common.h
++++ u-boot/include/common.h
+@@ -479,7 +479,9 @@
+ ulong get_OPB_freq (void);
+ ulong get_PCI_freq (void);
+ #endif
+-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440) || defined(CONFIG_LH7A40X)
++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) || \
++ defined(CONFIG_LH7A40X)
+ void s3c2410_irq(void);
+ #define ARM920_IRQ_CALLBACK s3c2410_irq
+ ulong get_FCLK (void);
+Index: u-boot/include/s3c24x0.h
+===================================================================
+--- u-boot.orig/include/s3c24x0.h
++++ u-boot/include/s3c24x0.h
+@@ -82,7 +82,8 @@
+ S3C24X0_REG32 PRIORITY;
+ S3C24X0_REG32 INTPND;
+ S3C24X0_REG32 INTOFFSET;
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ S3C24X0_REG32 SUBSRCPND;
+ S3C24X0_REG32 INTSUBMSK;
+ #endif
+@@ -92,11 +93,13 @@
+ /* DMAS (see manual chapter 8) */
+ typedef struct {
+ S3C24X0_REG32 DISRC;
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ S3C24X0_REG32 DISRCC;
+ #endif
+ S3C24X0_REG32 DIDST;
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ S3C24X0_REG32 DIDSTC;
+ #endif
+ S3C24X0_REG32 DCON;
+@@ -107,7 +110,8 @@
+ #ifdef CONFIG_S3C2400
+ S3C24X0_REG32 res[1];
+ #endif
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ S3C24X0_REG32 res[7];
+ #endif
+ } /*__attribute__((__packed__))*/ S3C24X0_DMA;
+@@ -126,7 +130,7 @@
+ S3C24X0_REG32 CLKCON;
+ S3C24X0_REG32 CLKSLOW;
+ S3C24X0_REG32 CLKDIVN;
+-#ifdef CONFIG_S3C2440
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ S3C24X0_REG32 CAMDIVN;
+ #endif
+ } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
+@@ -148,7 +152,8 @@
+ S3C24X0_REG32 res[8];
+ S3C24X0_REG32 DITHMODE;
+ S3C24X0_REG32 TPAL;
+-#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
++ defined(CONFIG_S3C2442)
+ S3C24X0_REG32 LCDINTPND;
+ S3C24X0_REG32 LCDSRCPND;
+ S3C24X0_REG32 LCDINTMSK;
+@@ -160,7 +165,7 @@
+ /* NAND FLASH (see S3C2410 manual chapter 6) */
+ typedef struct {
+ S3C24X0_REG32 NFCONF;
+-#ifdef CONFIG_S3C2440
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ S3C24X0_REG32 NFCONT;
+ #endif
+ S3C24X0_REG32 NFCMD;
+@@ -466,7 +471,7 @@
+ S3C24X0_REG32 GSTATUS3;
+ S3C24X0_REG32 GSTATUS4;
+ #endif
+-#ifdef CONFIG_S3C2440
++#if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ S3C24X0_REG32 GPACON;
+ S3C24X0_REG32 GPADAT;
+ S3C24X0_REG32 res1[2];
+@@ -714,7 +719,7 @@
+ #if defined(CONFIG_S3C2410)
+ S3C24X0_REG32 SDIDAT;
+ S3C24X0_REG32 SDIIMSK;
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ S3C24X0_REG32 SDIIMSK;
+ S3C24X0_REG32 SDIDAT;
+ #endif
+Index: u-boot/rtc/s3c24x0_rtc.c
+===================================================================
+--- u-boot.orig/rtc/s3c24x0_rtc.c
++++ u-boot/rtc/s3c24x0_rtc.c
+@@ -34,7 +34,7 @@
+ #include <s3c2400.h>
+ #elif defined(CONFIG_S3C2410)
+ #include <s3c2410.h>
+-#elif defined(CONFIG_S3C2440)
++#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
+ #include <s3c2440.h>
+ #endif
+
Modified: trunk/src/target/u-boot/patches/uboot-s3c2443.patch
===================================================================
--- trunk/src/target/u-boot/patches/uboot-s3c2443.patch 2007-08-27 00:27:06 UTC
(rev 2833)
+++ trunk/src/target/u-boot/patches/uboot-s3c2443.patch 2007-08-27 12:25:11 UTC
(rev 2834)
@@ -4,40 +4,41 @@
+++ u-boot/cpu/arm920t/start.S
@@ -35,6 +35,8 @@
#include <s3c2410.h>
- #elif defined(CONFIG_S3C2440)
+ #elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
#include <s3c2440.h>
+#elif defined(CONFIG_S3C2443)
+#include <s3c2443.h>
#endif
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) ||
defined(CONFIG_AT91RM9200DF)
#include <led.h>
-@@ -234,9 +236,15 @@
- #endif
+@@ -245,10 +247,15 @@
+ # endif
# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
# define CAMDIVN 0x4C000018
+#elif defined(CONFIG_S3C2443)
+# define INTSUBMSK_val 0x1fffffff
-+# define EPLLCON_val ((40 << 16) | (1 << 8) | (1)) /* 96 MHz */
-+# define MPLLCON_val ((81 << 16) | (2 << 8) | (0)) /* 1068 MHz */
-+# define CLKDIV0_val ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2)
++# define EPLLCON_val ((40 << 16) | (1 << 8) | (1)) /* 96 MHz */
++# define MPLLCON_val ((81 << 16) | (2 << 8) | (0)) /* 1068 MHz */
++# define CLKDIV0_val ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2)
#endif
--#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440)
-+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
-+ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443)
+ #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ||
defined(CONFIG_S3C2440) || \
+- defined(CONFIG_S3C2442)
++ defined(CONFIG_S3C2442) || defined(CONFIG_S3c2443)
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
-@@ -247,7 +255,7 @@
+@@ -259,7 +266,8 @@
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
--# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
-+# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ||
defined(CONFIG_S3C2443)
+-# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ||
defined(CONFIG_S3C2442)
++# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ||
defined(CONFIG_S3C2442) || \
++ defined(CONFIG_S3C2443)
ldr r1, =INTSUBMSK_val
ldr r0, =INTSUBMSK
str r1, [r0]
-@@ -266,6 +274,43 @@
+@@ -278,6 +286,43 @@
mcr p15, 0, r1, c1, c0, 0
@@ -81,7 +82,7 @@
#define LOCKTIME 0x4c000000
#define UPLLCON 0x4c000008
-@@ -293,6 +338,7 @@
+@@ -305,6 +350,7 @@
ldr r0, =CLKDIVN
mov r1, #CLKDIVN_val
str r1, [r0]
@@ -89,12 +90,13 @@
#if 1
/* enable uart */
-@@ -319,7 +365,7 @@
+@@ -331,7 +377,8 @@
str r1, [r0, #0x28]
#endif
--#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */
-+#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 ||
CONFIG_S3C2443 */
+-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 ||
CONFIG_S3C2442 */
++#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 ||
CONFIG_S3C2442
++ CONFIG_S3C2443 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#ifndef CONFIG_LL_INIT_NAND_ONLY
@@ -102,26 +104,25 @@
===================================================================
--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
+++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
-@@ -31,7 +31,8 @@
-
+@@ -32,7 +32,7 @@
#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
-- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
-+ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443) || \
-+ defined (CONFIG_TRAB)
+ defined(CONFIG_S3C2440) || defined (CONFIG_S3C2442) || \
+- defined (CONFIG_TRAB)
++ defined(CONFIG_S3C2443) || defined (CONFIG_TRAB)
#include <arm920t.h>
#if defined(CONFIG_S3C2400)
-@@ -40,6 +41,8 @@
+@@ -41,6 +41,8 @@
#include <s3c2410.h>
- #elif defined(CONFIG_S3C2440)
+ #elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
#include <s3c2440.h>
+#elif defined(CONFIG_S3C2443)
+#include <s3c2443.h>
#endif
int timer_load_val = 0;
-@@ -186,6 +189,7 @@
+@@ -187,6 +189,7 @@
#elif defined(CONFIG_SBC2410X) || \
defined(CONFIG_SMDK2410) || \
defined(CONFIG_SMDK2440) || \
@@ -133,13 +134,12 @@
===================================================================
--- u-boot.orig/drivers/usbdcore_s3c2410.c
+++ u-boot/drivers/usbdcore_s3c2410.c
-@@ -24,7 +24,8 @@
-
+@@ -25,7 +25,7 @@
#include <config.h>
--#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) &&
defined(CONFIG_USB_DEVICE)
-+#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
-+ defined(CONFIG_S3C2443)) && defined(CONFIG_USB_DEVICE)
+ #if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
+- defined(CONFIG_S3C2442)) && defined(CONFIG_USB_DEVICE)
++ defined(CONFIG_S3C2442) || defined(CONFIG_S3C2443)) &&
defined(CONFIG_USB_DEVICE)
#include <common.h>
--- End Message ---
