commit f89b4a45c33ccb84eab6ec70ca37a5b9e33e5a81
Author: Sepherosa Ziehau <se...@dragonflybsd.org>
Date: Tue Jun 5 23:03:46 2018 +0800
x86_64: Implement x2apic support.
Now LAPIC registers are accessed through MSR at fixed location, instead
of going through MMIO region.
Most noticeable is that ICR operation is greatly simplified, i.e. IPI
sending operation:
- Reserved bits are read as 0; there is no need to read ICR first for
OR with the new values.
- No more pending bit, i.e. ICR write is synchronized; there is no need
to read ICR to test pending bit.
- ICR is 64 bits in x2apic mode, i.e. two 32 bits writes to ICR-low and
ICR-high become one write to ICR.
NOTE:
Though Intel SDM says that wrmsr to LAPIC registers are relaxed, we
don't need to put mfence or sfence before them, especially for sending
IPIs, since the generic IPIQ and the machdep code already uses atomic
operation before doing ICR operation. For the rest of the code, there
really are no needs to add mfence/sfence before rdmsr/wrmsr to LAPIC
registers.
As of this commit, x2apic mode is _not_ enabled by default. It can be
enabled through hw.x2apic_enable tuneable, and a read-only sysctl node
with the same name is available for debugging purpose.
Based on work by ivadasz@.
Summary of changes:
sys/cpu/x86_64/include/specialreg.h | 1 +
sys/platform/pc64/acpica/acpi_madt.c | 44 +++++++++---
sys/platform/pc64/apic/apicreg.h | 28 ++++++++
sys/platform/pc64/apic/lapic.c | 125 ++++++++++++++++++++++++++++++++--
sys/platform/pc64/apic/lapic.h | 24 +++++--
sys/platform/pc64/x86_64/mp_machdep.c | 4 ++
6 files changed, 207 insertions(+), 19 deletions(-)
http://gitweb.dragonflybsd.org/dragonfly.git/commitdiff/f89b4a45c33ccb84eab6ec70ca37a5b9e33e5a81
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