This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 97338b0e28dd649116c3070e6322134c6956f13b
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Fri May 24 09:24:05 2019 -0300
Update B-L072Z-LRWAN1 startup
---
hw/bsp/b-l072z-lrwan1/src/system_stm32l0xx.c | 104 +++++++++++++--------------
1 file changed, 49 insertions(+), 55 deletions(-)
diff --git a/hw/bsp/b-l072z-lrwan1/src/system_stm32l0xx.c
b/hw/bsp/b-l072z-lrwan1/src/system_stm32l0xx.c
index b848154..140fa11 100644
--- a/hw/bsp/b-l072z-lrwan1/src/system_stm32l0xx.c
+++ b/hw/bsp/b-l072z-lrwan1/src/system_stm32l0xx.c
@@ -22,29 +22,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without
modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
notice,
- * this list of conditions and the following disclaimer in the
documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its
contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -65,15 +49,15 @@
#include "mcu/cmsis_nvic.h"
#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External
oscillator in Hz */
+ #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External
oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (MSI_VALUE)
- #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal
oscillator in Hz*/
+ #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal
oscillator in Hz*/
#endif /* MSI_VALUE */
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal
oscillator in Hz*/
+ #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal
oscillator in Hz*/
#endif /* HSI_VALUE */
@@ -97,8 +81,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
@@ -123,10 +107,10 @@
is no need to call the 2 first functions listed above, since
SystemCoreClock
variable is updated automatically.
*/
- uint32_t SystemCoreClock = 2000000;
- const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7,
8, 9};
- const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
- const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+ uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
+ const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U,
3U, 4U, 6U, 7U, 8U, 9U};
+ const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+ const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
/**
* @}
@@ -152,25 +136,25 @@
void SystemInit (void)
{
/*!< Set MSION bit */
- RCC->CR |= (uint32_t)0x00000100;
+ RCC->CR |= (uint32_t)0x00000100U;
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and
MCOPRE[2:0] bits */
- RCC->CFGR &= (uint32_t) 0x88FF400C;
+ RCC->CFGR &= (uint32_t) 0x88FF400CU;
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFF6;
+ RCC->CR &= (uint32_t)0xFEF6FFF6U;
/*!< Reset HSI48ON bit */
- RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
+ RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
/*!< Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
+ RCC->CR &= (uint32_t)0xFFFBFFFFU;
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
- RCC->CFGR &= (uint32_t)0xFF02FFFF;
+ RCC->CFGR &= (uint32_t)0xFF02FFFFU;
/*!< Disable all interrupts */
- RCC->CIER = 0x00000000;
+ RCC->CIER = 0x00000000U;
/* Relocate the vector table */
NVIC_Relocate();
@@ -216,36 +200,50 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
- uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+ uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
/* Get SYSCLK source
-------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
- case 0x00: /* MSI used as system clock */
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
- SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ case 0x00U: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
+ SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
- case 0x04: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
+ case 0x04U: /* HSI used as system clock */
+ if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+ {
+ SystemCoreClock = HSI_VALUE / 4U;
+ }
+ else
+ {
+ SystemCoreClock = HSI_VALUE;
+ }
break;
- case 0x08: /* HSE used as system clock */
+ case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
- case 0x0C: /* PLL used as system clock */
+ default: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor
----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
- pllmul = PLLMulTable[(pllmul >> 18)];
- plldiv = (plldiv >> 22) + 1;
+ pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
+ plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- if (pllsource == 0x00)
+ if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
- SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+ if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+ {
+ SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
+ }
+ else
+ {
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+ }
}
else
{
@@ -253,14 +251,10 @@ void SystemCoreClockUpdate (void)
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
}
break;
- default: /* MSI used as system clock */
- msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
- SystemCoreClock = (32768 * (1 << (msirange + 1)));
- break;
}
/* Compute HCLK clock frequency
--------------------------------------------*/
/* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
