kasjer commented on a change in pull request #2017: P-NUCLEO-WB55 URL: https://github.com/apache/mynewt-core/pull/2017#discussion_r334447957
########## File path: hw/mcu/stm/stm32wbxx/syscfg.yml ########## @@ -0,0 +1,199 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + MCU_FLASH_MIN_WRITE_SIZE: + description: > + Specifies the required alignment for internal flash writes. + Used internally by the newt tool. + value: 8 + + MCU_STM32WB: + description: MCUs are of STM32WBxx family + value: 1 + + STM32_CLOCK_VOLTAGESCALING_CONFIG: + description: Voltage scale + value: 0 + + STM32_CLOCK_LSI1: + description: Enable low-speed internal clock source + value: 0 + + STM32_CLOCK_LSI2: + description: Enable low-speed internal clock source + value: 0 + + STM32_CLOCK_LSI2_CALIBRATION: + description: LSI2 calibration value + value: 0 + + STM32_CLOCK_LSE: + description: Enable low-speed external clock source (aka RTC xtal) + value: 0 + + STM32_CLOCK_LSE_BYPASS: + description: 0 for 32768 xtal; 1 for input clock + value: 0 + + STM32_CLOCK_MSI: + description: Enable multi-speed internal clock source + value: 1 + + STM32_CLOCK_MSI_CALIBRATION: + description: MSI calibration value + value: 'RCC_MSICALIBRATION_DEFAULT' + + STM32_CLOCK_MSI_CLOCK_RANGE: + description: MSI clock range + value: 'RCC_MSICALIBRATION_DEFAULT' + + STM32_CLOCK_HSE: + description: Enable high-speed external clock source + value: 0 + + STM32_CLOCK_HSE_BYPASS: + description: 0 for xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSEPRE: + description: Enable HSE prescaler divider + value: 0 + + STM32_CLOCK_HSI: + description: Enable high-speed internal clock source + value: 1 + + STM32_CLOCK_HSI_CALIBRATION: + description: HSI calibration value + value: 'RCC_HSICALIBRATION_DEFAULT' + + STM32_CLOCK_HSI48: + description: Enable high-speed 48MHz internal clock source + value: 0 + + STM32_CLOCK_PLL_PLLM: + description: PLL config M parameter + value: 0 + + STM32_CLOCK_PLL_PLLN: + description: PLL config N parameter + value: 0 + + STM32_CLOCK_PLL_PLLP: + description: PLL config P parameter + value: 0 + + STM32_CLOCK_PLL_PLLQ: + description: PLL config Q parameter + value: 0 + + STM32_CLOCK_PLL_PLLR: + description: PLL config R parameter + value: 0 + + STM32_CLOCK_AHB_DIVIDER: + description: AHB CLK1 prescaler (64MHz max) + value: 0 + + STM32_CLOCK_APB1_DIVIDER: + description: APB low-speed prescaler (64MHz max) + value: 0 + + STM32_CLOCK_APB2_DIVIDER: + description: APB high-speed prescaler (64MHz max) + value: 0 + + STM32_CLOCK_AHBCLK2_DIVIDER: + description: AHB CLK2 prescaler (32MHz max) + value: 0 + + STM32_CLOCK_AHBCLK4_DIVIDER: + description: AHB CLK4 prescaler (64MHz max) + value: 0 + + STM32_FLASH_LATENCY: + description: Number of wait-states + value: 0 + + STM32_FLASH_PREFETCH_ENABLE: + description: Enable pre-fetch of instructions (when latency > 0) + value: 0 + + STM32_INSTRUCTION_CACHE_ENABLE: + description: Enable flash instruction cache + value: 0 + + STM32_DATA_CACHE_ENABLE: + description: Enable flash data cache + value: 0 + + STM32_HAL_SPI_HAS_FIFO: + description: This MCU has a SPI with FIFO + value: 1 + + STM32_HAL_I2C_HAS_CLOCKSPEED: + description: This MCU's I2C has no clock speed register (has TIMINGR) + value: 0 + + STM32_HAL_UART_HAS_SR: + description: This MCU's UART uses ISR register (not SR) for status. + value: 0 + + MCU_FLASH_ERASED_VAL: + description: Value read from erased flash. + value: 0xff + + STM32_FLASH_IS_LINEAR: + description: This MCU's Flash has one single sector size. + value: 1 + + STM32_FLASH_SECTOR_SIZE: + description: This MCU's Flash sector size in bytes. + value: 4096 + + I2C_0: + description: 'I2C (TWI) interface I2C1' + value: 0 + + I2C_0_PIN_SCL: + description: 'SCL pin for I2C1, PB6, PB8, PG14' + value: MCU_GPIO_PORTB(8) + + I2C_0_PIN_SDA: + description: 'SDA pin for I2C1, PB7, PB9, PG13' + value: MCU_GPIO_PORTB(9) + + SPI_0_MASTER: + description: 'SPI 0 master' + value: 0 + restrictions: + - "!SPI_0_SLAVE" + SPI_0_SLAVE: + description: 'SPI 0 slave' + value: 0 + restrictions: + - "!SPI_0_MASTER" + + TRNG: + description: 'True Random Number Generator (RNG)' Review comment: maybe **enable** word here? like in CRYPTO case ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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