apache-mynewt-bot commented on pull request #2466: URL: https://github.com/apache/mynewt-core/pull/2466#issuecomment-773577569
<!-- style-bot --> ## Style check summary ### Our coding style is [here!](https://github.com/apache/mynewt-core/blob/master/CODING_STANDARDS.md) #### hw/mcu/nxp/kinetis/MK64F12/src/fsl_clock.c <details> ```diff @@ -187,15 +187,15 @@ ******************************************************************************/ #ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN -static void CLOCK_FllStableDelay(void) +static void +CLOCK_FllStableDelay(void) { /* Should wait at least 1ms. Because in these modes, the core clock is 100MHz at most, so this function could obtain the 1ms delay. */ volatile uint32_t i = 30000U; - while (0U != (i--)) - { + while (0U != (i--)) { __NOP(); } } @@ -207,34 +207,35 @@ extern void CLOCK_FllStableDelay(void); #endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */ -static uint32_t CLOCK_GetMcgExtClkFreq(void) +static uint32_t +CLOCK_GetMcgExtClkFreq(void) { uint32_t freq; - switch (MCG_C7_OSCSEL_VAL) - { - case 0U: - /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ - assert(0U != g_xtal0Freq); - freq = g_xtal0Freq; - break; - case 1U: - /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ - assert(0U != g_xtal32Freq); - freq = g_xtal32Freq; - break; - case 2U: - freq = MCG_INTERNAL_IRC_48M; - break; - default: - freq = 0U; - break; + switch (MCG_C7_OSCSEL_VAL) { + case 0U: + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(0U != g_xtal0Freq); + freq = g_xtal0Freq; + break; + case 1U: + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(0U != g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 2U: + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; } return freq; } -static uint32_t CLOCK_GetFllExtRefClkFreq(void) +static uint32_t +CLOCK_GetFllExtRefClkFreq(void) { /* FllExtRef = McgExtRef / FllExtRefDiv */ uint8_t frdiv; @@ -246,54 +247,50 @@ frdiv = MCG_C1_FRDIV_VAL; freq >>= frdiv; - range = MCG_C2_RANGE_VAL; + range = MCG_C2_RANGE_VAL; oscsel = MCG_C7_OSCSEL_VAL; /* When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. 1. MCG_C7[OSCSEL] selects IRC48M. 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. - */ - if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) - { - switch (frdiv) - { - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - freq >>= 5u; - break; - case 6: - /* 64*20=1280 */ - freq /= 20u; - break; - case 7: - /* 128*12=1536 */ - freq /= 12u; - break; - default: - freq = 0u; - break; + */ + if (((0U != range) && ((uint8_t)kMCG_OscselOsc == oscsel)) || ((uint8_t)kMCG_OscselIrc == oscsel)) { + switch (frdiv) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + freq >>= 5u; + break; + case 6: + /* 64*20=1280 */ + freq /= 20u; + break; + case 7: + /* 128*12=1536 */ + freq /= 12u; + break; + default: + freq = 0u; + break; } } return freq; } -static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) +static uint32_t +CLOCK_GetInternalRefClkSelectFreq(void) { uint32_t freq; - if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) - { + if ((uint8_t)kMCG_IrcSlow == MCG_S_IRCST_VAL) { /* Slow internal reference clock selected*/ freq = s_slowIrcFreq; - } - else - { + } else { /* Fast internal reference clock selected*/ freq = s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; } @@ -301,44 +298,40 @@ return freq; } -static uint32_t CLOCK_GetFllRefClkFreq(void) +static uint32_t +CLOCK_GetFllRefClkFreq(void) { uint32_t freq; /* If use external reference clock. */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { + if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) { freq = CLOCK_GetFllExtRefClkFreq(); } /* If use internal reference clock. */ - else - { + else { freq = s_slowIrcFreq; } return freq; } -static uint32_t CLOCK_GetPll0RefFreq(void) +static uint32_t +CLOCK_GetPll0RefFreq(void) { /* MCG external reference clock. */ return CLOCK_GetMcgExtClkFreq(); } -static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) +static uint8_t +CLOCK_GetOscRangeFromFreq(uint32_t freq) { uint8_t range; - if (freq <= 39063U) - { + if (freq <= 39063U) { range = 0U; - } - else if (freq <= 8000000U) - { + } else if (freq <= 8000000U) { range = 1U; - } - else - { + } else { range = 2U; } @@ -350,17 +343,15 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetOsc0ErClkFreq(void) +uint32_t +CLOCK_GetOsc0ErClkFreq(void) { uint32_t freq; - if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) - { + if ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U) { /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ assert(g_xtal0Freq); freq = g_xtal0Freq; - } - else - { + } else { freq = 0U; } @@ -372,26 +363,26 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetEr32kClkFreq(void) +uint32_t +CLOCK_GetEr32kClkFreq(void) { uint32_t freq; - switch (SIM_SOPT1_OSC32KSEL_VAL) - { - case 0U: /* OSC 32k clock */ - freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; - break; - case 2U: /* RTC 32k clock */ - /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ - assert(g_xtal32Freq); - freq = g_xtal32Freq; - break; - case 3U: /* LPO clock */ - freq = LPO_CLK_FREQ; - break; - default: - freq = 0U; - break; + switch (SIM_SOPT1_OSC32KSEL_VAL) { + case 0U: /* OSC 32k clock */ + freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; + break; + case 2U: /* RTC 32k clock */ + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 3U: /* LPO clock */ + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; } return freq; } @@ -401,24 +392,24 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetPllFllSelClkFreq(void) +uint32_t +CLOCK_GetPllFllSelClkFreq(void) { uint32_t freq; - switch (SIM_SOPT2_PLLFLLSEL_VAL) - { - case 0U: /* FLL. */ - freq = CLOCK_GetFllFreq(); - break; - case 1U: /* PLL. */ - freq = CLOCK_GetPll0Freq(); - break; - case 3U: /* MCG IRC48M. */ - freq = MCG_INTERNAL_IRC_48M; - break; - default: - freq = 0U; - break; + switch (SIM_SOPT2_PLLFLLSEL_VAL) { + case 0U: /* FLL. */ + freq = CLOCK_GetFllFreq(); + break; + case 1U: /* PLL. */ + freq = CLOCK_GetPll0Freq(); + break; + case 3U: /* MCG IRC48M. */ + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; } return freq; @@ -429,7 +420,8 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetPlatClkFreq(void) +uint32_t +CLOCK_GetPlatClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL); } @@ -439,7 +431,8 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetFlashClkFreq(void) +uint32_t +CLOCK_GetFlashClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL); } @@ -449,7 +442,8 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetFlexBusClkFreq(void) +uint32_t +CLOCK_GetFlexBusClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL); } @@ -459,7 +453,8 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetBusClkFreq(void) +uint32_t +CLOCK_GetBusClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL); } @@ -469,7 +464,8 @@ * * return Clock frequency in Hz. */ -uint32_t CLOCK_GetCoreSysClkFreq(void) +uint32_t +CLOCK_GetCoreSysClkFreq(void) { return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL); } @@ -484,55 +480,55 @@ * param clockName Clock names defined in clock_name_t * return Clock frequency value in Hertz */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) +uint32_t +CLOCK_GetFreq(clock_name_t clockName) { uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - case kCLOCK_PlatClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL); - break; - case kCLOCK_FlexBusClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL); - break; - case kCLOCK_FlashClk: - freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL); - break; - case kCLOCK_PllFllSelClk: - freq = CLOCK_GetPllFllSelClkFreq(); - break; - case kCLOCK_Er32kClk: - freq = CLOCK_GetEr32kClkFreq(); - break; - case kCLOCK_Osc0ErClk: - freq = CLOCK_GetOsc0ErClkFreq(); - break; - case kCLOCK_McgFixedFreqClk: - freq = CLOCK_GetFixedFreqClkFreq(); - break; - case kCLOCK_McgInternalRefClk: - freq = CLOCK_GetInternalRefClkFreq(); - break; - case kCLOCK_McgFllClk: - freq = CLOCK_GetFllFreq(); - break; - case kCLOCK_McgPll0Clk: - freq = CLOCK_GetPll0Freq(); - break; - case kCLOCK_McgIrc48MClk: - freq = MCG_INTERNAL_IRC_48M; - break; - case kCLOCK_LpoClk: - freq = LPO_CLK_FREQ; - break; - default: - freq = 0U; - break; + switch (clockName) { + case kCLOCK_CoreSysClk: + case kCLOCK_PlatClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1UL); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1UL); + break; + case kCLOCK_FlexBusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1UL); + break; + case kCLOCK_FlashClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1UL); + break; + case kCLOCK_PllFllSelClk: + freq = CLOCK_GetPllFllSelClkFreq(); + break; + case kCLOCK_Er32kClk: + freq = CLOCK_GetEr32kClkFreq(); + break; + case kCLOCK_Osc0ErClk: + freq = CLOCK_GetOsc0ErClkFreq(); + break; + case kCLOCK_McgFixedFreqClk: + freq = CLOCK_GetFixedFreqClkFreq(); + break; + case kCLOCK_McgInternalRefClk: + freq = CLOCK_GetInternalRefClkFreq(); + break; + case kCLOCK_McgFllClk: + freq = CLOCK_GetFllFreq(); + break; + case kCLOCK_McgPll0Clk: + freq = CLOCK_GetPll0Freq(); + break; + case kCLOCK_McgIrc48MClk: + freq = MCG_INTERNAL_IRC_48M; + break; + case kCLOCK_LpoClk: + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; } return freq; @@ -545,7 +541,8 @@ * * param config Pointer to the configure structure. */ -void CLOCK_SetSimConfig(sim_clock_config_t const *config) +void +CLOCK_SetSimConfig(sim_clock_config_t const *config) { SIM->CLKDIV1 = config->clkdiv1; CLOCK_SetPllFllSelClock(config->pllFllSel); @@ -559,35 +556,32 @@ * retval true The clock is set successfully. * retval false The clock source is invalid to get proper USB FS clock. */ -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +bool +CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) { bool ret = true; CLOCK_DisableClock(kCLOCK_Usbfs0); - if (kCLOCK_UsbSrcExt == src) - { + if (kCLOCK_UsbSrcExt == src) { SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; - } - else - { - switch (freq) - { - case 120000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); - break; - case 96000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); - break; - case 72000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); - break; - case 48000000U: - SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); - break; - default: - ret = false; - break; + } else { + switch (freq) { + case 120000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); + break; + case 96000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); + break; + case 72000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); + break; + case 48000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); + break; + default: + ret = false; + break; } SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); @@ -595,8 +589,7 @@ CLOCK_EnableClock(kCLOCK_Usbfs0); - if (kCLOCK_UsbSrcIrc48M == src) - { + if (kCLOCK_UsbSrcIrc48M == src) { USB0->CLK_RECOVER_IRC_EN = 0x03U; USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; } @@ -611,28 +604,28 @@ * * return The frequency of MCGOUTCLK. */ -uint32_t CLOCK_GetOutClkFreq(void) +uint32_t +CLOCK_GetOutClkFreq(void) { uint32_t mcgoutclk; uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL; - switch (clkst) - { - case (uint32_t)kMCG_ClkOutStatPll: - mcgoutclk = CLOCK_GetPll0Freq(); - break; - case (uint32_t)kMCG_ClkOutStatFll: - mcgoutclk = CLOCK_GetFllFreq(); - break; - case (uint32_t)kMCG_ClkOutStatInt: - mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); - break; - case (uint32_t)kMCG_ClkOutStatExt: - mcgoutclk = CLOCK_GetMcgExtClkFreq(); - break; - default: - mcgoutclk = 0U; - break; + switch (clkst) { + case (uint32_t)kMCG_ClkOutStatPll: + mcgoutclk = CLOCK_GetPll0Freq(); + break; + case (uint32_t)kMCG_ClkOutStatFll: + mcgoutclk = CLOCK_GetFllFreq(); + break; + case (uint32_t)kMCG_ClkOutStatInt: + mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); + break; + case (uint32_t)kMCG_ClkOutStatExt: + mcgoutclk = CLOCK_GetMcgExtClkFreq(); + break; + default: + mcgoutclk = 0U; + break; } return mcgoutclk; @@ -647,7 +640,8 @@ * * return The frequency of MCGFLLCLK. */ -uint32_t CLOCK_GetFllFreq(void) +uint32_t +CLOCK_GetFllFreq(void) { static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; @@ -656,23 +650,17 @@ uint32_t ret; /* If FLL is not enabled currently, then return 0U. */ - if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) - { + if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) { ret = 0U; - } - else - { + } else { /* Get FLL reference clock frequency. */ freq = CLOCK_GetFllRefClkFreq(); - if (0U == freq) - { + if (0U == freq) { ret = freq; - } - else - { - drs = MCG_C4_DRST_DRS_VAL; + } else { + drs = MCG_C4_DRST_DRS_VAL; dmx32 = MCG_C4_DMX32_VAL; - ret = freq * fllFactorTable[drs][dmx32]; + ret = freq * fllFactorTable[drs][dmx32]; } } @@ -687,17 +675,15 @@ * * return The frequency of MCGIRCLK. */ -uint32_t CLOCK_GetInternalRefClkFreq(void) +uint32_t +CLOCK_GetInternalRefClkFreq(void) { uint32_t freq; /* If MCGIRCLK is gated. */ - if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) - { + if (0U == (MCG->C1 & MCG_C1_IRCLKEN_MASK)) { freq = 0U; - } - else - { + } else { freq = CLOCK_GetInternalRefClkSelectFreq(); } @@ -712,18 +698,16 @@ * * return The frequency of MCGFFCLK. */ -uint32_t CLOCK_GetFixedFreqClkFreq(void) +uint32_t +CLOCK_GetFixedFreqClkFreq(void) { uint32_t freq = CLOCK_GetFllRefClkFreq(); uint32_t ret; /* MCGFFCLK must be no more than MCGOUTCLK/8. */ - if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) - { + if ((freq <= (CLOCK_GetOutClkFreq() / 8U)) && (0U != freq)) { ret = freq; - } - else - { + } else { ret = 0U; } @@ -738,7 +722,8 @@ * * return The frequency of MCGPLL0CLK. */ -uint32_t CLOCK_GetPll0Freq(void) +uint32_t +CLOCK_GetPll0Freq(void) { uint32_t mcgpll0clk; uint32_t freq; @@ -746,12 +731,9 @@ uint8_t mcgpll0prdiv; uint8_t mcgpll0vdiv; /* If PLL0 is not enabled, return 0. */ - if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) - { + if (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) { freq = 0U; - } - else - { + } else { mcgpll0clk = CLOCK_GetPll0RefFreq(); /* @@ -783,36 +765,31 @@ * the configuration should not be changed. Otherwise, a glitch occurs. * retval kStatus_Success External reference clock set successfully. */ -status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) +status_t +CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) { bool needDelay; uint32_t i; #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ - if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) - { + if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) { return kStatus_MCG_SourceUsed; } #endif /* MCG_CONFIG_CHECK_PARAM */ - if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) - { + if (MCG_C7_OSCSEL_VAL != (uint8_t)oscsel) { /* If change OSCSEL, need to delay, ERR009878. */ needDelay = true; - } - else - { + } else { needDelay = false; } MCG->C7 = (uint8_t)(MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); - if (needDelay) - { + if (needDelay) { /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ i = 1500U; - while (0U != (i--)) - { + while (0U != (i--)) { __NOP(); } } @@ -836,34 +813,30 @@ * the configuration should not be changed. Otherwise, a glitch occurs. * retval kStatus_Success MCGIRCLK configuration finished successfully. */ -status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) +status_t +CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) { uint32_t mcgOutClkState = (uint32_t)MCG_S_CLKST_VAL; - mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL); - uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; + mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)((uint32_t)MCG_S_IRCST_VAL); + uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) /* If MCGIRCLK is used as system clock source. */ - if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) - { + if ((uint32_t)kMCG_ClkOutStatInt == mcgOutClkState) { /* If need to change MCGIRCLK source or driver, return error. */ - if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) - { + if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) { return kStatus_MCG_SourceUsed; } } #endif /* If need to update the FCRDIV. */ - if (fcrdiv != curFcrdiv) - { + if (fcrdiv != curFcrdiv) { /* If fast IRC is in use currently, change to slow IRC. */ if (((0U != (MCG->C1 & MCG_C1_IRCLKEN_MASK)) || (mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt)) && - (kMCG_IrcFast == curIrcs)) - { + (kMCG_IrcFast == curIrcs)) { MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); - while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) - { + while (MCG_S_IRCST_VAL != (uint8_t)kMCG_IrcSlow) { } } /* Update FCRDIV. */ @@ -876,10 +849,8 @@ MCG->C1 = (uint8_t)((MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode); /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ - if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) - { - while (MCG_S_IRCST_VAL != (uint8_t)ircs) - { + if ((mcgOutClkState == (uint32_t)kMCG_ClkOutStatInt) || (0U != (enableMode & (uint32_t)kMCG_IrclkEnable))) { + while (MCG_S_IRCST_VAL != (uint8_t)ircs) { } } @@ -901,7 +872,8 @@ * param vdiv VDIV value to generate desired PLL frequency. * return Closest frequency match that the PLL was able generate. */ -uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) +uint32_t +CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) { uint8_t ret_prdiv; /* PRDIV to return. */ uint8_t ret_vdiv; /* VDIV to return. */ @@ -910,7 +882,7 @@ uint8_t prdiv_cur; /* PRDIV value for iteration. */ uint8_t vdiv_cur; /* VDIV value for iteration. */ uint32_t ret_freq = 0U; /* PLL output frequency to return. */ - uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ + uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ uint32_t ref_div; /* Reference frequency after PRDIV. */ /* @@ -929,8 +901,7 @@ /* Reference frequency is out of range. */ if ((refFreq < (uint32_t)FSL_FEATURE_MCG_PLL_REF_MIN) || (refFreq > ((uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX * - ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) - { + ((uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_MAX + (uint32_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) { return 0U; } @@ -940,62 +911,52 @@ (uint8_t)((refFreq + (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / (uint32_t)FSL_FEATURE_MCG_PLL_REF_MAX); /* PRDIV traversal. */ - for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) - { + for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) { /* Reference frequency after PRDIV. */ ref_div = refFreq / prdiv_cur; vdiv_cur = (uint8_t)(desireFreq / ref_div); if ((vdiv_cur < ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U)) || - (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) - { + (vdiv_cur > (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) { /* No VDIV is available with this PRDIV. */ continue; } ret_freq = vdiv_cur * ref_div; - if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) - { - if (ret_freq == desireFreq) /* If desire frequency is got. */ - { + if (vdiv_cur >= (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE) { + if (ret_freq == desireFreq) { /* If desire frequency is got. */ *prdiv = prdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE; - *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; + *vdiv = vdiv_cur - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; return ret_freq; } /* New PRDIV/VDIV is closer. */ - if (diff > desireFreq - ret_freq) - { - diff = desireFreq - ret_freq; + if (diff > desireFreq - ret_freq) { + diff = desireFreq - ret_freq; ret_prdiv = prdiv_cur; - ret_vdiv = vdiv_cur; + ret_vdiv = vdiv_cur; } } vdiv_cur++; - if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) - { + if (vdiv_cur <= ((uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) { ret_freq += ref_div; /* New PRDIV/VDIV is closer. */ - if (diff > ret_freq - desireFreq) - { - diff = ret_freq - desireFreq; + if (diff > ret_freq - desireFreq) { + diff = ret_freq - desireFreq; ret_prdiv = prdiv_cur; - ret_vdiv = vdiv_cur; + ret_vdiv = vdiv_cur; } } } - if (0xFFFFFFFFU != diff) - { + if (0xFFFFFFFFU != diff) { /* PRDIV/VDIV found. */ - *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE; - *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; + *prdiv = ret_prdiv - (uint8_t)FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = ret_vdiv - (uint8_t)FSL_FEATURE_MCG_PLL_VDIV_BASE; ret_freq = (refFreq / ret_prdiv) * ret_vdiv; return ret_freq; - } - else - { + } else { /* No proper PRDIV/VDIV found. */ return 0U; } @@ -1012,7 +973,8 @@ * * param config Pointer to the configuration structure. */ -void CLOCK_EnablePll0(mcg_pll_config_t const *config) +void +CLOCK_EnablePll0(mcg_pll_config_t const *config) { assert(config); @@ -1027,8 +989,7 @@ MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); /* Wait for PLL lock. */ - while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) - { + while (((MCG->S & MCG_S_LOCK0_MASK)) == 0U) { } } @@ -1039,23 +1000,18 @@ * * param mode Monitor mode to set. */ -void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) +void +CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) { /* Clear the previous flag, MCG_SC[LOCS0]. */ MCG->SC &= ~(uint8_t)MCG_SC_ATMF_MASK; - if (kMCG_MonitorNone == mode) - { + if (kMCG_MonitorNone == mode) { MCG->C6 &= ~(uint8_t)MCG_C6_CME0_MASK; - } - else - { - if (kMCG_MonitorInt == mode) - { + } else { + if (kMCG_MonitorInt == mode) { MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; - } - else - { + } else { MCG->C2 |= MCG_C2_LOCRE0_MASK; } MCG->C6 |= MCG_C6_CME0_MASK; @@ -1069,16 +1025,15 @@ * * param mode Monitor mode to set. */ -void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) +void +CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) { uint8_t mcg_c8 = MCG->C8; mcg_c8 &= ~(uint8_t)(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); - if (kMCG_MonitorNone != mode) - { - if (kMCG_MonitorReset == mode) - { + if (kMCG_MonitorNone != mode) { + if (kMCG_MonitorReset == mode) { mcg_c8 |= MCG_C8_LOCRE1_MASK; } mcg_c8 |= MCG_C8_CME1_MASK; @@ -1093,29 +1048,24 @@ * * param mode Monitor mode to set. */ -void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) +void +CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) { uint8_t mcg_c8; /* Clear previous flag. */ MCG->S = MCG_S_LOLS0_MASK; - if (kMCG_MonitorNone == mode) - { + if (kMCG_MonitorNone == mode) { MCG->C6 &= (uint8_t)(~MCG_C6_LOLIE0_MASK); - } - else - { + } else { mcg_c8 = MCG->C8; mcg_c8 &= (uint8_t)(~MCG_C8_LOCS1_MASK); - if (kMCG_MonitorInt == mode) - { + if (kMCG_MonitorInt == mode) { mcg_c8 &= (uint8_t)(~MCG_C8_LOLRE_MASK); - } - else - { + } else { mcg_c8 |= MCG_C8_LOLRE_MASK; } MCG->C8 = mcg_c8; @@ -1149,29 +1099,25 @@ * * return Logical OR value of the ref _mcg_status_flags_t. */ -uint32_t CLOCK_GetStatusFlags(void) -{ - uint32_t ret = 0U; +uint32_t +CLOCK_GetStatusFlags(void) +{ + uint32_t ret = 0U; uint8_t mcg_s = MCG->S; - if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) - { + if ((MCG->SC & MCG_SC_LOCS0_MASK) != 0U) { ret |= (uint32_t)kMCG_Osc0LostFlag; } - if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) - { + if ((mcg_s & MCG_S_OSCINIT0_MASK) != 0U) { ret |= (uint32_t)kMCG_Osc0InitFlag; } - if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) - { + if (0U != (MCG->C8 & MCG_C8_LOCS1_MASK)) { ret |= (uint32_t)kMCG_RtcOscLostFlag; } - if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) - { + if ((mcg_s & MCG_S_LOLS0_MASK) != 0U) { ret |= (uint32_t)kMCG_Pll0LostFlag; } - if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) - { + if ((mcg_s & MCG_S_LOCK0_MASK) != 0U) { ret |= (uint32_t)kMCG_Pll0LockFlag; } return ret; @@ -1193,21 +1139,19 @@ * param mask The status flags to clear. This is a logical OR of members of the * enumeration ref _mcg_status_flags_t. */ -void CLOCK_ClearStatusFlags(uint32_t mask) +void +CLOCK_ClearStatusFlags(uint32_t mask) { uint8_t reg; - if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) - { + if ((mask & (uint32_t)kMCG_Osc0LostFlag) != 0UL) { MCG->SC &= (uint8_t)(~MCG_SC_ATMF_MASK); } - if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) - { - reg = MCG->C8; + if (0U != (mask & (uint32_t)kMCG_RtcOscLostFlag)) { + reg = MCG->C8; MCG->C8 = reg; } - if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) - { + if ((mask & (uint32_t)kMCG_Pll0LostFlag) != 0UL) { MCG->S = MCG_S_LOLS0_MASK; } } @@ -1219,7 +1163,8 @@ * * param config Pointer to the OSC0 configuration structure. */ -void CLOCK_InitOsc0(osc_config_t const *config) +void +CLOCK_InitOsc0(osc_config_t const *config) { uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); @@ -1228,11 +1173,9 @@ MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); - if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) - { + if ((kOSC_ModeExt != config->workMode) && ((OSC0->CR & OSC_CR_ERCLKEN_MASK) != 0U)) { /* Wait for stable. */ - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { + while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) { } } } @@ -1242,7 +1185,8 @@ * * This function deinitializes the OSC0. */ -void CLOCK_DeinitOsc0(void) +void +CLOCK_DeinitOsc0(void) { OSC0->CR = 0U; MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; @@ -1253,7 +1197,8 @@ * * param freq The Slow IRC frequency input clock frequency in Hz. */ -void CLOCK_SetSlowIrcFreq(uint32_t freq) +void +CLOCK_SetSlowIrcFreq(uint32_t freq) { s_slowIrcFreq = freq; } @@ -1263,7 +1208,8 @@ * * param freq The Fast IRC frequency input clock frequency in Hz. */ -void CLOCK_SetFastIrcFreq(uint32_t freq) +void +CLOCK_SetFastIrcFreq(uint32_t freq) { s_fastIrcFreq = freq; } @@ -1286,7 +1232,8 @@ * retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. * retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. */ -status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) +status_t +CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) { uint32_t multi; /* extFreq / desireFreq */ uint32_t actv; /* Auto trim value. */ @@ -1299,30 +1246,24 @@ {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ }; - if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) - { + if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) { status = kStatus_MCG_AtmBusClockInvalid; } /* Check desired frequency range. */ - else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) - { + else if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) { status = kStatus_MCG_AtmDesiredFreqInvalid; } /* Make sure internal reference clock is not used to generate bus clock. Here only need to check (MCG_S_IREFST == 1). */ - else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) - { + else if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) { status = kStatus_MCG_AtmIrcUsed; - } - else - { + } else { multi = extFreq / desireFreq; - actv = multi * 21U; - - if (kMCG_AtmSel4m == atms) - { + actv = multi * 21U; + + if (kMCG_AtmSel4m == atms) { actv *= 128U; } @@ -1336,27 +1277,20 @@ MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); /* Wait for MCG finished. */ - while (0U != (MCG->SC & MCG_SC_ATME_MASK)) - { + while (0U != (MCG->SC & MCG_SC_ATME_MASK)) { } /* Error occurs? */ - if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) - { + if (0U != (MCG->SC & MCG_SC_ATMF_MASK)) { /* Clear the failed flag. */ MCG->SC = mcg_sc; - status = kStatus_MCG_AtmHardwareFail; - } - else - { + status = kStatus_MCG_AtmHardwareFail; + } else { *actualFreq = extFreq / multi; - if (kMCG_AtmSel4m == atms) - { + if (kMCG_AtmSel4m == atms) { s_fastIrcFreq = *actualFreq; - } - else - { + } else { s_slowIrcFreq = *actualFreq; } } @@ -1372,103 +1306,83 @@ * * return Current MCG mode or error code; See ref mcg_mode_t. */ -mcg_mode_t CLOCK_GetMode(void) +mcg_mode_t +CLOCK_GetMode(void) { mcg_mode_t mode = kMCG_ModeError; - uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL; + uint32_t clkst = (uint32_t)MCG_S_CLKST_VAL; uint32_t irefst = (uint32_t)MCG_S_IREFST_VAL; - uint32_t lp = (uint32_t)MCG_C2_LP_VAL; - uint32_t pllst = MCG_S_PLLST_VAL; + uint32_t lp = (uint32_t)MCG_C2_LP_VAL; + uint32_t pllst = MCG_S_PLLST_VAL; /*------------------------------------------------------------------ Mode and Registers - ____________________________________________________________________ - - Mode | CLKST | IREFST | PLLST | LP - ____________________________________________________________________ - - FEI | 00(FLL) | 1(INT) | 0(FLL) | X - ____________________________________________________________________ - - FEE | 00(FLL) | 0(EXT) | 0(FLL) | X - ____________________________________________________________________ - - FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) - ____________________________________________________________________ - - FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) - ____________________________________________________________________ - - BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) - ____________________________________________________________________ - - BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) - ____________________________________________________________________ - - PEE | 11(PLL) | 0(EXT) | 1(PLL) | X - ____________________________________________________________________ - - PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) - ____________________________________________________________________ - - PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) - ____________________________________________________________________ - - PEI | 11(PLL) | 1(INT) | 1(PLL) | X - ____________________________________________________________________ - - ----------------------------------------------------------------------*/ - - if (clkst == (uint32_t)kMCG_ClkOutStatFll) - { - if ((uint32_t)kMCG_FllSrcExternal == irefst) - { + ____________________________________________________________________ + + Mode | CLKST | IREFST | PLLST | LP + ____________________________________________________________________ + + FEI | 00(FLL) | 1(INT) | 0(FLL) | X + ____________________________________________________________________ + + FEE | 00(FLL) | 0(EXT) | 0(FLL) | X + ____________________________________________________________________ + + FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) + ____________________________________________________________________ + + BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) + ____________________________________________________________________ + + PEE | 11(PLL) | 0(EXT) | 1(PLL) | X + ____________________________________________________________________ + + PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) + ____________________________________________________________________ + + PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) + ____________________________________________________________________ + + PEI | 11(PLL) | 1(INT) | 1(PLL) | X + ____________________________________________________________________ + + ----------------------------------------------------------------------*/ + + if (clkst == (uint32_t)kMCG_ClkOutStatFll) { + if ((uint32_t)kMCG_FllSrcExternal == irefst) { mode = kMCG_ModeFEE; - } - else - { + } else { mode = kMCG_ModeFEI; } - } - else if (clkst == (uint32_t)kMCG_ClkOutStatInt) - { - if (0U != lp) - { + } else if (clkst == (uint32_t)kMCG_ClkOutStatInt) { + if (0U != lp) { mode = kMCG_ModeBLPI; - } - else - { + } else { { mode = kMCG_ModeFBI; } } - } - else if (clkst == (uint32_t)kMCG_ClkOutStatExt) - { - if (0U != lp) - { + } else if (clkst == (uint32_t)kMCG_ClkOutStatExt) { + if (0U != lp) { mode = kMCG_ModeBLPE; - } - else - { - if ((uint32_t)kMCG_PllstPll == pllst) - { + } else { + if ((uint32_t)kMCG_PllstPll == pllst) { mode = kMCG_ModePBE; - } - else - { + } else { mode = kMCG_ModeFBE; } } - } - else if (clkst == (uint32_t)kMCG_ClkOutStatPll) - { + } else if (clkst == (uint32_t)kMCG_ClkOutStatPll) { { mode = kMCG_ModePEE; } - } - else - { + } else { /*do nothing*/ } @@ -1490,15 +1404,15 @@ * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed * to a frequency above 32768 Hz. */ -status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +status_t +CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; bool change_drs = false; #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) - { + if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) { return kStatus_MCG_ModeUnreachable; } #endif @@ -1510,8 +1424,7 @@ reference clock source changes, then reset to previous value after reference clock changes. */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { + if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) { change_drs = true; /* Change the LSB of DRST_DRS. */ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); @@ -1523,13 +1436,11 @@ | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ /* Wait and check status. */ - while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) - { + while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) { } /* Errata: ERR007993 */ - if (change_drs) - { + if (change_drs) { MCG->C4 = mcg_c4; } @@ -1538,13 +1449,11 @@ (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); /* Check MCG_S[CLKST] */ - while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) - { + while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) { } /* Wait for FLL stable time. */ - if (NULL != fllStableDelay) - { + if (NULL != fllStableDelay) { fllStableDelay(); } @@ -1566,15 +1475,15 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +status_t +CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; bool change_drs = false; #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) mcg_mode_t mode = CLOCK_GetMode(); - if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) - { + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) { return kStatus_MCG_ModeUnreachable; } #endif @@ -1586,8 +1495,7 @@ reference clock source changes, then reset to previous value after reference clock changes. */ - if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) - { + if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) { change_drs = true; /* Change the LSB of DRST_DRS. */ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); @@ -1600,45 +1508,37 @@ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) - { - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { + if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) { + if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) { + while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) { } } } /* Wait and check status. */ - while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) - { + while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) { } /* Errata: ERR007993 */ - if (change_drs) - { + if (change_drs) { MCG->C4 = mcg_c4; } /* Set DRS and DMX32. */ - mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | + mcg_c4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); MCG->C4 = mcg_c4; /* Wait for DRST_DRS update. */ - while (MCG->C4 != mcg_c4) - { + while (MCG->C4 != mcg_c4) { } /* Check MCG_S[CLKST] */ - while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) - { + while ((uint8_t)kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) { } /* Wait for FLL stable time. */ - if (NULL != fllStableDelay) - { + if (NULL != fllStableDelay) { fllStableDelay(); } @@ -1661,7 +1561,8 @@ * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed * to frequency above 32768 Hz. */ -status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +status_t +CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; bool change_drs = false; @@ -1670,9 +1571,7 @@ mcg_mode_t mode = CLOCK_GetMode(); if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || - (kMCG_ModeBLPI == mode))) - - { + (kMCG_ModeBLPI == mode))) { return kStatus_MCG_ModeUnreachable; } #endif @@ -1687,8 +1586,7 @@ reference clock source changes, then reset to previous value after reference clock changes. */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { + if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) { change_drs = true; /* Change the LSB of DRST_DRS. */ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); @@ -1700,26 +1598,22 @@ | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ /* Wait and check status. */ - while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) - { + while ((uint8_t)kMCG_FllSrcInternal != MCG_S_IREFST_VAL) { } /* Errata: ERR007993 */ - if (change_drs) - { + if (change_drs) { MCG->C4 = mcg_c4; } - while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) - { + while ((uint8_t)kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) { } MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); /* Wait for FLL stable time. */ - if (NULL != fllStableDelay) - { + if (NULL != fllStableDelay) { fllStableDelay(); } @@ -1741,7 +1635,8 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +status_t +CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { uint8_t mcg_c4; bool change_drs = false; @@ -1749,16 +1644,14 @@ #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) mcg_mode_t mode = CLOCK_GetMode(); if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || - (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) - { + (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) { return kStatus_MCG_ModeUnreachable; } #endif /* Change to FLL mode. */ MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; - while ((MCG->S & MCG_S_PLLST_MASK) != 0U) - { + while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } /* Set LP bit to enable the FLL */ @@ -1772,8 +1665,7 @@ reference clock source changes, then reset to previous value after reference clock changes. */ - if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) - { + if ((uint8_t)kMCG_FllSrcInternal == MCG_S_IREFST_VAL) { change_drs = true; /* Change the LSB of DRST_DRS. */ MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); @@ -1786,24 +1678,19 @@ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) - { - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { + if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) { + if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) { + while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) { } } } /* Wait for Reference clock Status bit to clear */ - while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) - { + while ((uint8_t)kMCG_FllSrcExternal != MCG_S_IREFST_VAL) { } /* Errata: ERR007993 */ - if (change_drs) - { + if (change_drs) { MCG->C4 = mcg_c4; } @@ -1812,13 +1699,11 @@ (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); /* Wait for clock status bits to show clock source is ext ref clk */ - while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) - { + while ((uint8_t)kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) { } /* Wait for fll stable time. */ - if (NULL != fllStableDelay) - { + if (NULL != fllStableDelay) { fllStableDelay(); } @@ -1834,11 +1719,11 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_SetBlpiMode(void) +status_t +CLOCK_SetBlpiMode(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) - { + if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) { return kStatus_MCG_ModeUnreachable; } #endif /* MCG_CONFIG_CHECK_PARAM */ @@ -1858,11 +1743,11 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_SetBlpeMode(void) +status_t +CLOCK_SetBlpeMode(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) - { + if (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) { return kStatus_MCG_ModeUnreachable; } #endif @@ -1892,7 +1777,8 @@ * configuration structure not necessary. In this case, pass in NULL. * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); */ -status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +status_t +CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) { assert(config); @@ -1907,14 +1793,12 @@ /* Wait for CLKST clock status bits to show clock source is ext ref clk */ while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != - (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) - { + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) { } /* Disable PLL first, then configure PLL. */ MCG->C6 &= (uint8_t)(~MCG_C6_PLLS_MASK); - while ((MCG->S & MCG_S_PLLST_MASK) != 0U) - { + while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } /* Configure the PLL. */ @@ -1926,8 +1810,7 @@ MCG->C6 |= MCG_C6_PLLS_MASK; /* Wait for PLL mode changed. */ - while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) - { + while (((MCG->S & MCG_S_PLLST_MASK)) == 0U) { } return kStatus_Success; @@ -1945,12 +1828,12 @@ * PRDIV/VDIV are different than in the PBE mode, set them up * in PBE mode and wait. When the clock is stable, switch to PEE mode. */ -status_t CLOCK_SetPeeMode(void) +status_t +CLOCK_SetPeeMode(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) mcg_mode_t mode = CLOCK_GetMode(); - if (kMCG_ModePBE != mode) - { + if (kMCG_ModePBE != mode) { return kStatus_MCG_ModeUnreachable; } #endif @@ -1959,8 +1842,7 @@ MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); /* Wait for clock status bits to update */ - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) - { + while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) { } return kStatus_Success; @@ -1982,11 +1864,11 @@ * retval kStatus_Success Switched successfully. * retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. */ -status_t CLOCK_ExternalModeToFbeModeQuick(void) +status_t +CLOCK_ExternalModeToFbeModeQuick(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if ((MCG->S & MCG_S_IREFST_MASK) != 0U) - { + if ((MCG->S & MCG_S_IREFST_MASK) != 0U) { return kStatus_MCG_ModeInvalid; } #endif /* MCG_CONFIG_CHECK_PARAM */ @@ -1995,14 +1877,12 @@ MCG->C2 &= (uint8_t)(~MCG_C2_LP_MASK); MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) - { + while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) { } /* Disable PLL. */ MCG->C6 &= ~(uint8_t)MCG_C6_PLLS_MASK; - while ((MCG->S & MCG_S_PLLST_MASK) != 0U) - { + while ((MCG->S & MCG_S_PLLST_MASK) != 0U) { } return kStatus_Success; @@ -2024,11 +1904,11 @@ * retval kStatus_Success Switched successfully. * retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. */ -status_t CLOCK_InternalModeToFbiModeQuick(void) +status_t +CLOCK_InternalModeToFbiModeQuick(void) { #if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) - if ((MCG->S & MCG_S_IREFST_MASK) == 0U) - { + if ((MCG->S & MCG_S_IREFST_MASK) == 0U) { return kStatus_MCG_ModeInvalid; } #endif @@ -2037,8 +1917,7 @@ MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) - { + while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) { } return kStatus_Success; @@ -2059,7 +1938,8 @@ * note If p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed * to frequency above 32768 Hz. */ -status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +status_t +CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay); } @@ -2079,8 +1959,8 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_BootToFeeMode( - mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +status_t +CLOCK_BootToFeeMode(mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) { (void)CLOCK_SetExternalRefClkConfig(oscsel); @@ -2100,15 +1980,15 @@ * retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) +status_t +CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) { /* If reset mode is FEI mode, set MCGIRCLK and always success. */ (void)CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); /* If reset mode is not BLPI, first enter FBI mode. */ MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) - { + while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatInt) { } /* Enter BLPI mode. */ @@ -2128,7 +2008,8 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) +status_t +CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) { (void)CLOCK_SetExternalRefClkConfig(oscsel); @@ -2138,20 +2019,16 @@ | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ /* If use external crystal as clock source, wait for it stable. */ - if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) - { - if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) - { - while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) - { + if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) { + if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) { + while (0U == (MCG->S & MCG_S_OSCINIT0_MASK)) { } } } /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != - (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) - { + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) { } /* In FBE now, start to enter BLPE. */ @@ -2173,7 +2050,8 @@ * retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. * retval kStatus_Success Switched to the target mode successfully. */ -status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +status_t +CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) { assert(config); @@ -2183,8 +2061,7 @@ /* Change to use PLL output clock. */ MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) - { + while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatPll) { } return kStatus_Success; @@ -2233,7 +2110,8 @@ * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this * function. */ -status_t CLOCK_SetMcgConfig(const mcg_config_t *config) +status_t +CLOCK_SetMcgConfig(const mcg_config_t *config) { mcg_mode_t next_mode; status_t status = kStatus_Success; @@ -2241,11 +2119,9 @@ mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0; /* If need to change external clock, MCG_C7[OSCSEL]. */ - if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) - { + if (MCG_C7_OSCSEL_VAL != (uint8_t)(config->oscsel)) { /* If external clock is in use, change to FEI first. */ - if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) - { + if ((uint8_t)kMCG_FllSrcExternal == MCG_S_IREFST_VAL) { (void)CLOCK_ExternalModeToFbeModeQuick(); (void)CLOCK_SetFeiMode(config->dmx32, config->drs, NULL); } @@ -2254,8 +2130,7 @@ } /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ - if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) - { + if (MCG_S_CLKST_VAL == (uint8_t)kMCG_ClkOutStatInt) { MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK; /* Disable lowpower. */ { @@ -2268,67 +2143,56 @@ next_mode = CLOCK_GetMode(); - do - { + do{ next_mode = mcgModeMatrix[next_mode][config->mcgMode]; - switch (next_mode) - { - case kMCG_ModeFEI: - status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); - break; - case kMCG_ModeFEE: - status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); - break; - case kMCG_ModeFBI: - status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL); - break; - case kMCG_ModeFBE: - status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL); - break; - case kMCG_ModeBLPI: - status = CLOCK_SetBlpiMode(); - break; - case kMCG_ModeBLPE: - status = CLOCK_SetBlpeMode(); - break; - case kMCG_ModePBE: - /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ - if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) + switch (next_mode) { + case kMCG_ModeFEI: + status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFEE: + status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFBI: + status = CLOCK_SetFbiMode(config->dmx32, config->drs, NULL); + break; + case kMCG_ModeFBE: + status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, NULL); + break; + case kMCG_ModeBLPI: + status = CLOCK_SetBlpiMode(); + break; + case kMCG_ModeBLPE: + status = CLOCK_SetBlpeMode(); + break; + case kMCG_ModePBE: + /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ + if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) { { - { - status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); - } + status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); } - else - { - MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); - while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) - { - } + } else { + MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != (uint8_t)kMCG_ClkOutStatExt) { } - break; - case kMCG_ModePEE: - status = CLOCK_SetPeeMode(); - break; - default: - assert(false); - break; - } - if (kStatus_Success != status) - { + } break; + case kMCG_ModePEE: + status = CLOCK_SetPeeMode(); + break; + default: + assert(false); + break; + } + if (kStatus_Success != status) { + break; } } while (next_mode != config->mcgMode); - if (status == kStatus_Success) - { - if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) - { + if (status == kStatus_Success) { + if ((config->pll0Config.enableMode & (uint8_t)kMCG_PllEnableIndependent) != 0U) { CLOCK_EnablePll0(&config->pll0Config); - } - else - { + } else { MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; } } ``` </details> #### hw/mcu/nxp/kinetis/src/hal_flash.c <details> ```diff @@ -6,7 +6,7 @@ * to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance * with the License. You may obtain a copy of the License at -* + * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, ``` </details> #### hw/mcu/nxp/kinetis/src/hal_lpuart.c <details> ```diff @@ -59,10 +59,10 @@ hal_uart_tx_char u_tx_func; hal_uart_tx_done u_tx_done; void *u_func_arg; - uint8_t u_configured:1; - uint8_t u_open:1; - uint8_t u_tx_started:1; - uint8_t u_rx_stall:1; + uint8_t u_configured : 1; + uint8_t u_open : 1; + uint8_t u_tx_started : 1; + uint8_t u_rx_stall : 1; struct uart_ring ur_tx; uint8_t tx_buffer[TX_BUF_SZ]; struct uart_ring ur_rx; @@ -465,8 +465,7 @@ uarts[port].ur_rx.ur_head = 0; uarts[port].ur_rx.ur_tail = 0; uarts[port].u_configured = 1; - } - else { + } else { uarts[port].u_configured = 0; } } ``` </details> #### hw/mcu/nxp/kinetis/src/hal_qspi.c <details> ```diff @@ -84,7 +84,8 @@ [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18), /* Match MISRA rule */ - [63] = 0}; + [63] = 0 +}; qspi_flash_config_t g_qspi_flash_cfg = { .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2, @@ -109,15 +110,12 @@ { uint32_t val = 0; /* Check WIP bit */ - do - { - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + do{ + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo); QSPI_ExecuteIPCommand(QuadSPI0, 12U); - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } val = QuadSPI0->RBDR[0]; /* Clear ARDB area */ @@ -128,19 +126,17 @@ static void cmd_write_enable() { - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } QSPI_ExecuteIPCommand(QuadSPI0, 4U); } static void -read_page(uint32_t address, uint32_t* dst) +read_page(uint32_t address, uint32_t * dst) { int i; - for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) - { - dst[i] = ((uint32_t*)address)[i]; + for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++) { + dst[i] = ((uint32_t *)address)[i]; } } @@ -172,15 +168,13 @@ { uint32_t leftLongWords = 0; - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo); QSPI_SetIPCommandAddress(QuadSPI0, dest_addr); cmd_write_enable(); - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } /* First write some data into TXFIFO to prevent from underrun */ @@ -196,8 +190,7 @@ /* Wait until flash finished program */ check_if_finished(); - while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) - { + while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess)) { } #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) @@ -221,7 +214,7 @@ npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE); while (npages) { - write_page(address, (uint32_t*) src); + write_page(address, (uint32_t *) src); npages--; address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE); } @@ -230,13 +223,12 @@ static int nxp_qspi_erase_sector(const struct hal_flash *dev, - uint32_t sector_address) + uint32_t sector_address) { sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE); sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE); - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo); QSPI_SetIPCommandAddress(QuadSPI0, sector_address); @@ -263,8 +255,7 @@ nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE); while (nsects) { - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo); QSPI_SetIPCommandAddress(QuadSPI0, address); @@ -273,7 +264,7 @@ check_if_finished(); #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && \ - (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) + (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) QSPI_ClearCache(QuadSPI0); #endif nsects--; @@ -300,8 +291,7 @@ { uint32_t val[4] = {0x40U, 0, 0, 0}; - while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) - { + while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy) { } QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE); ``` </details> ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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