utzig commented on a change in pull request #2466: URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570608431
########## File path: hw/mcu/nxp/kinetis/src/hal_spi.c ########## @@ -0,0 +1,623 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <string.h> +#include <errno.h> +#include "syscfg/syscfg.h" +#include "os/mynewt.h" +#include "mcu/mcu.h" +#include "mcu/kinetis_hal.h" +#include "hal/hal_spi.h" + +#include <fsl_dspi.h> +#include <fsl_port.h> +#include <fsl_clock.h> + +/* The maximum number of SPI interfaces we will allow */ +#define NXP_HAL_SPI_MAX 3 + +enum spi_type_t { + TYPE_MASTER = HAL_SPI_TYPE_MASTER, + TYPE_SLAVE = HAL_SPI_TYPE_SLAVE +}; + +struct nxp_hal_spi { + SPI_Type *dev; + uint32_t clk_pin; + uint32_t pcs_pin; + uint32_t sout_pin; + uint32_t sin_pin; + PORT_Type *port; + port_mux_t mux; + IRQn_Type irqn; + void (*irq_handler)(void); + hal_spi_txrx_cb txrx_cb; + void *txrx_cb_arg; + bool enabled; + enum spi_type_t type; +}; + +struct nxp_spi_master { + struct nxp_hal_spi hal_spi; + dspi_master_config_t config; + dspi_master_handle_t handle; +}; + +struct nxp_spi_slave { + struct nxp_hal_spi hal_spi; + dspi_slave_config_t config; + dspi_slave_handle_t handle; +}; + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) +static void spi0_irq(void); +#endif +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +static void spi1_irq(void); +#endif +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +static void spi2_irq(void); +#endif + +#if MYNEWT_VAL(SPI_0_MASTER) +struct nxp_spi_master hal_spi0 = { + .hal_spi = { + .dev = SPI0, + .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_0_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_0_MASTER_MUX), + .irqn = SPI0_IRQn, + .irq_handler = spi0_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_0_SLAVE) +struct nxp_spi_slave hal_spi0 = { + .hal_spi = { + .dev = SPI0, + .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_0_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX), + .irqn = SPI0_IRQn, + .irq_handler = spi0_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif +#if MYNEWT_VAL(SPI_1_MASTER) +struct nxp_spi_master hal_spi1 = { + .hal_spi = { + .dev = SPI1, + .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_1_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_1_MASTER_MUX), + .irqn = SPI1_IRQn, + .irq_handler = spi1_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_1_SLAVE) +struct nxp_spi_slave hal_spi1 = { + .hal_spi = { + .dev = SPI1, + .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_1_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX), + .irqn = SPI1_IRQn, + .irq_handler = spi1_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif +#if MYNEWT_VAL(SPI_2_MASTER) +struct nxp_spi_master hal_spi2 = { + .hal_spi = { + .dev = SPI2, + .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_1_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_1_MASTER_MUX), + .irqn = SPI2_IRQn, + .irq_handler = spi2_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_2_SLAVE) +struct nxp_spi_slave hal_spi2 = { + .hal_spi = { + .dev = SPI2, + .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_1_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX), + .irqn = SPI2_IRQn, + .irq_handler = spi2_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif + +static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = { +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) + (struct nxp_hal_spi *) &hal_spi0, +#else + NULL, +#endif +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) + (struct nxp_hal_spi *) &hal_spi1, +#else + NULL, +#endif +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) + (struct nxp_hal_spi *) &hal_spi2 +#else + NULL +#endif +}; + +static struct nxp_hal_spi * +hal_spi_resolve(int spi_num) +{ + if (spi_num >= NXP_HAL_SPI_MAX) { + return NULL; + } + return spi_modules[spi_num]; +} + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) +static void +spi0_irq(void) +{ +#if MYNEWT_VAL(SPI_0_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle); +#elif MYNEWT_VAL(SPI_0_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle); +#endif +} +#endif + +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +static void +spi1_irq(void) +{ +#if MYNEWT_VAL(SPI_1_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle); +#elif MYNEWT_VAL(SPI_1_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle); +#endif +} +#endif + +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +static void +spi2_irq(void) +{ +#if MYNEWT_VAL(SPI_2_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle); +#elif MYNEWT_VAL(SPI_2_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle); +#endif +} +#endif + +static void +hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData) +{ + struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData; + + if (status == kStatus_Success) { + if (spi->txrx_cb) { + spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount); + } + } +} + +static void +hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData) +{ + struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData; + + if (status == kStatus_Success) { + if (spi->txrx_cb) { + spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount); + } + } +} + +static int +hal_spi_init_master(struct nxp_hal_spi *spi, + const struct nxp_hal_spi_cfg *cfg) +{ + struct nxp_spi_master *master; + + if (spi->type == HAL_SPI_TYPE_MASTER) { + master = (struct nxp_spi_master *) spi; + PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux); + DSPI_MasterGetDefaultConfig(&master->config); + return 0; + } + + return EINVAL; +} + +static int +hal_spi_init_slave(struct nxp_hal_spi *spi, + const struct nxp_hal_spi_cfg *cfg) +{ + struct nxp_spi_slave *slave; + + if (spi->type == HAL_SPI_TYPE_SLAVE) { + slave = (struct nxp_spi_slave *) spi; + PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux); + DSPI_SlaveGetDefaultConfig(&slave->config); + return 0; + } + + return EINVAL; +} + + +int +hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) +{ + struct nxp_hal_spi *spi; + + /* cfg isn't implemented, change pin usage using mynewt vals for now. */ + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (spi_type != spi->type) { + return EINVAL; + } + + if (spi_type == HAL_SPI_TYPE_MASTER) { + return hal_spi_init_master(spi, cfg); + } else { + return hal_spi_init_slave(spi, cfg); + } + return EINVAL; +} + +int +hal_spi_init_hw(uint8_t spi_num, + uint8_t spi_type, + const struct hal_spi_hw_settings *cfg) +{ + struct nxp_hal_spi_cfg hal_cfg; + hal_cfg.clk_pin = (uint8_t)cfg->pin_sck; + if (spi_type == HAL_SPI_TYPE_MASTER) { + hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi; + hal_cfg.sin_pin = (uint8_t)cfg->pin_miso; + } else { + hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi; + hal_cfg.sout_pin = (uint8_t)cfg->pin_miso; + } + hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss; + return hal_spi_init(spi_num, &hal_cfg, spi_type); +} + +int +hal_spi_config(int spi_num, struct hal_spi_settings *settings) +{ + struct nxp_hal_spi *spi; + struct nxp_spi_master *master; + struct nxp_spi_slave *slave; + dspi_clock_polarity_t cpol; + dspi_clock_phase_t cpha; + + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (!settings) { + return EINVAL; + } + + switch (settings->data_mode) { + case HAL_SPI_MODE0: + cpol = kDSPI_ClockPolarityActiveHigh; + cpha = kDSPI_ClockPhaseFirstEdge; + break; + case HAL_SPI_MODE1: + cpol = kDSPI_ClockPolarityActiveHigh; + cpha = kDSPI_ClockPhaseSecondEdge; + break; + case HAL_SPI_MODE2: + cpol = kDSPI_ClockPolarityActiveLow; + cpha = kDSPI_ClockPhaseFirstEdge; + break; + case HAL_SPI_MODE3: + cpol = kDSPI_ClockPolarityActiveLow; + cpha = kDSPI_ClockPhaseSecondEdge; + break; + default: + assert(0); Review comment: Can also `return EINVAL` ########## File path: hw/mcu/nxp/kinetis/src/hal_spi.c ########## @@ -0,0 +1,623 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <string.h> +#include <errno.h> +#include "syscfg/syscfg.h" +#include "os/mynewt.h" +#include "mcu/mcu.h" +#include "mcu/kinetis_hal.h" +#include "hal/hal_spi.h" + +#include <fsl_dspi.h> +#include <fsl_port.h> +#include <fsl_clock.h> + +/* The maximum number of SPI interfaces we will allow */ +#define NXP_HAL_SPI_MAX 3 + +enum spi_type_t { + TYPE_MASTER = HAL_SPI_TYPE_MASTER, + TYPE_SLAVE = HAL_SPI_TYPE_SLAVE +}; + +struct nxp_hal_spi { + SPI_Type *dev; + uint32_t clk_pin; + uint32_t pcs_pin; + uint32_t sout_pin; + uint32_t sin_pin; + PORT_Type *port; + port_mux_t mux; + IRQn_Type irqn; + void (*irq_handler)(void); + hal_spi_txrx_cb txrx_cb; + void *txrx_cb_arg; + bool enabled; + enum spi_type_t type; +}; + +struct nxp_spi_master { + struct nxp_hal_spi hal_spi; + dspi_master_config_t config; + dspi_master_handle_t handle; +}; + +struct nxp_spi_slave { + struct nxp_hal_spi hal_spi; + dspi_slave_config_t config; + dspi_slave_handle_t handle; +}; + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) +static void spi0_irq(void); +#endif +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +static void spi1_irq(void); +#endif +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +static void spi2_irq(void); +#endif + +#if MYNEWT_VAL(SPI_0_MASTER) +struct nxp_spi_master hal_spi0 = { + .hal_spi = { + .dev = SPI0, + .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_0_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_0_MASTER_MUX), + .irqn = SPI0_IRQn, + .irq_handler = spi0_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_0_SLAVE) +struct nxp_spi_slave hal_spi0 = { + .hal_spi = { + .dev = SPI0, + .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_0_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX), + .irqn = SPI0_IRQn, + .irq_handler = spi0_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif +#if MYNEWT_VAL(SPI_1_MASTER) +struct nxp_spi_master hal_spi1 = { + .hal_spi = { + .dev = SPI1, + .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_1_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_1_MASTER_MUX), + .irqn = SPI1_IRQn, + .irq_handler = spi1_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_1_SLAVE) +struct nxp_spi_slave hal_spi1 = { + .hal_spi = { + .dev = SPI1, + .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_1_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX), + .irqn = SPI1_IRQn, + .irq_handler = spi1_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif +#if MYNEWT_VAL(SPI_2_MASTER) +struct nxp_spi_master hal_spi2 = { + .hal_spi = { + .dev = SPI2, + .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_1_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_1_MASTER_MUX), + .irqn = SPI2_IRQn, + .irq_handler = spi2_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_2_SLAVE) +struct nxp_spi_slave hal_spi2 = { + .hal_spi = { + .dev = SPI2, + .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_1_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX), + .irqn = SPI2_IRQn, + .irq_handler = spi2_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif + +static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = { +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) + (struct nxp_hal_spi *) &hal_spi0, +#else + NULL, +#endif +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) + (struct nxp_hal_spi *) &hal_spi1, +#else + NULL, +#endif +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) + (struct nxp_hal_spi *) &hal_spi2 +#else + NULL +#endif +}; + +static struct nxp_hal_spi * +hal_spi_resolve(int spi_num) +{ + if (spi_num >= NXP_HAL_SPI_MAX) { + return NULL; + } + return spi_modules[spi_num]; +} + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) +static void +spi0_irq(void) +{ +#if MYNEWT_VAL(SPI_0_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle); +#elif MYNEWT_VAL(SPI_0_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle); +#endif +} +#endif + +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +static void +spi1_irq(void) +{ +#if MYNEWT_VAL(SPI_1_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle); +#elif MYNEWT_VAL(SPI_1_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle); +#endif +} +#endif + +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +static void +spi2_irq(void) +{ +#if MYNEWT_VAL(SPI_2_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle); +#elif MYNEWT_VAL(SPI_2_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle); +#endif +} +#endif + +static void +hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData) +{ + struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData; + + if (status == kStatus_Success) { + if (spi->txrx_cb) { + spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount); + } + } +} + +static void +hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData) +{ + struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData; + + if (status == kStatus_Success) { + if (spi->txrx_cb) { + spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount); + } + } +} + +static int +hal_spi_init_master(struct nxp_hal_spi *spi, + const struct nxp_hal_spi_cfg *cfg) +{ + struct nxp_spi_master *master; + + if (spi->type == HAL_SPI_TYPE_MASTER) { + master = (struct nxp_spi_master *) spi; + PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux); + DSPI_MasterGetDefaultConfig(&master->config); + return 0; + } + + return EINVAL; +} + +static int +hal_spi_init_slave(struct nxp_hal_spi *spi, + const struct nxp_hal_spi_cfg *cfg) +{ + struct nxp_spi_slave *slave; + + if (spi->type == HAL_SPI_TYPE_SLAVE) { + slave = (struct nxp_spi_slave *) spi; + PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux); + DSPI_SlaveGetDefaultConfig(&slave->config); + return 0; + } + + return EINVAL; +} + + +int +hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) +{ + struct nxp_hal_spi *spi; + + /* cfg isn't implemented, change pin usage using mynewt vals for now. */ + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (spi_type != spi->type) { + return EINVAL; + } + + if (spi_type == HAL_SPI_TYPE_MASTER) { + return hal_spi_init_master(spi, cfg); + } else { + return hal_spi_init_slave(spi, cfg); + } + return EINVAL; +} + +int +hal_spi_init_hw(uint8_t spi_num, + uint8_t spi_type, + const struct hal_spi_hw_settings *cfg) +{ + struct nxp_hal_spi_cfg hal_cfg; + hal_cfg.clk_pin = (uint8_t)cfg->pin_sck; + if (spi_type == HAL_SPI_TYPE_MASTER) { + hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi; + hal_cfg.sin_pin = (uint8_t)cfg->pin_miso; + } else { + hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi; + hal_cfg.sout_pin = (uint8_t)cfg->pin_miso; + } + hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss; + return hal_spi_init(spi_num, &hal_cfg, spi_type); +} + +int +hal_spi_config(int spi_num, struct hal_spi_settings *settings) +{ + struct nxp_hal_spi *spi; + struct nxp_spi_master *master; + struct nxp_spi_slave *slave; + dspi_clock_polarity_t cpol; + dspi_clock_phase_t cpha; + + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (!settings) { + return EINVAL; + } + + switch (settings->data_mode) { + case HAL_SPI_MODE0: + cpol = kDSPI_ClockPolarityActiveHigh; + cpha = kDSPI_ClockPhaseFirstEdge; + break; + case HAL_SPI_MODE1: + cpol = kDSPI_ClockPolarityActiveHigh; + cpha = kDSPI_ClockPhaseSecondEdge; + break; + case HAL_SPI_MODE2: + cpol = kDSPI_ClockPolarityActiveLow; + cpha = kDSPI_ClockPhaseFirstEdge; + break; + case HAL_SPI_MODE3: + cpol = kDSPI_ClockPolarityActiveLow; + cpha = kDSPI_ClockPhaseSecondEdge; + break; + default: + assert(0); + break; + } + + if (spi->type == HAL_SPI_TYPE_MASTER) { + master = (struct nxp_spi_master *) spi; + + master->config.ctarConfig.baudRate = settings->baudrate; + master->config.ctarConfig.pcsToSckDelayInNanoSec = + 1000000000U / master->config.ctarConfig.baudRate; + master->config.ctarConfig.lastSckToPcsDelayInNanoSec = + 1000000000U / master->config.ctarConfig.baudRate; + master->config.ctarConfig.betweenTransferDelayInNanoSec = + 1000000000U / master->config.ctarConfig.baudRate; + master->config.ctarConfig.direction = + (settings->data_order == HAL_SPI_MSB_FIRST) ? + kDSPI_MsbFirst : + kDSPI_LsbFirst; + master->config.ctarConfig.bitsPerFrame = + (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9; + master->config.ctarConfig.cpol = cpol; + master->config.ctarConfig.cpha = cpha; + } else { + slave = (struct nxp_spi_slave *) spi; + slave->config.ctarConfig.bitsPerFrame = + (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9; + slave->config.ctarConfig.cpol = cpol; + slave->config.ctarConfig.cpha = cpha; + } Review comment: Since `nxp_spi_master` and `nxp_spi_slave` contain the `nxp_hal_spi` as the first element you could probably just do `master` specific configuration inside the `if` and move the generic after the `if` block: ``` spi->config.ctarConfig.bitsPerFrame = (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9; spi->config.ctarConfig.cpol = cpol; spi->config.ctarConfig.cpha = cpha; ``` And get rid of the `slave` variable. Not entirely sure, disregard if you think it won't work. ########## File path: hw/mcu/nxp/kinetis/src/hal_i2c.c ########## @@ -0,0 +1,408 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <stdint.h> +#include <stdbool.h> +#include "syscfg/syscfg.h" +#include "os/mynewt.h" +#include "os/os_time.h" +#include "mcu/kinetis_hal.h" +#include "mcu/mcu.h" +#include "hal/hal_i2c.h" + +#include <fsl_i2c.h> +#include <fsl_port.h> +#include <fsl_clock.h> + +#define NXP_HAL_I2C_MAX 4 + +struct nxp_hal_i2c { + I2C_Type *dev; + uint32_t scl_pin; + uint32_t sda_pin; + PORT_Type *port; + port_mux_t mux; + IRQn_Type irqn; + void (*irq_handler)(void); + i2c_master_handle_t handle; + struct os_sem sync; + status_t stat; + bool enabled; + bool ongoing; +}; + +#if MYNEWT_VAL(I2C_0) +static void i2c0_irq(void); +static struct nxp_hal_i2c hal_i2c0 = { + .dev = I2C0, + .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL), + .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA), + .port = MYNEWT_VAL(I2C_0_PORT), + .mux = MYNEWT_VAL(I2C_0_MUX), + .irqn = I2C0_IRQn, + .irq_handler = i2c0_irq, + .stat = 0, + .enabled = false +}; +#endif + +#if MYNEWT_VAL(I2C_1) +static void i2c1_irq(void); +static struct nxp_hal_i2c hal_i2c1 = { + .dev = I2C1, + .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL), + .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA), + .port = MYNEWT_VAL(I2C_1_PORT), + .mux = MYNEWT_VAL(I2C_1_MUX), + .irqn = I2C1_IRQn, + .irq_handler = i2c1_irq, + .stat = 0, + .enabled = false +}; +#endif + +#if MYNEWT_VAL(I2C_2) +static void i2c2_irq(void); +static struct nxp_hal_i2c hal_i2c2 = { + .dev = I2C2, + .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL), + .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA), + .port = MYNEWT_VAL(I2C_2_PORT), + .mux = MYNEWT_VAL(I2C_2_MUX), + .irqn = I2C2_IRQn, + .irq_handler = i2c2_irq, + .stat = 0, + .enabled = false +}; +#endif + +#if MYNEWT_VAL(I2C_3) +static void i2c3_irq(void); +static struct nxp_hal_i2c hal_i2c3 = { + .dev = I2C3, + .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL), + .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA), + .port = MYNEWT_VAL(I2C_3_PORT), + .mux = MYNEWT_VAL(I2C_3_MUX), + .irqn = I2C3_IRQn, + .irq_handler = i2c3_irq, + .stat = 0, + .enabled = false +}; +#endif + +static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = { +#if MYNEWT_VAL(I2C_0) + &hal_i2c0, +#else + NULL, +#endif +#if MYNEWT_VAL(I2C_1) + &hal_i2c1, +#else + NULL, +#endif +#if MYNEWT_VAL(I2C_2) + &hal_i2c2, +#else + NULL, +#endif +#if MYNEWT_VAL(I2C_3) + &hal_i2c3, +#else + NULL, +#endif +}; + +#if MYNEWT_VAL(I2C_0) +static void +i2c0_irq(void) +{ + I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle); +} +#endif +#if MYNEWT_VAL(I2C_1) +static void +i2c1_irq(void) +{ + I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle); +} +#endif +#if MYNEWT_VAL(I2C_2) +static void +i2c2_irq(void) +{ + I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle); +} +#endif +#if MYNEWT_VAL(I2C_3) +static void +i2c3_irq(void) +{ + I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle); +} +#endif + +static void +master_xfer_cb(I2C_Type *dev, + i2c_master_handle_t *handle, + status_t status, + void *userData) Review comment: Naming convention: should be `user_data` ########## File path: hw/mcu/nxp/kinetis/src/hal_lpuart.c ########## @@ -0,0 +1,478 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <assert.h> +#include <stdlib.h> + +#include "os/mynewt.h" +#include "hal/hal_uart.h" +#include "hal/hal_gpio.h" +#include "hal/hal_system.h" +#include "mcu/cmsis_nvic.h" +#include "bsp/bsp.h" +#include "syscfg/syscfg.h" +#include "mcu/kinetis_common.h" + +#include "fsl_clock.h" +#include "fsl_port.h" +#include "fsl_lpuart.h" + +#include "hal_lpuart_nxp.h" + +/*! @brief Ring buffer size (Unit: Byte). */ +#define TX_BUF_SZ 32 +#define RX_BUF_SZ 128 + +struct uart_ring { + uint16_t ur_head; + uint16_t ur_tail; + uint16_t ur_size; + uint8_t _pad; + uint8_t *ur_buf; +}; + +struct hal_uart { + LPUART_Type *u_base; + clock_name_t clk_src; + uint32_t u_irq; + PORT_Type *p_base; + clock_ip_name_t p_clock; + int u_pin_rx; + int u_pin_tx; + hal_uart_rx_char u_rx_func; + hal_uart_tx_char u_tx_func; + hal_uart_tx_done u_tx_done; + void *u_func_arg; + uint8_t u_configured : 1; + uint8_t u_open : 1; + uint8_t u_tx_started : 1; + uint8_t u_rx_stall : 1; + struct uart_ring ur_tx; + uint8_t tx_buffer[TX_BUF_SZ]; + struct uart_ring ur_rx; + uint8_t rx_buffer[RX_BUF_SZ]; +}; + +/* UART configurations */ +static struct hal_uart uarts[FSL_FEATURE_SOC_LPUART_COUNT]; + +static uint8_t const s_uartExists[] = NXP_UART_EXISTS; +static uint8_t const s_uartEnabled[] = NXP_UART_ENABLED; +static LPUART_Type *const s_uartBases[] = LPUART_BASE_PTRS; +static clock_name_t s_uartClocks[] = NXP_UART_CLOCKS; +static uint8_t const s_uartIRQ[] = LPUART_RX_TX_IRQS; +static PORT_Type *const s_uartPort[] = NXP_UART_PORTS; +static clock_ip_name_t const s_uartPortClocks[] = NXP_UART_PORT_CLOCKS; +static uint8_t const s_uartPIN_RX[] = NXP_UART_PIN_RX; +static uint8_t const s_uartPIN_TX[] = NXP_UART_PIN_TX; + +static void uart_irq0(void); +static void uart_irq1(void); +static void uart_irq2(void); +static void uart_irq3(void); +static void uart_irq4(void); +static void (*s_uartirqs[])(void) = { + uart_irq0, uart_irq1, uart_irq2, uart_irq3, uart_irq4 +}; + +/* + * RING BUFFER FUNCTIONS + */ + +static uint8_t +ur_is_empty(struct uart_ring *ur) +{ + return (ur->ur_head == ur->ur_tail); +} + +static uint8_t +ur_is_full(struct uart_ring *ur) +{ + return (((ur->ur_tail + 1) % ur->ur_size) == ur->ur_head); +} + +static void +ur_bump(struct uart_ring *ur) +{ + if (!ur_is_empty(ur)) { + ur->ur_head++; + ur->ur_head %= ur->ur_size; + return; + } +} + +static uint8_t +ur_read(struct uart_ring *ur) +{ + return ur->ur_buf[ur->ur_head]; +} + +static int +ur_queue(struct uart_ring *ur, uint8_t data) +{ + if (!ur_is_full(ur)) { + ur->ur_buf[ur->ur_tail] = data; + ur->ur_tail++; + ur->ur_tail %= ur->ur_size; + return 0; + } + return -1; +} + +/* + * END RING BUFFER FUNCTIONS + */ + +int +hal_uart_init_cbs(int port, + hal_uart_tx_char tx_func, + hal_uart_tx_done tx_done, + hal_uart_rx_char rx_func, + void *arg) +{ + struct hal_uart *u; + + if (port >= FSL_FEATURE_SOC_LPUART_COUNT) { + return -1; + } + u = &uarts[port]; + u->u_rx_func = rx_func; + u->u_tx_func = tx_func; + u->u_tx_done = tx_done; + u->u_func_arg = arg; + + return 0; +} + +void +hal_uart_blocking_tx(int port, uint8_t byte) +{ + struct hal_uart *u; + + if (port >= FSL_FEATURE_SOC_LPUART_COUNT) { + return; + } + u = &uarts[port]; + if (!u->u_configured || !u->u_open) { + return; + } + + LPUART_WriteBlocking(u->u_base, &byte, 1); +} + +static int +hal_uart_tx_fill_buf(struct hal_uart *u) +{ + int data = 0; + int i = 0; + os_sr_t sr; + + OS_ENTER_CRITICAL(sr); + while (!ur_is_full(&u->ur_tx)) { + if (u->u_tx_func) { + data = u->u_tx_func(u->u_func_arg); + } + if (data <= 0) { + break; + } + i++; + ur_queue(&u->ur_tx, data); + } + OS_EXIT_CRITICAL(sr); + return i; +} + +void +hal_uart_start_tx(int port) +{ + struct hal_uart *u; + int data = -1; + int rc; + + if (port >= FSL_FEATURE_SOC_LPUART_COUNT) { + return; + } + u = &uarts[port]; + if (!u->u_configured || !u->u_open) { + return; + } + + /* main loop */ + while (true) { + /* add data to TX ring buffer */ + if (u->u_tx_started == 0) { + rc = hal_uart_tx_fill_buf(u); + if (rc > 0) { + u->u_tx_started = 1; + } + } + + /* Send data only when UART TX register is empty and TX ring buffer has data to send out. */ + while (!ur_is_empty(&u->ur_tx) && + (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base))) { + data = ur_read(&u->ur_tx); + LPUART_WriteByte(u->u_base, data); + ur_bump(&u->ur_tx); + } + + if (ur_is_empty(&u->ur_tx)) { + if (u->u_tx_done) { + u->u_tx_done(u->u_func_arg); + } + u->u_tx_started = 0; + break; + } + } +} + +void +hal_uart_start_rx(int port) +{ + struct hal_uart *u; + os_sr_t sr; + int rc = 0; + + if (port >= FSL_FEATURE_SOC_LPUART_COUNT) { + return; + } + u = &uarts[port]; + if (!u->u_configured || !u->u_open) { + return; + } + + u->u_rx_stall = 0; + + /* Send back what's in the RX ring buffer until it's empty or we get an + * error */ + while ((rc >= 0) && !ur_is_empty(&u->ur_rx)) { + OS_ENTER_CRITICAL(sr); + rc = u->u_rx_func(u->u_func_arg, ur_read(&u->ur_rx)); + if (rc >= 0) { + ur_bump(&u->ur_rx); + } else { + u->u_rx_stall = 1; + } + OS_EXIT_CRITICAL(sr); + } +} + +static void +uart_irq_handler(int port) +{ + struct hal_uart *u; + uint32_t status; + uint8_t data; + + u = &uarts[port]; + if (u->u_configured && u->u_open) { + status = LPUART_GetStatusFlags(u->u_base); + /* Check for RX data */ + if (status & (kLPUART_RxDataRegFullFlag | kLPUART_RxOverrunFlag)) { + data = LPUART_ReadByte(u->u_base); + if (u->u_rx_stall || u->u_rx_func(u->u_func_arg, data) < 0) { + /* + * RX queue full. + */ + u->u_rx_stall = 1; + ur_queue(&u->ur_rx, data); + } + } + /* Check for TX complete */ + if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(u->u_base)) { + if (u->u_tx_started) { + u->u_tx_started = 0; + if (u->u_tx_done) { + u->u_tx_done(u->u_func_arg); + } + } + } + } +} + +static void +uart_irq0(void) +{ + uart_irq_handler(0); +} + +static void +uart_irq1(void) +{ + uart_irq_handler(1); +} + +static void +uart_irq2(void) +{ + uart_irq_handler(2); +} + +static void +uart_irq3(void) +{ + uart_irq_handler(3); +} + +static void +uart_irq4(void) +{ + uart_irq_handler(4); +} + +int +hal_uart_config(int port, + int32_t speed, + uint8_t databits, + uint8_t stopbits, + enum hal_uart_parity parity, + enum hal_uart_flow_ctl flow_ctl) +{ + struct hal_uart *u; + lpuart_config_t uconfig; + + if (port >= FSL_FEATURE_SOC_LPUART_COUNT) { + return -1; + } + u = &uarts[port]; + if (!u->u_configured || u->u_open) { + return -1; + } + + /* PIN config (all UARTs use kPORT_MuxAlt3) */ + CLOCK_EnableClock(u->p_clock); + PORT_SetPinMux(u->p_base, u->u_pin_rx, kPORT_MuxAlt3); + PORT_SetPinMux(u->p_base, u->u_pin_tx, kPORT_MuxAlt3); + + /* UART CONFIG */ + CLOCK_SetLpuartClock(2U); + + LPUART_GetDefaultConfig(&uconfig); + uconfig.baudRate_Bps = speed; + + switch (databits) { + case 8: + uconfig.dataBitsCount = kLPUART_EightDataBits; + break; + case 7: +#if FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uconfig.dataBitsCount = kLPUART_SevenDataBits; + break; +#endif /* Fallthrought */ + default: + uconfig.parityMode = kLPUART_ParityEven; + return -1; Review comment: No reason to set `partityMode` if you're going to leave early right? ########## File path: hw/mcu/nxp/kinetis/src/hal_spi.c ########## @@ -0,0 +1,623 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include <string.h> +#include <errno.h> +#include "syscfg/syscfg.h" +#include "os/mynewt.h" +#include "mcu/mcu.h" +#include "mcu/kinetis_hal.h" +#include "hal/hal_spi.h" + +#include <fsl_dspi.h> +#include <fsl_port.h> +#include <fsl_clock.h> + +/* The maximum number of SPI interfaces we will allow */ +#define NXP_HAL_SPI_MAX 3 + +enum spi_type_t { + TYPE_MASTER = HAL_SPI_TYPE_MASTER, + TYPE_SLAVE = HAL_SPI_TYPE_SLAVE +}; + +struct nxp_hal_spi { + SPI_Type *dev; + uint32_t clk_pin; + uint32_t pcs_pin; + uint32_t sout_pin; + uint32_t sin_pin; + PORT_Type *port; + port_mux_t mux; + IRQn_Type irqn; + void (*irq_handler)(void); + hal_spi_txrx_cb txrx_cb; + void *txrx_cb_arg; + bool enabled; + enum spi_type_t type; +}; + +struct nxp_spi_master { + struct nxp_hal_spi hal_spi; + dspi_master_config_t config; + dspi_master_handle_t handle; +}; + +struct nxp_spi_slave { + struct nxp_hal_spi hal_spi; + dspi_slave_config_t config; + dspi_slave_handle_t handle; +}; + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) +static void spi0_irq(void); +#endif +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +static void spi1_irq(void); +#endif +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +static void spi2_irq(void); +#endif + +#if MYNEWT_VAL(SPI_0_MASTER) +struct nxp_spi_master hal_spi0 = { + .hal_spi = { + .dev = SPI0, + .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_0_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_0_MASTER_MUX), + .irqn = SPI0_IRQn, + .irq_handler = spi0_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_0_SLAVE) +struct nxp_spi_slave hal_spi0 = { + .hal_spi = { + .dev = SPI0, + .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_0_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX), + .irqn = SPI0_IRQn, + .irq_handler = spi0_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif +#if MYNEWT_VAL(SPI_1_MASTER) +struct nxp_spi_master hal_spi1 = { + .hal_spi = { + .dev = SPI1, + .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_1_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_1_MASTER_MUX), + .irqn = SPI1_IRQn, + .irq_handler = spi1_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_1_SLAVE) +struct nxp_spi_slave hal_spi1 = { + .hal_spi = { + .dev = SPI1, + .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_1_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX), + .irqn = SPI1_IRQn, + .irq_handler = spi1_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif +#if MYNEWT_VAL(SPI_2_MASTER) +struct nxp_spi_master hal_spi2 = { + .hal_spi = { + .dev = SPI2, + .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK), + .pcs_pin = 0, /* unused */ + .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI), + .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO), + .port = MYNEWT_VAL(SPI_1_MASTER_PORT), + .mux = MYNEWT_VAL(SPI_1_MASTER_MUX), + .irqn = SPI2_IRQn, + .irq_handler = spi2_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_MASTER, + }, + .config = {0}, + .handle = {0}, +}; +#elif MYNEWT_VAL(SPI_2_SLAVE) +struct nxp_spi_slave hal_spi2 = { + .hal_spi = { + .dev = SPI2, + .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK), + .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS), + .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO), + .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI), + .port = MYNEWT_VAL(SPI_1_SLAVE_PORT), + .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX), + .irqn = SPI2_IRQn, + .irq_handler = spi2_irq, + .txrx_cb = NULL, + .txrx_cb_arg = NULL, + .enabled = false, + .type = HAL_SPI_TYPE_SLAVE, + }, + .config = {0}, + .handle = {0}, +}; +#endif + +static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = { +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) + (struct nxp_hal_spi *) &hal_spi0, +#else + NULL, +#endif +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) + (struct nxp_hal_spi *) &hal_spi1, +#else + NULL, +#endif +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) + (struct nxp_hal_spi *) &hal_spi2 +#else + NULL +#endif +}; + +static struct nxp_hal_spi * +hal_spi_resolve(int spi_num) +{ + if (spi_num >= NXP_HAL_SPI_MAX) { + return NULL; + } + return spi_modules[spi_num]; +} + +#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE) +static void +spi0_irq(void) +{ +#if MYNEWT_VAL(SPI_0_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle); +#elif MYNEWT_VAL(SPI_0_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle); +#endif +} +#endif + +#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE) +static void +spi1_irq(void) +{ +#if MYNEWT_VAL(SPI_1_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle); +#elif MYNEWT_VAL(SPI_1_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle); +#endif +} +#endif + +#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE) +static void +spi2_irq(void) +{ +#if MYNEWT_VAL(SPI_2_MASTER) + DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle); +#elif MYNEWT_VAL(SPI_2_SLAVE) + DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle); +#endif +} +#endif + +static void +hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData) +{ + struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData; + + if (status == kStatus_Success) { + if (spi->txrx_cb) { + spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount); + } + } +} + +static void +hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData) +{ + struct nxp_hal_spi *spi = (struct nxp_hal_spi *) userData; + + if (status == kStatus_Success) { + if (spi->txrx_cb) { + spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount); + } + } +} + +static int +hal_spi_init_master(struct nxp_hal_spi *spi, + const struct nxp_hal_spi_cfg *cfg) +{ + struct nxp_spi_master *master; + + if (spi->type == HAL_SPI_TYPE_MASTER) { + master = (struct nxp_spi_master *) spi; + PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux); + DSPI_MasterGetDefaultConfig(&master->config); + return 0; + } + + return EINVAL; +} + +static int +hal_spi_init_slave(struct nxp_hal_spi *spi, + const struct nxp_hal_spi_cfg *cfg) +{ + struct nxp_spi_slave *slave; + + if (spi->type == HAL_SPI_TYPE_SLAVE) { + slave = (struct nxp_spi_slave *) spi; + PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux); + PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux); + DSPI_SlaveGetDefaultConfig(&slave->config); + return 0; + } + + return EINVAL; +} + + +int +hal_spi_init(int spi_num, void *cfg, uint8_t spi_type) +{ + struct nxp_hal_spi *spi; + + /* cfg isn't implemented, change pin usage using mynewt vals for now. */ + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (spi_type != spi->type) { + return EINVAL; + } + + if (spi_type == HAL_SPI_TYPE_MASTER) { + return hal_spi_init_master(spi, cfg); + } else { + return hal_spi_init_slave(spi, cfg); + } + return EINVAL; +} + +int +hal_spi_init_hw(uint8_t spi_num, + uint8_t spi_type, + const struct hal_spi_hw_settings *cfg) +{ + struct nxp_hal_spi_cfg hal_cfg; + hal_cfg.clk_pin = (uint8_t)cfg->pin_sck; + if (spi_type == HAL_SPI_TYPE_MASTER) { + hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi; + hal_cfg.sin_pin = (uint8_t)cfg->pin_miso; + } else { + hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi; + hal_cfg.sout_pin = (uint8_t)cfg->pin_miso; + } + hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss; + return hal_spi_init(spi_num, &hal_cfg, spi_type); +} + +int +hal_spi_config(int spi_num, struct hal_spi_settings *settings) +{ + struct nxp_hal_spi *spi; + struct nxp_spi_master *master; + struct nxp_spi_slave *slave; + dspi_clock_polarity_t cpol; + dspi_clock_phase_t cpha; + + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (!settings) { + return EINVAL; + } + + switch (settings->data_mode) { + case HAL_SPI_MODE0: + cpol = kDSPI_ClockPolarityActiveHigh; + cpha = kDSPI_ClockPhaseFirstEdge; + break; + case HAL_SPI_MODE1: + cpol = kDSPI_ClockPolarityActiveHigh; + cpha = kDSPI_ClockPhaseSecondEdge; + break; + case HAL_SPI_MODE2: + cpol = kDSPI_ClockPolarityActiveLow; + cpha = kDSPI_ClockPhaseFirstEdge; + break; + case HAL_SPI_MODE3: + cpol = kDSPI_ClockPolarityActiveLow; + cpha = kDSPI_ClockPhaseSecondEdge; + break; + default: + assert(0); + break; + } + + if (spi->type == HAL_SPI_TYPE_MASTER) { + master = (struct nxp_spi_master *) spi; + + master->config.ctarConfig.baudRate = settings->baudrate; + master->config.ctarConfig.pcsToSckDelayInNanoSec = + 1000000000U / master->config.ctarConfig.baudRate; + master->config.ctarConfig.lastSckToPcsDelayInNanoSec = + 1000000000U / master->config.ctarConfig.baudRate; + master->config.ctarConfig.betweenTransferDelayInNanoSec = + 1000000000U / master->config.ctarConfig.baudRate; + master->config.ctarConfig.direction = + (settings->data_order == HAL_SPI_MSB_FIRST) ? + kDSPI_MsbFirst : + kDSPI_LsbFirst; + master->config.ctarConfig.bitsPerFrame = + (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9; + master->config.ctarConfig.cpol = cpol; + master->config.ctarConfig.cpha = cpha; + } else { + slave = (struct nxp_spi_slave *) spi; + slave->config.ctarConfig.bitsPerFrame = + (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9; + slave->config.ctarConfig.cpol = cpol; + slave->config.ctarConfig.cpha = cpha; + } + return 0; +} + +int +hal_spi_enable(int spi_num) +{ + struct nxp_hal_spi *spi; + struct nxp_spi_master *master; + struct nxp_spi_slave *slave; + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + if (spi->enabled) { + return 0; + } + + if (spi->type == HAL_SPI_TYPE_MASTER) { + master = (struct nxp_spi_master *) spi; + DSPI_MasterInit(spi->dev, + &master->config, + CLOCK_GetFreq(kCLOCK_BusClk)); + } else { + slave = (struct nxp_spi_slave *) spi; + DSPI_SlaveInit(spi->dev, &slave->config); + } + + spi->enabled = true; + NVIC_ClearPendingIRQ(spi->irqn); + NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler); + NVIC_EnableIRQ(spi->irqn); + return 0; +} + +int +hal_spi_disable(int spi_num) +{ + struct nxp_hal_spi *spi; + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + if (!spi->enabled) { + return 0; + } + + DSPI_Deinit(spi->dev); + + spi->enabled = false; + NVIC_ClearPendingIRQ(spi->irqn); + NVIC_DisableIRQ(spi->irqn); + return 0; +} + +uint16_t +hal_spi_tx_val(int spi_num, uint16_t val) +{ + struct nxp_hal_spi *spi; + dspi_transfer_t xfer; + uint16_t retval = 0; + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (spi->type == HAL_SPI_TYPE_MASTER) { + xfer.txData = (uint8_t *) &val; + xfer.rxData = (uint8_t *) &retval; + xfer.dataSize = 1; + xfer.configFlags = kDSPI_MasterCtar0; + DSPI_MasterTransferBlocking(spi->dev, &xfer); + return retval; + } + return 0xFFFF; /* Invalid API. */ +} + +int +hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len) +{ + struct nxp_hal_spi *spi; + dspi_transfer_t xfer; + status_t rc; + spi = hal_spi_resolve(spi_num); + if (!spi) { + return EINVAL; + } + + if (spi->type == HAL_SPI_TYPE_MASTER) { + xfer.txData = (uint8_t *) txbuf; + xfer.rxData = (uint8_t *) rxbuf; + xfer.dataSize = len; + xfer.configFlags = kDSPI_MasterCtar0; + rc = DSPI_MasterTransferBlocking(spi->dev, &xfer); + return (rc == kStatus_Success) ? 0 : rc; Review comment: If you initialize `rc` to `-1` you can move this `return` after the `if` block. ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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