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The following commit(s) were added to refs/heads/master by this push:
new 039555474 hw/stm32gx: Remove incorrect syscfg values
039555474 is described below
commit 0395554741a8ea6dc243c2e78c729fbcdc3d8e97
Author: Jerzy Kasenberg <[email protected]>
AuthorDate: Tue Apr 8 20:14:58 2025 +0200
hw/stm32gx: Remove incorrect syscfg values
BSP's for STM32G4 and STM32G0 devices had settings
that were not defined for those MCUs
Signed-off-by: Jerzy Kasenberg <[email protected]>
---
hw/bsp/nucleo-g0b1re/syscfg.yml | 3 ---
hw/bsp/nucleo-g491re/syscfg.yml | 3 ---
hw/bsp/weact_g431cb/syscfg.yml | 3 ---
3 files changed, 9 deletions(-)
diff --git a/hw/bsp/nucleo-g0b1re/syscfg.yml b/hw/bsp/nucleo-g0b1re/syscfg.yml
index adf291246..5e330c229 100644
--- a/hw/bsp/nucleo-g0b1re/syscfg.yml
+++ b/hw/bsp/nucleo-g0b1re/syscfg.yml
@@ -35,9 +35,6 @@ syscfg.vals:
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
STM32_FLASH_LATENCY: 'FLASH_LATENCY_2'
WATCHDOG_INTERVAL: 28000
UART_0: 0
diff --git a/hw/bsp/nucleo-g491re/syscfg.yml b/hw/bsp/nucleo-g491re/syscfg.yml
index 92bfcd309..4938fcfd8 100644
--- a/hw/bsp/nucleo-g491re/syscfg.yml
+++ b/hw/bsp/nucleo-g491re/syscfg.yml
@@ -35,9 +35,6 @@ syscfg.vals:
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
STM32_FLASH_LATENCY: 'FLASH_LATENCY_4'
WATCHDOG_INTERVAL: 28000
UART_0_PIN_TX: 'MCU_GPIO_PORTA(9)'
diff --git a/hw/bsp/weact_g431cb/syscfg.yml b/hw/bsp/weact_g431cb/syscfg.yml
index 939c7eaa1..4e7d5a5eb 100644
--- a/hw/bsp/weact_g431cb/syscfg.yml
+++ b/hw/bsp/weact_g431cb/syscfg.yml
@@ -37,9 +37,6 @@ syscfg.vals:
STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
- STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
STM32_FLASH_LATENCY: 'FLASH_LATENCY_4'
WATCHDOG_INTERVAL: 28000
UART_0_PIN_TX: 'MCU_GPIO_PORTA(9)'
