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commit cddf19b4e56454d5efd839816a66583cd0a0ab7e Author: Jerzy Kasenberg <[email protected]> AuthorDate: Thu Oct 30 23:00:31 2025 +0100 bsp/stm32f1xx: Update clock configuration Add explicit values for clock configuration for STM32F1 based BSPs. This is needed due to changes in clock configuration in MCU level. Signed-off-by: Jerzy Kasenberg <[email protected]> --- hw/bsp/bluepill/syscfg.yml | 2 ++ hw/bsp/nucleo-f103rb/syscfg.yml | 2 ++ hw/bsp/olimex-p103/syscfg.yml | 2 ++ 3 files changed, 6 insertions(+) diff --git a/hw/bsp/bluepill/syscfg.yml b/hw/bsp/bluepill/syscfg.yml index 64016a6c7..d74e47d3f 100644 --- a/hw/bsp/bluepill/syscfg.yml +++ b/hw/bsp/bluepill/syscfg.yml @@ -28,6 +28,8 @@ syscfg.vals: STM32_CLOCK_HSI: 1 STM32_CLOCK_HSE: 1 STM32_CLOCK_HSE_BYPASS: 0 + STM32_CLOCK_SYSCLK_SOURCE: LL_RCC_SYS_CLKSOURCE_PLL + STM32_CLOCK_PLL_SOURCE: LL_RCC_PLLSOURCE_HSE STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL9' STM32_CLOCK_PREDIV: 'RCC_HSE_PREDIV_DIV1' STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1' diff --git a/hw/bsp/nucleo-f103rb/syscfg.yml b/hw/bsp/nucleo-f103rb/syscfg.yml index 27707b445..86a9446d2 100644 --- a/hw/bsp/nucleo-f103rb/syscfg.yml +++ b/hw/bsp/nucleo-f103rb/syscfg.yml @@ -28,6 +28,8 @@ syscfg.vals: STM32_CLOCK_HSI: 1 STM32_CLOCK_HSE: 1 STM32_CLOCK_HSE_BYPASS: 1 + STM32_CLOCK_SYSCLK_SOURCE: LL_RCC_SYS_CLKSOURCE_PLL + STM32_CLOCK_PLL_SOURCE: LL_RCC_PLLSOURCE_HSE STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL9' STM32_CLOCK_PREDIV: 'RCC_HSE_PREDIV_DIV1' STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1' diff --git a/hw/bsp/olimex-p103/syscfg.yml b/hw/bsp/olimex-p103/syscfg.yml index 013b0238d..5a63f6b3d 100644 --- a/hw/bsp/olimex-p103/syscfg.yml +++ b/hw/bsp/olimex-p103/syscfg.yml @@ -31,6 +31,8 @@ syscfg.vals: STM32_CLOCK_HSI: 1 STM32_CLOCK_HSE: 1 STM32_CLOCK_HSE_BYPASS: 0 + STM32_CLOCK_SYSCLK_SOURCE: LL_RCC_SYS_CLKSOURCE_PLL + STM32_CLOCK_PLL_SOURCE: LL_RCC_PLLSOURCE_HSE STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL9' STM32_CLOCK_PREDIV: 'RCC_HSE_PREDIV_DIV1' STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
