MYNEWT-391 STM32F4 ADC driver and ADC HAL support - Cleaning up and correcting the dual buf mechanism
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/28814b8d Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/28814b8d Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/28814b8d Branch: refs/heads/sterly_refactor Commit: 28814b8d608a8e2a92a4284220b2c84db4dec9c8 Parents: 82767ae Author: Vipul Rahane <vi...@runtime.io> Authored: Wed Sep 21 16:12:20 2016 -0700 Committer: Vipul Rahane <vi...@runtime.io> Committed: Thu Sep 22 20:21:03 2016 -0700 ---------------------------------------------------------------------- apps/sblinky/src/main.c | 29 ++-- .../include/adc_stm32f4/adc_stm32f4.h | 3 + drivers/adc/adc_stm32f4/src/adc_stm32f4.c | 131 ++++++++------ drivers/adc/include/adc/adc.h | 3 - hw/bsp/olimex_stm32-e407_devboard/pkg.yml | 2 +- hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c | 173 +++++++++++++------ 6 files changed, 221 insertions(+), 120 deletions(-) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/28814b8d/apps/sblinky/src/main.c ---------------------------------------------------------------------- diff --git a/apps/sblinky/src/main.c b/apps/sblinky/src/main.c index 280f410..4277b70 100755 --- a/apps/sblinky/src/main.c +++ b/apps/sblinky/src/main.c @@ -240,14 +240,14 @@ saadc_test(void) #if MYNEWT_VAL(ADC_3) -#define STM32F4_ADC_DEFAULT_CHAN_CFG {\ +#define STM32F4_ADC3_DEFAULT_CHAN_CFG {\ .Channel = ADC_CHANNEL_4,\ .Rank = 1,\ .SamplingTime = ADC_SAMPLETIME_144CYCLES,\ .Offset = 0\ } -ADC_ChannelConfTypeDef adc_chan_cfg = STM32F4_ADC_DEFAULT_CHAN_CFG; +ADC_ChannelConfTypeDef adc3_chan_cfg = STM32F4_ADC3_DEFAULT_CHAN_CFG; uint8_t *sample_buffer1; uint8_t *sample_buffer2; @@ -280,14 +280,14 @@ err: #if MYNEWT_VAL(ADC_1) -#define STM32F4_ADC_DEFAULT_CHAN_CFG10 {\ +#define STM32F4_ADC1_DEFAULT_CHAN_CFG {\ .Channel = ADC_CHANNEL_10,\ .Rank = 1,\ .SamplingTime = ADC_SAMPLETIME_144CYCLES,\ .Offset = 0\ } -ADC_ChannelConfTypeDef adc_chan_cfg10 = STM32F4_ADC_DEFAULT_CHAN_CFG10; +ADC_ChannelConfTypeDef adc1_chan_cfg = STM32F4_ADC1_DEFAULT_CHAN_CFG; int adc1_result; int my_result_mv1[ADC_NUMBER_SAMPLES]; @@ -363,10 +363,10 @@ task1_handler(void *arg) #ifdef STM32F4 #if MYNEWT_VAL(ADC_3) - adc_chan_config(adc3, ADC_CHANNEL_4, &adc_chan_cfg); + adc_chan_config(adc3, ADC_CHANNEL_4, &adc3_chan_cfg); #endif #if MYNEWT_VAL(ADC_1) - adc_chan_config(adc1, ADC_CHANNEL_10, &adc_chan_cfg10); + adc_chan_config(adc1, ADC_CHANNEL_10, &adc1_chan_cfg); #endif #endif @@ -468,15 +468,16 @@ task1_handler(void *arg) int rc; rc = OS_OK; -#if MYNEWT_VAL(ADC_3) - rc = adc_sample(adc3); - assert(rc == OS_OK); -#endif #if MYNEWT_VAL(ADC_1) rc = adc_sample(adc1); assert(rc == OS_OK); #endif + +#if MYNEWT_VAL(ADC_3) + rc = adc_sample(adc3); + assert(rc == OS_OK); +#endif ++g_task1_loops; #if MYNEWT_VAL(SPI_MASTER) @@ -505,13 +506,15 @@ task1_handler(void *arg) /* Release semaphore to task 2 */ os_sem_release(&g_test_sem); } -#if MYNEWT_VAL(ADC_3) - os_dev_close((struct os_dev *) adc3); -#endif #if MYNEWT_VAL(ADC_1) os_dev_close((struct os_dev *) adc1); #endif + +#if MYNEWT_VAL(ADC_3) + os_dev_close((struct os_dev *) adc3); +#endif + } void http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/28814b8d/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h ---------------------------------------------------------------------- diff --git a/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h b/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h index ad5bc86..31f0bb4 100644 --- a/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h +++ b/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h @@ -51,6 +51,9 @@ struct stm32f4_adc_dev_cfg { uint8_t sac_chan_count; void *sac_chans; + void *primarybuf; + void *secondarybuf; + int buflen; ADC_HandleTypeDef *sac_adc_handle; }; http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/28814b8d/drivers/adc/adc_stm32f4/src/adc_stm32f4.c ---------------------------------------------------------------------- diff --git a/drivers/adc/adc_stm32f4/src/adc_stm32f4.c b/drivers/adc/adc_stm32f4/src/adc_stm32f4.c index 029c267..d95c4ea 100644 --- a/drivers/adc/adc_stm32f4/src/adc_stm32f4.c +++ b/drivers/adc/adc_stm32f4/src/adc_stm32f4.c @@ -39,10 +39,13 @@ static struct adc_dev *adc_dma[5]; struct stm32f4_adc_stats { uint16_t adc_events; + uint16_t adc_error; uint16_t adc_DMA_xfer_failed; uint16_t adc_DMA_xfer_aborted; uint16_t adc_DMA_xfer_complete; - uint16_t adc_error; + uint16_t adc_DMA_start_error; + uint16_t adc_DMA_overrun; + uint16_t adc_internal_error; }; static struct stm32f4_adc_stats stm32f4_adc_stats; @@ -266,32 +269,37 @@ stm32f4_resolve_dma_handle_idx(DMA_HandleTypeDef *hdma) return ((stream_addr & 0xFF) - ((uintptr_t)DMA2_Stream0_BASE & 0xFF))/0x18; } -static void -stm32f4_xfer_error_cb(DMA_HandleTypeDef *hdma) -{ - /* DMA transfer error callback */ - stm32f4_adc_stats.adc_DMA_xfer_failed++; -} - -static void -stm32f4_xfer_abort_cb(DMA_HandleTypeDef *hdma) -{ - /* DMA transfer Abort callback */ - stm32f4_adc_stats.adc_DMA_xfer_aborted++; -} - void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { - stm32f4_adc_stats.adc_error++; + ++stm32f4_adc_stats.adc_error; + + if (hadc->ErrorCode & HAL_ADC_ERROR_DMA) { + /* DMA transfer error */ + ++stm32f4_adc_stats.adc_DMA_xfer_failed; + } else if (hadc->ErrorCode & HAL_ADC_ERROR_OVR) { + /* DMA transfer overrun */ + ++stm32f4_adc_stats.adc_DMA_overrun; + } else if (hadc->ErrorCode & HAL_ADC_ERROR_INTERNAL) { + /* ADC IP Internal Error */ + ++stm32f4_adc_stats.adc_internal_error; + } } +/** + * Callback that gets called by the HAL when ADC conversion is complete and + * the DMA buffer is full. If a secondary buffer exists it will the buffers. + * + * @param ADC Handle + */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { int rc; struct adc_dev *adc; DMA_HandleTypeDef *hdma; + struct stm32f4_adc_dev_cfg *cfg; + void *buf; assert(hadc); hdma = hadc->DMA_Handle; @@ -299,16 +307,35 @@ HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) ++stm32f4_adc_stats.adc_DMA_xfer_complete; adc = adc_dma[stm32f4_resolve_dma_handle_idx(hdma)]; + cfg = adc->adc_dev_cfg; + + buf = cfg->primarybuf; + /** + * If primary buffer gets full and secondary buffer exists, swap the + * buffers and start ADC conversion with DMA with the now primary + * buffer(former secondary buffer) + * If the secondary buffer(former primary buffer) doesn't get processed + * by the application in sampling period required for the primary/secondary buffer + * i,e; (sample itvl * ADC_NUMBER_SAMPLES), the buffers would get swapped resulting + * in new sample data. + */ + if (cfg->secondarybuf) { + cfg->primarybuf = cfg->secondarybuf; + cfg->secondarybuf = buf; + + if (HAL_ADC_Start_DMA(hadc, cfg->primarybuf, cfg->buflen) != HAL_OK) { + ++stm32f4_adc_stats.adc_DMA_start_error; + } + } + + rc = adc->ad_event_handler_func(adc, NULL, ADC_EVENT_RESULT, buf, + cfg->buflen); - rc = adc->ad_event_handler_func(adc, NULL, ADC_EVENT_RESULT, adc->primarybuf, - adc->buflen); if (rc) { ++stm32f4_adc_stats.adc_error; } } - -//void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) static void stm32f4_adc_dma_init(ADC_HandleTypeDef* hadc) { @@ -324,16 +351,6 @@ stm32f4_adc_dma_init(ADC_HandleTypeDef* hadc) HAL_DMA_Init(hdma); dma_handle[stm32f4_resolve_dma_handle_idx(hdma)] = hdma; - if (HAL_DMA_RegisterCallback(hdma, HAL_DMA_XFER_ERROR_CB_ID, - stm32f4_xfer_error_cb) != HAL_OK) { - assert(0); - } - - if (HAL_DMA_RegisterCallback(hdma, HAL_DMA_XFER_ABORT_CB_ID, - stm32f4_xfer_abort_cb) != HAL_OK) { - assert(0); - } - NVIC_SetPriority(stm32f4_resolve_adc_dma_irq(hdma), NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_SetVector(stm32f4_resolve_adc_dma_irq(hdma), @@ -528,16 +545,19 @@ static int stm32f4_adc_set_buffer(struct adc_dev *dev, void *buf1, void *buf2, int buflen) { + struct stm32f4_adc_dev_cfg *cfg; int rc; + + assert(dev != NULL && buf1 != NULL); rc = OS_OK; buflen /= sizeof(uint16_t); - assert(dev != NULL && buf1 != NULL); + cfg = dev->adc_dev_cfg; - dev->primarybuf = buf1; - dev->secondarybuf = buf2; - dev->buflen = buflen; + cfg->primarybuf = buf1; + cfg->secondarybuf = buf2; + cfg->buflen = buflen; return rc; } @@ -554,18 +574,14 @@ stm32f4_adc_release_buffer(struct adc_dev *dev, void *buf, int buf_len) HAL_ADC_Stop_DMA(hadc); - if (dev->primarybuf == buf) { - if (dev->secondarybuf) { - dev->primarybuf = dev->secondarybuf; - dev->secondarybuf = buf; - } - } - return (0); } /** * Trigger an ADC sample. + * + * @param ADC device structure + * @return OS_OK on success, non OS_OK on failure */ static int stm32f4_adc_sample(struct adc_dev *dev) @@ -574,13 +590,14 @@ stm32f4_adc_sample(struct adc_dev *dev) ADC_HandleTypeDef *hadc; struct stm32f4_adc_dev_cfg *cfg; - assert(dev != NULL && dev->primarybuf != NULL); + assert(dev); cfg = dev->adc_dev_cfg; hadc = cfg->sac_adc_handle; rc = OS_EINVAL; - if (HAL_ADC_Start_DMA(hadc, dev->primarybuf, dev->buflen) != HAL_OK) { + if (HAL_ADC_Start_DMA(hadc, cfg->primarybuf, cfg->buflen) != HAL_OK) { + ++stm32f4_adc_stats.adc_DMA_start_error; goto err; } @@ -592,6 +609,10 @@ err: /** * Blocking read of an ADC channel, returns result as an integer. + * + * @param1 ADC device structure + * @param2 channel number + * @param3 ADC result ptr */ static int stm32f4_adc_read_channel(struct adc_dev *dev, uint8_t cnum, int *result) @@ -615,11 +636,23 @@ stm32f4_adc_read_buffer(struct adc_dev *dev, void *buf, int buf_len, int off, assert(off < buf_len); - *result = *((uint32_t *) buf + off); + /* + * If secondary buffer exists the primary buf is going to be cached + * in the secondary buffer if the primary buffer is full and we + * would be reading that instead since the buffer is specified by + * the application + */ + *result = *((uint32_t *)buf + off); return (OS_OK); } +/** + * Callback to return size of buffer + * + * @param1 ADC device ptr + * @param2 + */ static int stm32f4_adc_size_buffer(struct adc_dev *dev, int chans, int samples) { @@ -638,6 +671,10 @@ void ADC_IRQHandler(void) * Callback to initialize an adc_dev structure from the os device * initialization callback. This sets up a stm32f4_adc_device(), so * that subsequent lookups to this device allow us to manipulate it. + * + * @param1 os device ptr + * @param2 stm32f4 ADC device cfg ptr + * @return OS_OK on success */ int stm32f4_adc_dev_init(struct os_dev *odev, void *arg) @@ -654,10 +691,6 @@ stm32f4_adc_dev_init(struct os_dev *odev, void *arg) os_mutex_init(&dev->ad_lock); - /* Have a pointer to the init typedef from the configured - * value. This allows non-driver specific items to be configured. - */ - dev->ad_chans = (void *) sac->sac_chans; dev->ad_chan_count = sac->sac_chan_count; @@ -674,6 +707,6 @@ stm32f4_adc_dev_init(struct os_dev *odev, void *arg) af->af_read_buffer = stm32f4_adc_read_buffer; af->af_size_buffer = stm32f4_adc_size_buffer; - return (0); + return (OS_OK); } http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/28814b8d/drivers/adc/include/adc/adc.h ---------------------------------------------------------------------- diff --git a/drivers/adc/include/adc/adc.h b/drivers/adc/include/adc/adc.h index f0d4ad5..d81286e 100644 --- a/drivers/adc/include/adc/adc.h +++ b/drivers/adc/include/adc/adc.h @@ -158,9 +158,6 @@ struct adc_dev { int ad_chan_count; adc_event_handler_func_t ad_event_handler_func; void *ad_event_handler_arg; - void *primarybuf; - void *secondarybuf; - int buflen; }; int adc_chan_config(struct adc_dev *, uint8_t, void *); http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/28814b8d/hw/bsp/olimex_stm32-e407_devboard/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/olimex_stm32-e407_devboard/pkg.yml b/hw/bsp/olimex_stm32-e407_devboard/pkg.yml index 41c0674..3cd2cc0 100644 --- a/hw/bsp/olimex_stm32-e407_devboard/pkg.yml +++ b/hw/bsp/olimex_stm32-e407_devboard/pkg.yml @@ -65,7 +65,7 @@ pkg.syscfg_defs: value: 1 ADC_2: description: "ADC_2" - value: 1 + value: 0 ADC_3: description: "ADC_3" value: 1 http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/28814b8d/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c ---------------------------------------------------------------------- diff --git a/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c b/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c index 39b0bac..3edb114 100644 --- a/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c +++ b/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c @@ -70,23 +70,53 @@ static struct uart_dev hal_uart0; #if MYNEWT_VAL(ADC_1) struct adc_dev my_dev_adc1; #endif - -struct stm32f4_uart_cfg; +#if MYNEWT_VAL(ADC_2) +struct adc_dev my_dev_adc2; +#endif #if MYNEWT_VAL(ADC_3) struct adc_dev my_dev_adc3; #endif +struct stm32f4_uart_cfg; + extern struct stm32f4_uart_cfg *bsp_uart_config(int port); /*****************ADC3 Config ***************/ -#if MYNEWT_VAL(ADC_3) +#if MYNEWT_VAL(ADC_1) +/* + * adc_handle is defined earlier because the DMA handle's + * parent needs to be pointing to the adc_handle + */ +ADC_HandleTypeDef adc1_handle; -ADC_HandleTypeDef adc_handle; +#define STM32F4_DEFAULT_DMA40_HANDLE {\ + .Instance = DMA2_Stream4,\ + .Init.Channel = DMA_CHANNEL_0,\ + .Init.Direction = DMA_PERIPH_TO_MEMORY,\ + .Init.PeriphInc = DMA_PINC_DISABLE,\ + .Init.MemInc = DMA_MINC_ENABLE,\ + .Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD,\ + .Init.MemDataAlignment = DMA_MDATAALIGN_WORD,\ + .Init.Mode = DMA_CIRCULAR,\ + .Init.Priority = DMA_PRIORITY_HIGH,\ + .Init.FIFOMode = DMA_FIFOMODE_DISABLE,\ + .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\ + .Init.MemBurst = DMA_MBURST_SINGLE,\ + .Init.PeriphBurst = DMA_PBURST_SINGLE,\ + .Parent = &adc1_handle,\ +} -#define STM32F4_DEFAULT_DMA_HANDLE21 {\ - .Instance = DMA2_Stream1,\ - .Init.Channel = DMA_CHANNEL_2,\ +DMA_HandleTypeDef adc1_dma40_handle = STM32F4_DEFAULT_DMA40_HANDLE; +#endif + +#if MYNEWT_VAL(ADC_2) + +ADC_HandleTypeDef adc2_handle; + +#define STM32F4_DEFAULT_DMA21_HANDLE {\ + .Instance = DMA2_Stream2,\ + .Init.Channel = DMA_CHANNEL_1,\ .Init.Direction = DMA_PERIPH_TO_MEMORY,\ .Init.PeriphInc = DMA_PINC_DISABLE,\ .Init.MemInc = DMA_MINC_ENABLE,\ @@ -98,22 +128,20 @@ ADC_HandleTypeDef adc_handle; .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\ .Init.MemBurst = DMA_MBURST_SINGLE,\ .Init.PeriphBurst = DMA_PBURST_SINGLE,\ - .Parent = &adc_handle,\ + .Parent = &adc2_handle,\ } + +DMA_HandleTypeDef adc2_dma21_handle = STM32F4_DEFAULT_DMA21_HANDLE; #endif -#if MYNEWT_VAL(ADC_1) -/* - * adc_handle is defined earlier because the DMA handle's - * parent needs to be pointing to the adc_handle - */ -ADC_HandleTypeDef adc_handle120; -DMA_HandleTypeDef adc_dma_handle21 = STM32F4_DEFAULT_DMA_HANDLE21; +#if MYNEWT_VAL(ADC_3) + +ADC_HandleTypeDef adc3_handle; -#define STM32F4_DEFAULT_DMA_HANDLE20 {\ +#define STM32F4_DEFAULT_DMA02_HANDLE {\ .Instance = DMA2_Stream0,\ - .Init.Channel = DMA_CHANNEL_0,\ + .Init.Channel = DMA_CHANNEL_2,\ .Init.Direction = DMA_PERIPH_TO_MEMORY,\ .Init.PeriphInc = DMA_PINC_DISABLE,\ .Init.MemInc = DMA_MINC_ENABLE,\ @@ -125,13 +153,12 @@ DMA_HandleTypeDef adc_dma_handle21 = STM32F4_DEFAULT_DMA_HANDLE21; .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\ .Init.MemBurst = DMA_MBURST_SINGLE,\ .Init.PeriphBurst = DMA_PBURST_SINGLE,\ - .Parent = &adc_handle120,\ + .Parent = &adc3_handle,\ } -DMA_HandleTypeDef adc_dma_handle20 = STM32F4_DEFAULT_DMA_HANDLE20; +DMA_HandleTypeDef adc3_dma02_handle = STM32F4_DEFAULT_DMA02_HANDLE; #endif - #define STM32F4_ADC_DEFAULT_INIT_TD {\ .ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2,\ .Resolution = ADC_RESOLUTION12b,\ @@ -147,74 +174,106 @@ DMA_HandleTypeDef adc_dma_handle20 = STM32F4_DEFAULT_DMA_HANDLE20; .DMAContinuousRequests = ENABLE\ } +#if MYNEWT_VAL(ADC_1) -#if MYNEWT_VAL(ADC_3) - -#define STM32F4_DEFAULT_ADC_HANDLE {\ +/*****************ADC1 Config ***************/ +#define STM32F4_DEFAULT_ADC1_HANDLE {\ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\ - .Instance = ADC3,\ + .Instance = ADC1,\ .NbrOfCurrentConversionRank = 0,\ - .DMA_Handle = &adc_dma_handle21,\ + .DMA_Handle = &adc1_dma40_handle,\ .Lock = HAL_UNLOCKED,\ .State = 0,\ .ErrorCode = 0\ } -ADC_HandleTypeDef adc_handle = STM32F4_DEFAULT_ADC_HANDLE; +ADC_HandleTypeDef adc1_handle = STM32F4_DEFAULT_ADC1_HANDLE; -#define STM32F4_ADC_DEFAULT_SAC_CHAN {\ +#define STM32F4_ADC1_DEFAULT_SAC {\ .c_refmv = 3300,\ .c_res = 12,\ .c_configured = 1,\ - .c_cnum = ADC_CHANNEL_4\ + .c_cnum = ADC_CHANNEL_10\ } -struct adc_chan_config def_sac_chan = STM32F4_ADC_DEFAULT_SAC_CHAN; +struct adc_chan_config adc1_chan10_config = STM32F4_ADC1_DEFAULT_SAC; -#define STM32F4_ADC_DEFAULT_CONFIG {\ +#define STM32F4_ADC1_DEFAULT_CONFIG {\ .sac_chan_count = 16,\ - .sac_chans = &def_sac_chan,\ - .sac_adc_handle = &adc_handle,\ + .sac_chans = &adc1_chan10_config,\ + .sac_adc_handle = &adc1_handle,\ } -struct stm32f4_adc_dev_cfg adc_config = STM32F4_ADC_DEFAULT_CONFIG; +struct stm32f4_adc_dev_cfg adc1_config = STM32F4_ADC1_DEFAULT_CONFIG; +/*********************************************/ #endif +#if MYNEWT_VAL(ADC_2) -#if MYNEWT_VAL(ADC_1) - -/*****************ADC1 Config ***************/ -#define STM32F4_DEFAULT_ADC_HANDLE120 {\ +/*****************ADC2 Config ***************/ +#define STM32F4_DEFAULT_ADC2_HANDLE {\ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\ - .Instance = ADC1,\ + .Instance = ADC2,\ .NbrOfCurrentConversionRank = 0,\ - .DMA_Handle = &adc_dma_handle20,\ + .DMA_Handle = &adc2_dma21_handle,\ .Lock = HAL_UNLOCKED,\ .State = 0,\ .ErrorCode = 0\ } -ADC_HandleTypeDef adc_handle120 = STM32F4_DEFAULT_ADC_HANDLE120; +ADC_HandleTypeDef adc2_handle = STM32F4_DEFAULT_ADC2_HANDLE; -#define STM32F4_ADC_DEFAULT_SAC_CHAN10 {\ +#define STM32F4_ADC2_DEFAULT_SAC {\ .c_refmv = 3300,\ .c_res = 12,\ .c_configured = 1,\ - .c_cnum = ADC_CHANNEL_10\ + .c_cnum = ADC_CHANNEL_1\ } -struct adc_chan_config def_sac_chan10 = STM32F4_ADC_DEFAULT_SAC_CHAN10; +struct adc_chan_config adc2_chan1_config = STM32F4_ADC2_DEFAULT_SAC; -#define STM32F4_ADC_DEFAULT_CONFIG_1_2_0_10 {\ +#define STM32F4_ADC2_DEFAULT_CONFIG {\ .sac_chan_count = 16,\ - .sac_chans = &def_sac_chan10,\ - .sac_adc_handle = &adc_handle120,\ + .sac_chans = &adc2_chan1_config,\ + .sac_adc_handle = &adc2_handle,\ } -struct stm32f4_adc_dev_cfg adc_config12010 = STM32F4_ADC_DEFAULT_CONFIG_1_2_0_10; +struct stm32f4_adc_dev_cfg adc2_config = STM32F4_ADC2_DEFAULT_CONFIG; /*********************************************/ #endif +#if MYNEWT_VAL(ADC_3) + +#define STM32F4_DEFAULT_ADC3_HANDLE {\ + .Init = STM32F4_ADC_DEFAULT_INIT_TD,\ + .Instance = ADC3,\ + .NbrOfCurrentConversionRank = 0,\ + .DMA_Handle = &adc3_dma02_handle,\ + .Lock = HAL_UNLOCKED,\ + .State = 0,\ + .ErrorCode = 0\ +} + +ADC_HandleTypeDef adc3_handle = STM32F4_DEFAULT_ADC3_HANDLE; + +#define STM32F4_ADC3_DEFAULT_SAC {\ + .c_refmv = 3300,\ + .c_res = 12,\ + .c_configured = 1,\ + .c_cnum = ADC_CHANNEL_4\ +} + +struct adc_chan_config adc3_chan4_config = STM32F4_ADC3_DEFAULT_SAC; + +#define STM32F4_ADC3_DEFAULT_CONFIG {\ + .sac_chan_count = 16,\ + .sac_chans = &adc3_chan4_config,\ + .sac_adc_handle = &adc3_handle,\ +} + +struct stm32f4_adc_dev_cfg adc3_config = STM32F4_ADC3_DEFAULT_CONFIG; +#endif + void _close(int fd); /* @@ -247,18 +306,24 @@ bsp_init(void) rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART, OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)bsp_uart_config(0)); assert(rc == 0); -#if MYNEWT_VAL(ADC_3) - rc = os_dev_create((struct os_dev *) &my_dev_adc3, "adc3", +#if MYNEWT_VAL(ADC_1) + rc = os_dev_create((struct os_dev *) &my_dev_adc1, "adc1", OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT, - stm32f4_adc_dev_init, &adc_config); + stm32f4_adc_dev_init, &adc1_config); assert(rc == 0); #endif - -#if MYNEWT_VAL(ADC_1) - rc = os_dev_create((struct os_dev *) &my_dev_adc1, "adc1", +#if MYNEWT_VAL(ADC_2) + rc = os_dev_create((struct os_dev *) &my_dev_adc2, "adc2", OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT, - stm32f4_adc_dev_init, &adc_config12010); + stm32f4_adc_dev_init, &adc2_config); assert(rc == 0); #endif +#if MYNEWT_VAL(ADC_3) + rc = os_dev_create((struct os_dev *) &my_dev_adc3, "adc3", + OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT, + stm32f4_adc_dev_init, &adc3_config); + assert(rc == 0); +#endif + }
