bsp: frdm-k64f: initial setup for FRDM-K64F BSP Adds support for NXP FRDM-K64F hardware using mcu/nxp/MK64F12 HAL layers
Signed-off-by: Michael Scott <michael.sc...@linaro.org> Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/9a45975e Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/9a45975e Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/9a45975e Branch: refs/heads/develop Commit: 9a45975e65c819b9147e48cebde47a601bfe73e3 Parents: 920371a Author: Michael Scott <michael.sc...@linaro.org> Authored: Fri Oct 7 16:41:38 2016 -0700 Committer: Michael Scott <michael.sc...@linaro.org> Committed: Mon Oct 10 23:59:41 2016 -0700 ---------------------------------------------------------------------- hw/bsp/frdm-k64f/MK64FN1M0xxx12_flash.ld | 266 +++++ hw/bsp/frdm-k64f/boot-MK64FN1M0xxx12_flash.ld | 261 +++++ hw/bsp/frdm-k64f/bsp.yml | 57 ++ hw/bsp/frdm-k64f/frdm-k64_debug.sh | 45 + hw/bsp/frdm-k64f/frdm-k64_download.sh | 62 ++ hw/bsp/frdm-k64f/include/bsp/bsp.h | 50 + hw/bsp/frdm-k64f/include/bsp/bsp_sysid.h | 35 + hw/bsp/frdm-k64f/include/bsp/cmsis_nvic.h | 52 + hw/bsp/frdm-k64f/pkg.yml | 51 + .../src/arch/cortex_m4/startup_MK64F12.S | 997 +++++++++++++++++++ hw/bsp/frdm-k64f/src/clock_config.c | 197 ++++ hw/bsp/frdm-k64f/src/clock_config.h | 53 + hw/bsp/frdm-k64f/src/hal_bsp.c | 95 ++ hw/bsp/frdm-k64f/src/libc_stubs.c | 70 ++ hw/bsp/frdm-k64f/src/os_bsp.c | 110 ++ hw/bsp/frdm-k64f/syscfg.yml | 114 +++ 16 files changed, 2515 insertions(+) ---------------------------------------------------------------------- http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/MK64FN1M0xxx12_flash.ld ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/MK64FN1M0xxx12_flash.ld b/hw/bsp/frdm-k64f/MK64FN1M0xxx12_flash.ld new file mode 100644 index 0000000..838e64d --- /dev/null +++ b/hw/bsp/frdm-k64f/MK64FN1M0xxx12_flash.ld @@ -0,0 +1,266 @@ +/* +** ################################################################### +** Processors: MK64FN1M0CAJ12 +** MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: GNU C Compiler +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.9, 2016-03-21 +** Build: b160321 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: supp...@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x10000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00008000, LENGTH = 0x00000420 + m_flash_config (RX) : ORIGIN = 0x00008420, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00008430, LENGTH = 0x00100000-0x8430 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +/* Define output sections */ +SECTIONS +{ + .imghdr (NOLOAD): + { + . = . + 0x20; + } > m_interrupts + + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + . = ALIGN(512); + USB_RAM_START = .; + . += USB_RAM_GAP; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data_2 + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data_2 + + m_usb_bdt USB_RAM_START (NOLOAD) : + { + *(m_usb_bdt) + USB_RAM_BDT_END = .; + } + + m_usb_global USB_RAM_BDT_END (NOLOAD) : + { + *(m_usb_global) + } + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/boot-MK64FN1M0xxx12_flash.ld ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/boot-MK64FN1M0xxx12_flash.ld b/hw/bsp/frdm-k64f/boot-MK64FN1M0xxx12_flash.ld new file mode 100644 index 0000000..9f5da70 --- /dev/null +++ b/hw/bsp/frdm-k64f/boot-MK64FN1M0xxx12_flash.ld @@ -0,0 +1,261 @@ +/* +** ################################################################### +** Processors: MK64FN1M0CAJ12 +** MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: GNU C Compiler +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.9, 2016-03-21 +** Build: b160321 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: supp...@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x10000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + . = ALIGN(512); + USB_RAM_START = .; + . += USB_RAM_GAP; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data_2 + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data_2 + + m_usb_bdt USB_RAM_START (NOLOAD) : + { + *(m_usb_bdt) + USB_RAM_BDT_END = .; + } + + m_usb_global USB_RAM_BDT_END (NOLOAD) : + { + *(m_usb_global) + } + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/bsp.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/bsp.yml b/hw/bsp/frdm-k64f/bsp.yml new file mode 100644 index 0000000..10ed8e7 --- /dev/null +++ b/hw/bsp/frdm-k64f/bsp.yml @@ -0,0 +1,57 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +bsp.arch: cortex_m4 +bsp.compiler: compiler/arm-none-eabi-m4 +bsp.linkerscript: "MK64FN1M0xxx12_flash.ld" +bsp.linkerscript.BOOT_LOADER.OVERWRITE: "boot-MK64FN1M0xxx12_flash.ld" +bsp.downloadscript: frdm-k64_download.sh +bsp.debugscript: frdm-k64_debug.sh + +bsp.flash_map: + areas: + # System areas. + FLASH_AREA_BOOTLOADER: + device: 0 + offset: 0x00000000 + size: 24kB + FLASH_AREA_IMAGE_SCRATCH: + device: 0 + offset: 0x00006000 + size: 8kB + FLASH_AREA_IMAGE_0: + device: 0 + offset: 0x00008000 + size: 480kB + FLASH_AREA_IMAGE_1: + device: 0 + offset: 0x00080000 + size: 480kB + + # User areas + FLASH_AREA_REBOOT_LOG: + user_id: 0 + device: 0 + offset: 0x000F8000 + size: 16kB + FLASH_AREA_NFFS: + user_id: 1 + device: 0 + offset: 0x000FC000 + size: 16kB http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/frdm-k64_debug.sh ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/frdm-k64_debug.sh b/hw/bsp/frdm-k64f/frdm-k64_debug.sh new file mode 100755 index 0000000..b387d9c --- /dev/null +++ b/hw/bsp/frdm-k64f/frdm-k64_debug.sh @@ -0,0 +1,45 @@ +#!/bin/sh +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# +# Called: $0 <bsp_directory_path> <binary> [features...] +# - bsp_directory_path is absolute path to hw/bsp/bsp_name +# - binary is the path to prefix to target binary, .elf appended to name is +# the ELF file +# - identities is the project identities string. +# +if [ $# -lt 1 ]; then + echo "Need binary to debug" + exit 1 +fi + +FILE_NAME=$2.elf +GDB_CMD_FILE=.gdb_cmds + +echo "Debugging" $FILE_NAME + +# +# Block Ctrl-C from getting passed to openocd. +# Exit openocd when gdb detaches. +# +set -m +pyocd-gdbserver & +set +m + +echo "target remote localhost:3333" > $GDB_CMD_FILE +arm-none-eabi-gdb -x $GDB_CMD_FILE $FILE_NAME +rm $GDB_CMD_FILE http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/frdm-k64_download.sh ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/frdm-k64_download.sh b/hw/bsp/frdm-k64f/frdm-k64_download.sh new file mode 100755 index 0000000..e62dc4d --- /dev/null +++ b/hw/bsp/frdm-k64f/frdm-k64_download.sh @@ -0,0 +1,62 @@ +#!/bin/bash +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. + +# Called with following variables set: +# - BSP_PATH is absolute path to hw/bsp/bsp_name +# - BIN_BASENAME is the path to prefix to target binary, +# .elf appended to name is the ELF file +# - IMAGE_SLOT is the image slot to download to +# - FEATURES holds the target features string +# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software +# + +if [ -z "${BIN_BASENAME}" ]; then + echo "Need binary to download" + exit 1 +fi + +if [ -z "${IMAGE_SLOT}" ]; then + echo "Need image slot to download" + exit 1 +fi + +IS_BOOTLOADER=0 +USE_OPENOCD=0 +GDB_CMD_FILE=.gdb_cmds + +# Look for 'bootloader' in FEATURES +for feature in ${FEATURES}; do + if [ ${feature} == "BOOT_LOADER" ]; then + IS_BOOTLOADER=1 + fi + if [ ${feature} = "openocd_debug" ]; then + USE_OPENOCD=1 + fi +done + +if [ ${IS_BOOTLOADER} -eq 1 ]; then + FLASH_OFFSET=0x00000000 + FILE_NAME=${BIN_BASENAME}.elf.bin +else + FLASH_OFFSET=0x00008000 + FILE_NAME=${BIN_BASENAME}.elf.bin +fi + +echo "Downloading" ${FILE_NAME} "to" ${FLASH_OFFSET} + +pyocd-flashtool -se --address ${FLASH_OFFSET} ${FILE_NAME} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/include/bsp/bsp.h ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/include/bsp/bsp.h b/hw/bsp/frdm-k64f/include/bsp/bsp.h new file mode 100644 index 0000000..3eab87e --- /dev/null +++ b/hw/bsp/frdm-k64f/include/bsp/bsp.h @@ -0,0 +1,50 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_BSP_H +#define H_BSP_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint8_t __DATA_ROM; +#define RAM_SIZE 0x40000 + +/* LED pins */ +#define LED_BLINK_PIN (54) + +/* UART info */ +#define CONSOLE_UART "uart0" +#define CONSOLE_UART_SPEED 115200 + +/* This defines the maximum NFFS areas (block) are in the BSPs NFS file + * system space. This in conjunction with flash map determines how + * many NFS blocks there will be. A minimum is the number of individually + * erasable sectors in the flash area and the maximum is this number. If + * your max is less than the number of sectors then the NFFS will combine + * multiple sectors into an NFFS area */ +#define NFFS_AREA_MAX (8) + +#ifdef __cplusplus +} +#endif + +#endif /* H_BSP_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/include/bsp/bsp_sysid.h ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/include/bsp/bsp_sysid.h b/hw/bsp/frdm-k64f/include/bsp/bsp_sysid.h new file mode 100644 index 0000000..bcce1e6 --- /dev/null +++ b/hw/bsp/frdm-k64f/include/bsp/bsp_sysid.h @@ -0,0 +1,35 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef BSP_SYSID_H +#define BSP_SYSID_H + +#ifdef __cplusplus +extern "C" { +#endif + +enum system_device_id +{ + NONE = 0, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_SYSID_H */ http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/include/bsp/cmsis_nvic.h ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/include/bsp/cmsis_nvic.h b/hw/bsp/frdm-k64f/include/bsp/cmsis_nvic.h new file mode 100644 index 0000000..4531d63 --- /dev/null +++ b/hw/bsp/frdm-k64f/include/bsp/cmsis_nvic.h @@ -0,0 +1,52 @@ +/** + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/* mbed Microcontroller Library - cmsis_nvic + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef CMSIS_NVIC_H +#define CMSIS_NVIC_H + +#include <stdint.h> + +#define NVIC_NUM_VECTORS (16 + 101) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +/* + * include board definition file which includes: cmsis-core/core_cm4.h + * this fixes missing CORTEX_M* definition in cmsis_nvic.c + */ +#include "MK64F12.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_Relocate(void); +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/pkg.yml ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/pkg.yml b/hw/bsp/frdm-k64f/pkg.yml new file mode 100644 index 0000000..e9163de --- /dev/null +++ b/hw/bsp/frdm-k64f/pkg.yml @@ -0,0 +1,51 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: "hw/bsp/frdm-k64f" +pkg.type: bsp +pkg.description: BSP definition for NXP FRDM-K64F with 1Mb flash. +pkg.keywords: + - frdm-k64f + - nxp + +pkg.cflags: -DDEBUG -fno-builtin -fno-common -ffreestanding -mfloat-abi=hard -mfpu=fpv4-sp-d16 -DCPU_MK64FN1M0VMD12 -DPRINTF_FLOAT_ENABLE=0 -DSCANF_FLOAT_ENABLE=0 -DPRINTF_ADVANCED_ENABLE=0 -DSCANF_ADVANCED_ENABLE=0 -DFRDM_K64F -DFREEDOM -DUSE_RAM_VECTOR_TABLE -Wl,--defsym=__ram_vector_table__=1 + +pkg.deps: + - boot/bootutil + - hw/mcu/nxp/MK64F12 + - libc/baselibc + - sys/flash_map + +pkg.deps.UART_0: + - hw/drivers/uart/uart_hal + +pkg.deps.UART_1: + - hw/drivers/uart/uart_hal + +pkg.deps.UART_2: + - hw/drivers/uart/uart_hal + +pkg.deps.UART_3: + - hw/drivers/uart/uart_hal + +pkg.deps.UART_4: + - hw/drivers/uart/uart_hal + +pkg.deps.UART_5: + - hw/drivers/uart/uart_hal http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/src/arch/cortex_m4/startup_MK64F12.S ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/src/arch/cortex_m4/startup_MK64F12.S b/hw/bsp/frdm-k64f/src/arch/cortex_m4/startup_MK64F12.S new file mode 100644 index 0000000..dcc6e3f --- /dev/null +++ b/hw/bsp/frdm-k64f/src/arch/cortex_m4/startup_MK64F12.S @@ -0,0 +1,997 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MK64F12.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MK64F12 */ +/* @version: 2.9 */ +/* @date: 2016-3-21 */ +/* @build: b160321 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ + .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ + .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ + .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ + .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/ + .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/ + .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/ + .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/ + .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/ + .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/ + .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/ + .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/ + .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/ + .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/ + .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/ + .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/ + .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ + .long MCM_IRQHandler /* Normal Interrupt*/ + .long FTFE_IRQHandler /* FTFE Command complete interrupt*/ + .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ + .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/ + .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ + .long RNG_IRQHandler /* RNG Interrupt*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 Interrupt*/ + .long SPI1_IRQHandler /* SPI1 Interrupt*/ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ + .long UART0_LON_IRQHandler /* UART0 LON interrupt*/ + .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ + .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ + .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ + .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ + .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ + .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ + .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/ + .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long CMP1_IRQHandler /* CMP1 interrupt*/ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ + .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ + .long CMT_IRQHandler /* CMT interrupt*/ + .long RTC_IRQHandler /* RTC interrupt*/ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ + .long PDB0_IRQHandler /* PDB0 Interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long USBDCD_IRQHandler /* USBDCD Interrupt*/ + .long Reserved71_IRQHandler /* Reserved interrupt 71*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long MCG_IRQHandler /* MCG Interrupt*/ + .long LPTMR0_IRQHandler /* LPTimer interrupt*/ + .long PORTA_IRQHandler /* Port A interrupt*/ + .long PORTB_IRQHandler /* Port B interrupt*/ + .long PORTC_IRQHandler /* Port C interrupt*/ + .long PORTD_IRQHandler /* Port D interrupt*/ + .long PORTE_IRQHandler /* Port E interrupt*/ + .long SWI_IRQHandler /* Software interrupt*/ + .long SPI2_IRQHandler /* SPI2 Interrupt*/ + .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/ + .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/ + .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/ + .long UART5_ERR_IRQHandler /* UART5 Error interrupt*/ + .long CMP2_IRQHandler /* CMP2 interrupt*/ + .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ + .long DAC1_IRQHandler /* DAC1 interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long I2C2_IRQHandler /* I2C2 interrupt*/ + .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/ + .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/ + .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/ + .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/ + .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/ + .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/ + .long SDHC_IRQHandler /* SDHC interrupt*/ + .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/ + .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/ + .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/ + .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/ + .long DefaultISR /* 102*/ + .long DefaultISR /* 103*/ + .long DefaultISR /* 104*/ + .long DefaultISR /* 105*/ + .long DefaultISR /* 106*/ + .long DefaultISR /* 107*/ + .long DefaultISR /* 108*/ + .long DefaultISR /* 109*/ + .long DefaultISR /* 110*/ + .long DefaultISR /* 111*/ + .long DefaultISR /* 112*/ + .long DefaultISR /* 113*/ + .long DefaultISR /* 114*/ + .long DefaultISR /* 115*/ + .long DefaultISR /* 116*/ + .long DefaultISR /* 117*/ + .long DefaultISR /* 118*/ + .long DefaultISR /* 119*/ + .long DefaultISR /* 120*/ + .long DefaultISR /* 121*/ + .long DefaultISR /* 122*/ + .long DefaultISR /* 123*/ + .long DefaultISR /* 124*/ + .long DefaultISR /* 125*/ + .long DefaultISR /* 126*/ + .long DefaultISR /* 127*/ + .long DefaultISR /* 128*/ + .long DefaultISR /* 129*/ + .long DefaultISR /* 130*/ + .long DefaultISR /* 131*/ + .long DefaultISR /* 132*/ + .long DefaultISR /* 133*/ + .long DefaultISR /* 134*/ + .long DefaultISR /* 135*/ + .long DefaultISR /* 136*/ + .long DefaultISR /* 137*/ + .long DefaultISR /* 138*/ + .long DefaultISR /* 139*/ + .long DefaultISR /* 140*/ + .long DefaultISR /* 141*/ + .long DefaultISR /* 142*/ + .long DefaultISR /* 143*/ + .long DefaultISR /* 144*/ + .long DefaultISR /* 145*/ + .long DefaultISR /* 146*/ + .long DefaultISR /* 147*/ + .long DefaultISR /* 148*/ + .long DefaultISR /* 149*/ + .long DefaultISR /* 150*/ + .long DefaultISR /* 151*/ + .long DefaultISR /* 152*/ + .long DefaultISR /* 153*/ + .long DefaultISR /* 154*/ + .long DefaultISR /* 155*/ + .long DefaultISR /* 156*/ + .long DefaultISR /* 157*/ + .long DefaultISR /* 158*/ + .long DefaultISR /* 159*/ + .long DefaultISR /* 160*/ + .long DefaultISR /* 161*/ + .long DefaultISR /* 162*/ + .long DefaultISR /* 163*/ + .long DefaultISR /* 164*/ + .long DefaultISR /* 165*/ + .long DefaultISR /* 166*/ + .long DefaultISR /* 167*/ + .long DefaultISR /* 168*/ + .long DefaultISR /* 169*/ + .long DefaultISR /* 170*/ + .long DefaultISR /* 171*/ + .long DefaultISR /* 172*/ + .long DefaultISR /* 173*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR +#ifdef USE_RAM_VECTOR_TABLE + ldr r1, =__interrupts_ram_start__ +#else + ldr r1, =__isr_vector +#endif + str r1, [r0] +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_IRQHandler + .type DMA4_IRQHandler, %function +DMA4_IRQHandler: + ldr r0,=DMA4_DriverIRQHandler + bx r0 + .size DMA4_IRQHandler, . - DMA4_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_IRQHandler + .type DMA5_IRQHandler, %function +DMA5_IRQHandler: + ldr r0,=DMA5_DriverIRQHandler + bx r0 + .size DMA5_IRQHandler, . - DMA5_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_IRQHandler + .type DMA6_IRQHandler, %function +DMA6_IRQHandler: + ldr r0,=DMA6_DriverIRQHandler + bx r0 + .size DMA6_IRQHandler, . - DMA6_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_IRQHandler + .type DMA7_IRQHandler, %function +DMA7_IRQHandler: + ldr r0,=DMA7_DriverIRQHandler + bx r0 + .size DMA7_IRQHandler, . - DMA7_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_IRQHandler + .type DMA8_IRQHandler, %function +DMA8_IRQHandler: + ldr r0,=DMA8_DriverIRQHandler + bx r0 + .size DMA8_IRQHandler, . - DMA8_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_IRQHandler + .type DMA9_IRQHandler, %function +DMA9_IRQHandler: + ldr r0,=DMA9_DriverIRQHandler + bx r0 + .size DMA9_IRQHandler, . - DMA9_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_IRQHandler + .type DMA10_IRQHandler, %function +DMA10_IRQHandler: + ldr r0,=DMA10_DriverIRQHandler + bx r0 + .size DMA10_IRQHandler, . - DMA10_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_IRQHandler + .type DMA11_IRQHandler, %function +DMA11_IRQHandler: + ldr r0,=DMA11_DriverIRQHandler + bx r0 + .size DMA11_IRQHandler, . - DMA11_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_IRQHandler + .type DMA12_IRQHandler, %function +DMA12_IRQHandler: + ldr r0,=DMA12_DriverIRQHandler + bx r0 + .size DMA12_IRQHandler, . - DMA12_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_IRQHandler + .type DMA13_IRQHandler, %function +DMA13_IRQHandler: + ldr r0,=DMA13_DriverIRQHandler + bx r0 + .size DMA13_IRQHandler, . - DMA13_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_IRQHandler + .type DMA14_IRQHandler, %function +DMA14_IRQHandler: + ldr r0,=DMA14_DriverIRQHandler + bx r0 + .size DMA14_IRQHandler, . - DMA14_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_IRQHandler + .type DMA15_IRQHandler, %function +DMA15_IRQHandler: + ldr r0,=DMA15_DriverIRQHandler + bx r0 + .size DMA15_IRQHandler, . - DMA15_IRQHandler + + .align 1 + .thumb_func + .weak DMA_Error_IRQHandler + .type DMA_Error_IRQHandler, %function +DMA_Error_IRQHandler: + ldr r0,=DMA_Error_DriverIRQHandler + bx r0 + .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Tx_IRQHandler + .type I2S0_Tx_IRQHandler, %function +I2S0_Tx_IRQHandler: + ldr r0,=I2S0_Tx_DriverIRQHandler + bx r0 + .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Rx_IRQHandler + .type I2S0_Rx_IRQHandler, %function +I2S0_Rx_IRQHandler: + ldr r0,=I2S0_Rx_DriverIRQHandler + bx r0 + .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler + + .align 1 + .thumb_func + .weak UART0_LON_IRQHandler + .type UART0_LON_IRQHandler, %function +UART0_LON_IRQHandler: + ldr r0,=UART0_LON_DriverIRQHandler + bx r0 + .size UART0_LON_IRQHandler, . - UART0_LON_IRQHandler + + .align 1 + .thumb_func + .weak UART0_RX_TX_IRQHandler + .type UART0_RX_TX_IRQHandler, %function +UART0_RX_TX_IRQHandler: + ldr r0,=UART0_RX_TX_DriverIRQHandler + bx r0 + .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART0_ERR_IRQHandler + .type UART0_ERR_IRQHandler, %function +UART0_ERR_IRQHandler: + ldr r0,=UART0_ERR_DriverIRQHandler + bx r0 + .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART1_RX_TX_IRQHandler + .type UART1_RX_TX_IRQHandler, %function +UART1_RX_TX_IRQHandler: + ldr r0,=UART1_RX_TX_DriverIRQHandler + bx r0 + .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART1_ERR_IRQHandler + .type UART1_ERR_IRQHandler, %function +UART1_ERR_IRQHandler: + ldr r0,=UART1_ERR_DriverIRQHandler + bx r0 + .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART2_RX_TX_IRQHandler + .type UART2_RX_TX_IRQHandler, %function +UART2_RX_TX_IRQHandler: + ldr r0,=UART2_RX_TX_DriverIRQHandler + bx r0 + .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART2_ERR_IRQHandler + .type UART2_ERR_IRQHandler, %function +UART2_ERR_IRQHandler: + ldr r0,=UART2_ERR_DriverIRQHandler + bx r0 + .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART3_RX_TX_IRQHandler + .type UART3_RX_TX_IRQHandler, %function +UART3_RX_TX_IRQHandler: + ldr r0,=UART3_RX_TX_DriverIRQHandler + bx r0 + .size UART3_RX_TX_IRQHandler, . - UART3_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART3_ERR_IRQHandler + .type UART3_ERR_IRQHandler, %function +UART3_ERR_IRQHandler: + ldr r0,=UART3_ERR_DriverIRQHandler + bx r0 + .size UART3_ERR_IRQHandler, . - UART3_ERR_IRQHandler + + .align 1 + .thumb_func + .weak SPI2_IRQHandler + .type SPI2_IRQHandler, %function +SPI2_IRQHandler: + ldr r0,=SPI2_DriverIRQHandler + bx r0 + .size SPI2_IRQHandler, . - SPI2_IRQHandler + + .align 1 + .thumb_func + .weak UART4_RX_TX_IRQHandler + .type UART4_RX_TX_IRQHandler, %function +UART4_RX_TX_IRQHandler: + ldr r0,=UART4_RX_TX_DriverIRQHandler + bx r0 + .size UART4_RX_TX_IRQHandler, . - UART4_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART4_ERR_IRQHandler + .type UART4_ERR_IRQHandler, %function +UART4_ERR_IRQHandler: + ldr r0,=UART4_ERR_DriverIRQHandler + bx r0 + .size UART4_ERR_IRQHandler, . - UART4_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART5_RX_TX_IRQHandler + .type UART5_RX_TX_IRQHandler, %function +UART5_RX_TX_IRQHandler: + ldr r0,=UART5_RX_TX_DriverIRQHandler + bx r0 + .size UART5_RX_TX_IRQHandler, . - UART5_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART5_ERR_IRQHandler + .type UART5_ERR_IRQHandler, %function +UART5_ERR_IRQHandler: + ldr r0,=UART5_ERR_DriverIRQHandler + bx r0 + .size UART5_ERR_IRQHandler, . - UART5_ERR_IRQHandler + + .align 1 + .thumb_func + .weak I2C2_IRQHandler + .type I2C2_IRQHandler, %function +I2C2_IRQHandler: + ldr r0,=I2C2_DriverIRQHandler + bx r0 + .size I2C2_IRQHandler, . - I2C2_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_ORed_Message_buffer_IRQHandler + .type CAN0_ORed_Message_buffer_IRQHandler, %function +CAN0_ORed_Message_buffer_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_ORed_Message_buffer_IRQHandler, . - CAN0_ORed_Message_buffer_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Bus_Off_IRQHandler + .type CAN0_Bus_Off_IRQHandler, %function +CAN0_Bus_Off_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Bus_Off_IRQHandler, . - CAN0_Bus_Off_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Error_IRQHandler + .type CAN0_Error_IRQHandler, %function +CAN0_Error_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Error_IRQHandler, . - CAN0_Error_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Tx_Warning_IRQHandler + .type CAN0_Tx_Warning_IRQHandler, %function +CAN0_Tx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Tx_Warning_IRQHandler, . - CAN0_Tx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Rx_Warning_IRQHandler + .type CAN0_Rx_Warning_IRQHandler, %function +CAN0_Rx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Rx_Warning_IRQHandler, . - CAN0_Rx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Wake_Up_IRQHandler + .type CAN0_Wake_Up_IRQHandler, %function +CAN0_Wake_Up_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Wake_Up_IRQHandler, . - CAN0_Wake_Up_IRQHandler + + .align 1 + .thumb_func + .weak SDHC_IRQHandler + .type SDHC_IRQHandler, %function +SDHC_IRQHandler: + ldr r0,=SDHC_DriverIRQHandler + bx r0 + .size SDHC_IRQHandler, . - SDHC_IRQHandler + + .align 1 + .thumb_func + .weak ENET_1588_Timer_IRQHandler + .type ENET_1588_Timer_IRQHandler, %function +ENET_1588_Timer_IRQHandler: + ldr r0,=ENET_1588_Timer_DriverIRQHandler + bx r0 + .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler + + .align 1 + .thumb_func + .weak ENET_Transmit_IRQHandler + .type ENET_Transmit_IRQHandler, %function +ENET_Transmit_IRQHandler: + ldr r0,=ENET_Transmit_DriverIRQHandler + bx r0 + .size ENET_Transmit_IRQHandler, . - ENET_Transmit_IRQHandler + + .align 1 + .thumb_func + .weak ENET_Receive_IRQHandler + .type ENET_Receive_IRQHandler, %function +ENET_Receive_IRQHandler: + ldr r0,=ENET_Receive_DriverIRQHandler + bx r0 + .size ENET_Receive_IRQHandler, . - ENET_Receive_IRQHandler + + .align 1 + .thumb_func + .weak ENET_Error_IRQHandler + .type ENET_Error_IRQHandler, %function +ENET_Error_IRQHandler: + ldr r0,=ENET_Error_DriverIRQHandler + bx r0 + .size ENET_Error_IRQHandler, . - ENET_Error_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler DMA4_DriverIRQHandler + def_irq_handler DMA5_DriverIRQHandler + def_irq_handler DMA6_DriverIRQHandler + def_irq_handler DMA7_DriverIRQHandler + def_irq_handler DMA8_DriverIRQHandler + def_irq_handler DMA9_DriverIRQHandler + def_irq_handler DMA10_DriverIRQHandler + def_irq_handler DMA11_DriverIRQHandler + def_irq_handler DMA12_DriverIRQHandler + def_irq_handler DMA13_DriverIRQHandler + def_irq_handler DMA14_DriverIRQHandler + def_irq_handler DMA15_DriverIRQHandler + def_irq_handler DMA_Error_DriverIRQHandler + def_irq_handler MCM_IRQHandler + def_irq_handler FTFE_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler WDOG_EWM_IRQHandler + def_irq_handler RNG_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler I2S0_Tx_DriverIRQHandler + def_irq_handler I2S0_Rx_DriverIRQHandler + def_irq_handler UART0_LON_DriverIRQHandler + def_irq_handler UART0_RX_TX_DriverIRQHandler + def_irq_handler UART0_ERR_DriverIRQHandler + def_irq_handler UART1_RX_TX_DriverIRQHandler + def_irq_handler UART1_ERR_DriverIRQHandler + def_irq_handler UART2_RX_TX_DriverIRQHandler + def_irq_handler UART2_ERR_DriverIRQHandler + def_irq_handler UART3_RX_TX_DriverIRQHandler + def_irq_handler UART3_ERR_DriverIRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler FTM2_IRQHandler + def_irq_handler CMT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USBDCD_IRQHandler + def_irq_handler Reserved71_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler SPI2_DriverIRQHandler + def_irq_handler UART4_RX_TX_DriverIRQHandler + def_irq_handler UART4_ERR_DriverIRQHandler + def_irq_handler UART5_RX_TX_DriverIRQHandler + def_irq_handler UART5_ERR_DriverIRQHandler + def_irq_handler CMP2_IRQHandler + def_irq_handler FTM3_IRQHandler + def_irq_handler DAC1_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler I2C2_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler SDHC_DriverIRQHandler + def_irq_handler ENET_1588_Timer_DriverIRQHandler + def_irq_handler ENET_Transmit_DriverIRQHandler + def_irq_handler ENET_Receive_DriverIRQHandler + def_irq_handler ENET_Error_DriverIRQHandler + + .end http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/src/clock_config.c ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/src/clock_config.c b/hw/bsp/frdm-k64f/src/clock_config.c new file mode 100644 index 0000000..ec7b050 --- /dev/null +++ b/hw/bsp/frdm-k64f/src/clock_config.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" + +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 120MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcSlow, /* Select IRC32k. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 7U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U, + }, + }, + .simConfig = + { + .pllFllSel = 1U, /* PLLFLLSEL select PLL. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 120000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC, false); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig); + CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ); + + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + + CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode, + g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv); + + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + + SystemCoreClock = g_defaultClockConfigRun.coreClock; +} http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/9a45975e/hw/bsp/frdm-k64f/src/clock_config.h ---------------------------------------------------------------------- diff --git a/hw/bsp/frdm-k64f/src/clock_config.h b/hw/bsp/frdm-k64f/src/clock_config.h new file mode 100644 index 0000000..050c3ab --- /dev/null +++ b/hw/bsp/frdm-k64f/src/clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 50000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */