This is an automated email from the ASF dual-hosted git repository. acassis pushed a commit to branch pr402 in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ac654d9f2fcd64ec107b7dd47b6d211cea4970e7 Author: Joshua Lange <jla...@2g-eng.com> AuthorDate: Tue Feb 4 17:51:43 2020 -0600 Added basic power management (sleep/stop/standby) for STM32H7 --- arch/arm/src/stm32h7/Make.defs | 7 ++ arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h | 45 ++++++++- arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h | 20 +++- arch/arm/src/stm32h7/stm32_pm.h | 122 +++++++++++++++++++++++ arch/arm/src/stm32h7/stm32_pminitialize.c | 78 +++++++++++++++ arch/arm/src/stm32h7/stm32_pmsleep.c | 101 +++++++++++++++++++ arch/arm/src/stm32h7/stm32_pmstandby.c | 99 +++++++++++++++++++ arch/arm/src/stm32h7/stm32_pmstop.c | 125 ++++++++++++++++++++++++ 8 files changed, 594 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 965f38a..a8e37aa 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -210,3 +210,10 @@ endif ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32_qencoder.c endif + +ifeq ($(CONFIG_PM),y) +CHIP_CSRCS += stm32_pmsleep.c stm32_pmstandby.c stm32_pmstop.c +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += stm32_pminitialize.c +endif +endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h index 693c0be..3c84e6b 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h @@ -89,7 +89,7 @@ #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable backup domain write protection */ #define PWR_CR1_FLPS (1 << 9) /* Bit 9: */ /* Bits 10-13: Reserved */ -#define PWR_CR1_SVOS_SHIFT (1 << 14) /* Bits 14-15: */ +#define PWR_CR1_SVOS_SHIFT (14) /* Bits 14-15: */ #define PWR_CR1_SVOS_MASK (3 << PWR_CR1_SVOS_SHIFT) /* 00: Reserved */ # define PWR_CR1_SVOS_S5 (1 << PWR_CR1_SVOS_SHIFT) /* 01: */ @@ -161,11 +161,52 @@ # define PWR_D3CR_VOS_SCALE_0 (3 << STM32_PWR_D3CR_VOS_SHIFT) /* Fmax = 480MHz with ODN */ /* Bits 15-31: Reserved */ - /* Power wakeup clear register (WKUPCR) */ +#define STM32_PWR_WKUPC1 (1 << 0) /* Bit 0: Clear wakeup pin flag for WKUP1 */ +#define STM32_PWR_WKUPC2 (1 << 1) /* Bit 1: Clear wakeup pin flag for WKUP2 */ +#define STM32_PWR_WKUPC3 (1 << 2) /* Bit 2: Clear wakeup pin flag for WKUP3 */ +#define STM32_PWR_WKUPC4 (1 << 3) /* Bit 3: Clear wakeup pin flag for WKUP4 */ +#define STM32_PWR_WKUPC5 (1 << 4) /* Bit 4: Clear wakeup pin flag for WKUP5 */ +#define STM32_PWR_WKUPC6 (1 << 5) /* Bit 5: Clear wakeup pin flag for WKUP6 */ + /* Bits 6-31: Reserved */ + /* Power wakeup flag register (WKUPFR) */ +#define STM32_PWR_WKUPF1 (1 << 0) /* Bit 0: Wakeup pin flag for WKUP1 */ +#define STM32_PWR_WKUPF2 (1 << 1) /* Bit 1: Wakeup pin flag for WKUP2 */ +#define STM32_PWR_WKUPF3 (1 << 2) /* Bit 2: Wakeup pin flag for WKUP3 */ +#define STM32_PWR_WKUPF4 (1 << 3) /* Bit 3: Wakeup pin flag for WKUP4 */ +#define STM32_PWR_WKUPF5 (1 << 4) /* Bit 4: Wakeup pin flag for WKUP5 */ +#define STM32_PWR_WKUPF6 (1 << 5) /* Bit 5: Wakeup pin flag for WKUP6 */ + /* Bits 6-31: Reserved */ + /* Power wakeup enable and polarity register (WKUPEPR) */ +#define STM32_PWR_WKUPEN1 (1 << 0) /* Bit 0: Enable wakeup pin WKUP1 */ +#define STM32_PWR_WKUPEN2 (1 << 1) /* Bit 1: Enable wakeup pin WKUP2 */ +#define STM32_PWR_WKUPEN3 (1 << 2) /* Bit 2: Enable wakeup pin WKUP3 */ +#define STM32_PWR_WKUPEN4 (1 << 3) /* Bit 3: Enable wakeup pin WKUP4 */ +#define STM32_PWR_WKUPEN5 (1 << 4) /* Bit 4: Enable wakeup pin WKUP5 */ +#define STM32_PWR_WKUPEN6 (1 << 5) /* Bit 5: Enable wakeup pin WKUP6 */ + /* Bits 6-7: Reserved */ +#define STM32_PWR_WKUPP1 (1 << 8) /* Bit 8: Wakeup pin polarity for WKUP1 */ +#define STM32_PWR_WKUPP2 (1 << 9) /* Bit 9: Wakeup pin polarity for WKUP2 */ +#define STM32_PWR_WKUPP3 (1 << 10) /* Bit 10: Wakeup pin polarity for WKUP3 */ +#define STM32_PWR_WKUPP4 (1 << 11) /* Bit 11: Wakeup pin polarity for WKUP4 */ +#define STM32_PWR_WKUPP5 (1 << 12) /* Bit 12: Wakeup pin polarity for WKUP5 */ +#define STM32_PWR_WKUPP6 (1 << 13) /* Bit 13: Wakeup pin polarity for WKUP6 */ + /* Bits 14-15: Reserved */ +#define STM32_PWR_WKUPPUPD1_SHIFT (16) /* Bits 16-17: Wakeup pin pull config for WKUP1 */ +#define STM32_PWR_WKUPPUPD2_SHIFT (18) /* Bits 18-19: Wakeup pin pull config for WKUP2 */ +#define STM32_PWR_WKUPPUPD3_SHIFT (20) /* Bits 20-21: Wakeup pin pull config for WKUP3 */ +#define STM32_PWR_WKUPPUPD4_SHIFT (22) /* Bits 22-23: Wakeup pin pull config for WKUP4 */ +#define STM32_PWR_WKUPPUPD5_SHIFT (24) /* Bits 24-25: Wakeup pin pull config for WKUP5 */ +#define STM32_PWR_WKUPPUPD6_SHIFT (26) /* Bits 26-27: Wakeup pin pull config for WKUP6 */ +# define STM32_PWR_WKUPPUPD_NONE (0) /* No pull-up */ +# define STM32_PWR_WKUPPUPD_PULLUP (1) /* Pull-up enabled */ +# define STM32_PWR_WKUPPUPD_PULLDN (2) /* Pull-down enabled */ + /* 3 is reserved */ + /* Bits 28-31: Reserved */ + #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index dacd1ed..b4afa87 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -828,7 +828,25 @@ /* TODO: D3 Autonomous mode register */ -/* TODO: RCC Reset Status register */ +/* RCC Reset Status register */ + + /* Bits 0-15: Reserved */ +#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ +#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ + /* Bit 18: Reserved */ +#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ +#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ +#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ +#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ +#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ + /* Bit 25: Reserved */ +#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ + /* Bit 27: Reserved */ +#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ + /* Bit 29: Reserved */ +#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ + /* Bit 31: Reserved */ /* AHB3 Peripheral Clock enable register */ diff --git a/arch/arm/src/stm32h7/stm32_pm.h b/arch/arm/src/stm32h7/stm32_pm.h new file mode 100644 index 0000000..5339ffe --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pm.h @@ -0,0 +1,122 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/stm32_pm.h + * + * Copyright (C) 2018 Haltian Ltd. All rights reserved. + * Author: Juha Niskanen <juha.niska...@haltian.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_STM32_PM_H +#define __ARCH_ARM_SRC_STM32H7_STM32_PM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> + +#include "chip.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_pmstop + * + * Description: + * Enter STOP mode. + * + * Input Parameters: + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power under-drive mode using the + * LPDS and LPUDS bits of the Power control register (PWR_CR1). + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmstop(bool lpds); + +/**************************************************************************** + * Name: stm32_pmstandby + * + * Description: + * Enter STANDBY mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmstandby(void); + +/**************************************************************************** + * Name: stm32_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode + * as soon as WFI or WFE instruction is executed. + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmsleep(bool sleeponexit); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_STM32H7_STM32_PM_H */ diff --git a/arch/arm/src/stm32h7/stm32_pminitialize.c b/arch/arm/src/stm32h7/stm32_pminitialize.c new file mode 100644 index 0000000..ffcd5d0 --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pminitialize.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_pminitialize.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gn...@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <nuttx/power/pm.h> + +#include "up_internal.h" +#include "stm32_pm.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_pminitialize(void) +{ + /* Then initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} + +#endif /* CONFIG_PM */ diff --git a/arch/arm/src/stm32h7/stm32_pmsleep.c b/arch/arm/src/stm32h7/stm32_pmsleep.c new file mode 100644 index 0000000..b7c92e4 --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pmsleep.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_pmsleep.c + * + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt <gn...@nuttx.org> + * Diego Sanchez <dsanc...@nx-engineering.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> + +#include "up_arch.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep mode + * as soon as WFI or WFE instruction is executed. + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmsleep(bool sleeponexit) +{ + uint32_t regval; + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval &= ~NVIC_SYSCON_SLEEPDEEP; + if (sleeponexit) + { + regval |= NVIC_SYSCON_SLEEPONEXIT; + } + else + { + regval &= ~NVIC_SYSCON_SLEEPONEXIT; + } + + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup interrupt or event occurs */ + +#ifdef CONFIG_PM_WFE + /* Mode: SLEEP + Entry with WFE */ + + asm("wfe"); +#else + /* Mode: SLEEP + Entry with WFI */ + + asm("wfi"); +#endif +} diff --git a/arch/arm/src/stm32h7/stm32_pmstandby.c b/arch/arm/src/stm32h7/stm32_pmstandby.c new file mode 100644 index 0000000..2486e1c --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pmstandby.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_pmstandby.c + * + * Copyright (C) 2018 Haltian Ltd. All rights reserved. + * Author: Juha Niskanen <juha.niska...@haltian.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> + +#include "up_arch.h" +#include "nvic.h" +#include "stm32_rcc.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmstandby + * + * Description: + * Enter STANDBY mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmstandby(void) +{ + uint32_t regval; + + /* Clear the wake-up flags before reseting. */ + + modifyreg32(STM32_PWR_CPUCR, 0, STM32_PWR_CPUCR_CSSF); + modifyreg32(STM32_PWR_WKUPCR, 0, STM32_PWR_WKUPC1 | STM32_PWR_WKUPC2 | + STM32_PWR_WKUPC3 | STM32_PWR_WKUPC4 | + STM32_PWR_WKUPC5 | STM32_PWR_WKUPC6); + + /* Clear reset flags. */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_RSR_RMVF); + + /* Set the domain Power Down Deep Sleep (PDDS) bits in the power control register. + * so that D1, D2, and D3 will go into the DStop state. */ + + modifyreg32(STM32_PWR_CPUCR, 0, STM32_PWR_CPUCR_PDDS_D1 | + STM32_PWR_CPUCR_PDDS_D2 | + STM32_PWR_CPUCR_PDDS_D3); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval |= NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup reset occurs */ + + asm("wfi"); +} diff --git a/arch/arm/src/stm32h7/stm32_pmstop.c b/arch/arm/src/stm32h7/stm32_pmstop.c new file mode 100644 index 0000000..6159e8c --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pmstop.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_pmstop.c + * + * Copyright (C) 2018 Haltian Ltd. All rights reserved. + * Author: Juha Niskanen <juha.niska...@haltian.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdbool.h> + +#include "up_arch.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmstop + * + * Description: + * Enter STOP mode. + * + * Input Parameters: + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power under-drive mode using the + * LPDS and LPUDS bits of the Power control register (PWR_CR1). + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmstop(bool lpds) +{ + uint32_t regval; + + /* Clear the Low Power Deep Sleep (LPDS) bit in the CPU power control register. + */ + + regval = getreg32(STM32_PWR_CR1); + regval &= ~(PWR_CR1_LPDS | PWR_CR1_SVOS_MASK); + + /* Set low-power regulator mode and voltage scaling. */ + + if (lpds) + { + regval |= PWR_CR1_LPDS | PWR_CR1_SVOS_S5; + } + else + { + /* Set regulator to normal (S3) mode */ + + regval |= PWR_CR1_SVOS_S3; + } + + putreg32(regval, STM32_PWR_CR1); + + /* Clear the domain standby bits so D1, D2 and D3 remain in DStop mode */ + + regval = getreg32(STM32_PWR_CPUCR); + regval &= ~(STM32_PWR_CPUCR_PDDS_D1 | STM32_PWR_CPUCR_PDDS_D2 | STM32_PWR_CPUCR_PDDS_D3); + putreg32(regval, STM32_PWR_CPUCR); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval |= NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); + + /* Sleep until the wakeup interrupt or event occurs */ + +#ifdef CONFIG_PM_WFE + /* Mode: SLEEP + Entry with WFE */ + + asm volatile ("wfe"); +#else + /* Mode: SLEEP + Entry with WFI */ + + asm volatile ("wfi"); +#endif + + /* Clear deep sleep bits, so that MCU does not go into deep sleep in idle. */ + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + + regval = getreg32(NVIC_SYSCON); + regval &= ~NVIC_SYSCON_SLEEPDEEP; + putreg32(regval, NVIC_SYSCON); +}